2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
16 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
17 #include <asm/fsp/fsp_support.h>
19 #include "pci_internal.h"
21 DECLARE_GLOBAL_DATA_PTR
;
23 int pci_get_bus(int busnum
, struct udevice
**busp
)
27 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, busp
);
29 /* Since buses may not be numbered yet try a little harder with bus 0 */
31 ret
= uclass_first_device_err(UCLASS_PCI
, busp
);
34 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, busp
);
40 struct udevice
*pci_get_controller(struct udevice
*dev
)
42 while (device_is_on_pci_bus(dev
))
48 pci_dev_t
dm_pci_get_bdf(struct udevice
*dev
)
50 struct pci_child_platdata
*pplat
= dev_get_parent_platdata(dev
);
51 struct udevice
*bus
= dev
->parent
;
53 return PCI_ADD_BUS(bus
->seq
, pplat
->devfn
);
57 * pci_get_bus_max() - returns the bus number of the last active bus
59 * @return last bus number, or -1 if no active buses
61 static int pci_get_bus_max(void)
67 ret
= uclass_get(UCLASS_PCI
, &uc
);
68 uclass_foreach_dev(bus
, uc
) {
73 debug("%s: ret=%d\n", __func__
, ret
);
78 int pci_last_busno(void)
80 return pci_get_bus_max();
83 int pci_get_ff(enum pci_size_t size
)
95 int pci_bus_find_devfn(struct udevice
*bus
, pci_dev_t find_devfn
,
96 struct udevice
**devp
)
100 for (device_find_first_child(bus
, &dev
);
102 device_find_next_child(&dev
)) {
103 struct pci_child_platdata
*pplat
;
105 pplat
= dev_get_parent_platdata(dev
);
106 if (pplat
&& pplat
->devfn
== find_devfn
) {
115 int dm_pci_bus_find_bdf(pci_dev_t bdf
, struct udevice
**devp
)
120 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
123 return pci_bus_find_devfn(bus
, PCI_MASK_BUS(bdf
), devp
);
126 static int pci_device_matches_ids(struct udevice
*dev
,
127 struct pci_device_id
*ids
)
129 struct pci_child_platdata
*pplat
;
132 pplat
= dev_get_parent_platdata(dev
);
135 for (i
= 0; ids
[i
].vendor
!= 0; i
++) {
136 if (pplat
->vendor
== ids
[i
].vendor
&&
137 pplat
->device
== ids
[i
].device
)
144 int pci_bus_find_devices(struct udevice
*bus
, struct pci_device_id
*ids
,
145 int *indexp
, struct udevice
**devp
)
149 /* Scan all devices on this bus */
150 for (device_find_first_child(bus
, &dev
);
152 device_find_next_child(&dev
)) {
153 if (pci_device_matches_ids(dev
, ids
) >= 0) {
154 if ((*indexp
)-- <= 0) {
164 int pci_find_device_id(struct pci_device_id
*ids
, int index
,
165 struct udevice
**devp
)
169 /* Scan all known buses */
170 for (uclass_first_device(UCLASS_PCI
, &bus
);
172 uclass_next_device(&bus
)) {
173 if (!pci_bus_find_devices(bus
, ids
, &index
, devp
))
181 static int dm_pci_bus_find_device(struct udevice
*bus
, unsigned int vendor
,
182 unsigned int device
, int *indexp
,
183 struct udevice
**devp
)
185 struct pci_child_platdata
*pplat
;
188 for (device_find_first_child(bus
, &dev
);
190 device_find_next_child(&dev
)) {
191 pplat
= dev_get_parent_platdata(dev
);
192 if (pplat
->vendor
== vendor
&& pplat
->device
== device
) {
203 int dm_pci_find_device(unsigned int vendor
, unsigned int device
, int index
,
204 struct udevice
**devp
)
208 /* Scan all known buses */
209 for (uclass_first_device(UCLASS_PCI
, &bus
);
211 uclass_next_device(&bus
)) {
212 if (!dm_pci_bus_find_device(bus
, vendor
, device
, &index
, devp
))
213 return device_probe(*devp
);
220 int dm_pci_find_class(uint find_class
, int index
, struct udevice
**devp
)
224 /* Scan all known buses */
225 for (pci_find_first_device(&dev
);
227 pci_find_next_device(&dev
)) {
228 struct pci_child_platdata
*pplat
= dev_get_parent_platdata(dev
);
230 if (pplat
->class == find_class
&& !index
--) {
232 return device_probe(*devp
);
240 int pci_bus_write_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
241 unsigned long value
, enum pci_size_t size
)
243 struct dm_pci_ops
*ops
;
245 ops
= pci_get_ops(bus
);
246 if (!ops
->write_config
)
248 return ops
->write_config(bus
, bdf
, offset
, value
, size
);
251 int pci_bus_clrset_config32(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
257 ret
= pci_bus_read_config(bus
, bdf
, offset
, &val
, PCI_SIZE_32
);
263 return pci_bus_write_config(bus
, bdf
, offset
, val
, PCI_SIZE_32
);
266 int pci_write_config(pci_dev_t bdf
, int offset
, unsigned long value
,
267 enum pci_size_t size
)
272 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
276 return pci_bus_write_config(bus
, bdf
, offset
, value
, size
);
279 int dm_pci_write_config(struct udevice
*dev
, int offset
, unsigned long value
,
280 enum pci_size_t size
)
284 for (bus
= dev
; device_is_on_pci_bus(bus
);)
286 return pci_bus_write_config(bus
, dm_pci_get_bdf(dev
), offset
, value
,
290 int pci_write_config32(pci_dev_t bdf
, int offset
, u32 value
)
292 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_32
);
295 int pci_write_config16(pci_dev_t bdf
, int offset
, u16 value
)
297 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_16
);
300 int pci_write_config8(pci_dev_t bdf
, int offset
, u8 value
)
302 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_8
);
305 int dm_pci_write_config8(struct udevice
*dev
, int offset
, u8 value
)
307 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_8
);
310 int dm_pci_write_config16(struct udevice
*dev
, int offset
, u16 value
)
312 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_16
);
315 int dm_pci_write_config32(struct udevice
*dev
, int offset
, u32 value
)
317 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_32
);
320 int pci_bus_read_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
321 unsigned long *valuep
, enum pci_size_t size
)
323 struct dm_pci_ops
*ops
;
325 ops
= pci_get_ops(bus
);
326 if (!ops
->read_config
)
328 return ops
->read_config(bus
, bdf
, offset
, valuep
, size
);
331 int pci_read_config(pci_dev_t bdf
, int offset
, unsigned long *valuep
,
332 enum pci_size_t size
)
337 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
341 return pci_bus_read_config(bus
, bdf
, offset
, valuep
, size
);
344 int dm_pci_read_config(struct udevice
*dev
, int offset
, unsigned long *valuep
,
345 enum pci_size_t size
)
349 for (bus
= dev
; device_is_on_pci_bus(bus
);)
351 return pci_bus_read_config(bus
, dm_pci_get_bdf(dev
), offset
, valuep
,
355 int pci_read_config32(pci_dev_t bdf
, int offset
, u32
*valuep
)
360 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_32
);
368 int pci_read_config16(pci_dev_t bdf
, int offset
, u16
*valuep
)
373 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_16
);
381 int pci_read_config8(pci_dev_t bdf
, int offset
, u8
*valuep
)
386 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_8
);
394 int dm_pci_read_config8(struct udevice
*dev
, int offset
, u8
*valuep
)
399 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_8
);
407 int dm_pci_read_config16(struct udevice
*dev
, int offset
, u16
*valuep
)
412 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_16
);
420 int dm_pci_read_config32(struct udevice
*dev
, int offset
, u32
*valuep
)
425 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_32
);
433 int dm_pci_clrset_config8(struct udevice
*dev
, int offset
, u32 clr
, u32 set
)
438 ret
= dm_pci_read_config8(dev
, offset
, &val
);
444 return dm_pci_write_config8(dev
, offset
, val
);
447 int dm_pci_clrset_config16(struct udevice
*dev
, int offset
, u32 clr
, u32 set
)
452 ret
= dm_pci_read_config16(dev
, offset
, &val
);
458 return dm_pci_write_config16(dev
, offset
, val
);
461 int dm_pci_clrset_config32(struct udevice
*dev
, int offset
, u32 clr
, u32 set
)
466 ret
= dm_pci_read_config32(dev
, offset
, &val
);
472 return dm_pci_write_config32(dev
, offset
, val
);
475 static void set_vga_bridge_bits(struct udevice
*dev
)
477 struct udevice
*parent
= dev
->parent
;
480 while (parent
->seq
!= 0) {
481 dm_pci_read_config16(parent
, PCI_BRIDGE_CONTROL
, &bc
);
482 bc
|= PCI_BRIDGE_CTL_VGA
;
483 dm_pci_write_config16(parent
, PCI_BRIDGE_CONTROL
, bc
);
484 parent
= parent
->parent
;
488 int pci_auto_config_devices(struct udevice
*bus
)
490 struct pci_controller
*hose
= bus
->uclass_priv
;
491 struct pci_child_platdata
*pplat
;
492 unsigned int sub_bus
;
497 debug("%s: start\n", __func__
);
498 pciauto_config_init(hose
);
499 for (ret
= device_find_first_child(bus
, &dev
);
501 ret
= device_find_next_child(&dev
)) {
502 unsigned int max_bus
;
505 debug("%s: device %s\n", __func__
, dev
->name
);
506 ret
= dm_pciauto_config_device(dev
);
510 sub_bus
= max(sub_bus
, max_bus
);
512 pplat
= dev_get_parent_platdata(dev
);
513 if (pplat
->class == (PCI_CLASS_DISPLAY_VGA
<< 8))
514 set_vga_bridge_bits(dev
);
516 debug("%s: done\n", __func__
);
521 int pci_generic_mmap_write_config(
523 int (*addr_f
)(struct udevice
*bus
, pci_dev_t bdf
, uint offset
, void **addrp
),
527 enum pci_size_t size
)
531 if (addr_f(bus
, bdf
, offset
, &address
) < 0)
536 writeb(value
, address
);
539 writew(value
, address
);
542 writel(value
, address
);
549 int pci_generic_mmap_read_config(
551 int (*addr_f
)(struct udevice
*bus
, pci_dev_t bdf
, uint offset
, void **addrp
),
555 enum pci_size_t size
)
559 if (addr_f(bus
, bdf
, offset
, &address
) < 0) {
560 *valuep
= pci_get_ff(size
);
566 *valuep
= readb(address
);
569 *valuep
= readw(address
);
572 *valuep
= readl(address
);
579 int dm_pci_hose_probe_bus(struct udevice
*bus
)
584 debug("%s\n", __func__
);
586 sub_bus
= pci_get_bus_max() + 1;
587 debug("%s: bus = %d/%s\n", __func__
, sub_bus
, bus
->name
);
588 dm_pciauto_prescan_setup_bridge(bus
, sub_bus
);
590 ret
= device_probe(bus
);
592 debug("%s: Cannot probe bus %s: %d\n", __func__
, bus
->name
,
596 if (sub_bus
!= bus
->seq
) {
597 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
598 __func__
, bus
->name
, bus
->seq
, sub_bus
);
601 sub_bus
= pci_get_bus_max();
602 dm_pciauto_postscan_setup_bridge(bus
, sub_bus
);
608 * pci_match_one_device - Tell if a PCI device structure has a matching
609 * PCI device id structure
610 * @id: single PCI device id structure to match
611 * @find: the PCI device id structure to match against
613 * Returns true if the finding pci_device_id structure matched or false if
616 static bool pci_match_one_id(const struct pci_device_id
*id
,
617 const struct pci_device_id
*find
)
619 if ((id
->vendor
== PCI_ANY_ID
|| id
->vendor
== find
->vendor
) &&
620 (id
->device
== PCI_ANY_ID
|| id
->device
== find
->device
) &&
621 (id
->subvendor
== PCI_ANY_ID
|| id
->subvendor
== find
->subvendor
) &&
622 (id
->subdevice
== PCI_ANY_ID
|| id
->subdevice
== find
->subdevice
) &&
623 !((id
->class ^ find
->class) & id
->class_mask
))
630 * pci_find_and_bind_driver() - Find and bind the right PCI driver
632 * This only looks at certain fields in the descriptor.
634 * @parent: Parent bus
635 * @find_id: Specification of the driver to find
636 * @bdf: Bus/device/function addreess - see PCI_BDF()
637 * @devp: Returns a pointer to the device created
638 * @return 0 if OK, -EPERM if the device is not needed before relocation and
639 * therefore was not created, other -ve value on error
641 static int pci_find_and_bind_driver(struct udevice
*parent
,
642 struct pci_device_id
*find_id
,
643 pci_dev_t bdf
, struct udevice
**devp
)
645 struct pci_driver_entry
*start
, *entry
;
654 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__
,
655 find_id
->vendor
, find_id
->device
);
656 start
= ll_entry_start(struct pci_driver_entry
, pci_driver_entry
);
657 n_ents
= ll_entry_count(struct pci_driver_entry
, pci_driver_entry
);
658 for (entry
= start
; entry
!= start
+ n_ents
; entry
++) {
659 const struct pci_device_id
*id
;
661 const struct driver
*drv
;
663 for (id
= entry
->match
;
664 id
->vendor
|| id
->subvendor
|| id
->class_mask
;
666 if (!pci_match_one_id(id
, find_id
))
672 * In the pre-relocation phase, we only bind devices
673 * whose driver has the DM_FLAG_PRE_RELOC set, to save
674 * precious memory space as on some platforms as that
675 * space is pretty limited (ie: using Cache As RAM).
677 if (!(gd
->flags
& GD_FLG_RELOC
) &&
678 !(drv
->flags
& DM_FLAG_PRE_RELOC
))
682 * We could pass the descriptor to the driver as
683 * platdata (instead of NULL) and allow its bind()
684 * method to return -ENOENT if it doesn't support this
685 * device. That way we could continue the search to
686 * find another driver. For now this doesn't seem
687 * necesssary, so just bind the first match.
689 ret
= device_bind(parent
, drv
, drv
->name
, NULL
, -1,
693 debug("%s: Match found: %s\n", __func__
, drv
->name
);
694 dev
->driver_data
= find_id
->driver_data
;
700 bridge
= (find_id
->class >> 8) == PCI_CLASS_BRIDGE_PCI
;
702 * In the pre-relocation phase, we only bind bridge devices to save
703 * precious memory space as on some platforms as that space is pretty
704 * limited (ie: using Cache As RAM).
706 if (!(gd
->flags
& GD_FLG_RELOC
) && !bridge
)
709 /* Bind a generic driver so that the device can be used */
710 sprintf(name
, "pci_%x:%x.%x", parent
->seq
, PCI_DEV(bdf
),
715 drv
= bridge
? "pci_bridge_drv" : "pci_generic_drv";
717 ret
= device_bind_driver(parent
, drv
, str
, devp
);
719 debug("%s: Failed to bind generic driver: %d\n", __func__
, ret
);
723 debug("%s: No match found: bound generic driver instead\n", __func__
);
728 debug("%s: No match found: error %d\n", __func__
, ret
);
732 int pci_bind_bus_devices(struct udevice
*bus
)
734 ulong vendor
, device
;
741 end
= PCI_BDF(bus
->seq
, PCI_MAX_PCI_DEVICES
- 1,
742 PCI_MAX_PCI_FUNCTIONS
- 1);
743 for (bdf
= PCI_BDF(bus
->seq
, 0, 0); bdf
<= end
;
744 bdf
+= PCI_BDF(0, 0, 1)) {
745 struct pci_child_platdata
*pplat
;
749 if (PCI_FUNC(bdf
) && !found_multi
)
751 /* Check only the first access, we don't expect problems */
752 ret
= pci_bus_read_config(bus
, bdf
, PCI_HEADER_TYPE
,
753 &header_type
, PCI_SIZE_8
);
756 pci_bus_read_config(bus
, bdf
, PCI_VENDOR_ID
, &vendor
,
758 if (vendor
== 0xffff || vendor
== 0x0000)
762 found_multi
= header_type
& 0x80;
764 debug("%s: bus %d/%s: found device %x, function %d\n", __func__
,
765 bus
->seq
, bus
->name
, PCI_DEV(bdf
), PCI_FUNC(bdf
));
766 pci_bus_read_config(bus
, bdf
, PCI_DEVICE_ID
, &device
,
768 pci_bus_read_config(bus
, bdf
, PCI_CLASS_REVISION
, &class,
772 /* Find this device in the device tree */
773 ret
= pci_bus_find_devfn(bus
, PCI_MASK_BUS(bdf
), &dev
);
775 /* If nothing in the device tree, bind a device */
776 if (ret
== -ENODEV
) {
777 struct pci_device_id find_id
;
780 memset(&find_id
, '\0', sizeof(find_id
));
781 find_id
.vendor
= vendor
;
782 find_id
.device
= device
;
783 find_id
.class = class;
784 if ((header_type
& 0x7f) == PCI_HEADER_TYPE_NORMAL
) {
785 pci_bus_read_config(bus
, bdf
,
786 PCI_SUBSYSTEM_VENDOR_ID
,
788 find_id
.subvendor
= val
& 0xffff;
789 find_id
.subdevice
= val
>> 16;
791 ret
= pci_find_and_bind_driver(bus
, &find_id
, bdf
,
799 /* Update the platform data */
800 pplat
= dev_get_parent_platdata(dev
);
801 pplat
->devfn
= PCI_MASK_BUS(bdf
);
802 pplat
->vendor
= vendor
;
803 pplat
->device
= device
;
804 pplat
->class = class;
809 printf("Cannot read bus configuration: %d\n", ret
);
814 static int decode_regions(struct pci_controller
*hose
, ofnode parent_node
,
817 int pci_addr_cells
, addr_cells
, size_cells
;
818 phys_addr_t base
= 0, size
;
819 int cells_per_record
;
824 prop
= ofnode_get_property(node
, "ranges", &len
);
827 pci_addr_cells
= ofnode_read_simple_addr_cells(node
);
828 addr_cells
= ofnode_read_simple_addr_cells(parent_node
);
829 size_cells
= ofnode_read_simple_size_cells(node
);
831 /* PCI addresses are always 3-cells */
833 cells_per_record
= pci_addr_cells
+ addr_cells
+ size_cells
;
834 hose
->region_count
= 0;
835 debug("%s: len=%d, cells_per_record=%d\n", __func__
, len
,
837 for (i
= 0; i
< MAX_PCI_REGIONS
; i
++, len
-= cells_per_record
) {
838 u64 pci_addr
, addr
, size
;
844 if (len
< cells_per_record
)
846 flags
= fdt32_to_cpu(prop
[0]);
847 space_code
= (flags
>> 24) & 3;
848 pci_addr
= fdtdec_get_number(prop
+ 1, 2);
849 prop
+= pci_addr_cells
;
850 addr
= fdtdec_get_number(prop
, addr_cells
);
852 size
= fdtdec_get_number(prop
, size_cells
);
854 debug("%s: region %d, pci_addr=%" PRIx64
", addr=%" PRIx64
855 ", size=%" PRIx64
", space_code=%d\n", __func__
,
856 hose
->region_count
, pci_addr
, addr
, size
, space_code
);
857 if (space_code
& 2) {
858 type
= flags
& (1U << 30) ? PCI_REGION_PREFETCH
:
860 } else if (space_code
& 1) {
861 type
= PCI_REGION_IO
;
866 for (i
= 0; i
< hose
->region_count
; i
++) {
867 if (hose
->regions
[i
].flags
== type
)
871 pos
= hose
->region_count
++;
872 debug(" - type=%d, pos=%d\n", type
, pos
);
873 pci_set_region(hose
->regions
+ pos
, pci_addr
, addr
, size
, type
);
876 /* Add a region for our local memory */
878 #ifdef CONFIG_SYS_SDRAM_BASE
879 base
= CONFIG_SYS_SDRAM_BASE
;
881 if (gd
->pci_ram_top
&& gd
->pci_ram_top
< base
+ size
)
882 size
= gd
->pci_ram_top
- base
;
883 pci_set_region(hose
->regions
+ hose
->region_count
++, base
, base
,
884 size
, PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
889 static int pci_uclass_pre_probe(struct udevice
*bus
)
891 struct pci_controller
*hose
;
894 debug("%s, bus=%d/%s, parent=%s\n", __func__
, bus
->seq
, bus
->name
,
896 hose
= bus
->uclass_priv
;
898 /* For bridges, use the top-level PCI controller */
899 if (!device_is_on_pci_bus(bus
)) {
901 ret
= decode_regions(hose
, dev_ofnode(bus
->parent
),
904 debug("%s: Cannot decode regions\n", __func__
);
908 struct pci_controller
*parent_hose
;
910 parent_hose
= dev_get_uclass_priv(bus
->parent
);
911 hose
->ctlr
= parent_hose
->bus
;
914 hose
->first_busno
= bus
->seq
;
915 hose
->last_busno
= bus
->seq
;
920 static int pci_uclass_post_probe(struct udevice
*bus
)
924 debug("%s: probing bus %d\n", __func__
, bus
->seq
);
925 ret
= pci_bind_bus_devices(bus
);
929 #ifdef CONFIG_PCI_PNP
930 ret
= pci_auto_config_devices(bus
);
935 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
937 * Per Intel FSP specification, we should call FSP notify API to
938 * inform FSP that PCI enumeration has been done so that FSP will
939 * do any necessary initialization as required by the chipset's
940 * BIOS Writer's Guide (BWG).
942 * Unfortunately we have to put this call here as with driver model,
943 * the enumeration is all done on a lazy basis as needed, so until
944 * something is touched on PCI it won't happen.
946 * Note we only call this 1) after U-Boot is relocated, and 2)
947 * root bus has finished probing.
949 if ((gd
->flags
& GD_FLG_RELOC
) && (bus
->seq
== 0)) {
950 ret
= fsp_init_phase_pci();
959 static int pci_uclass_child_post_bind(struct udevice
*dev
)
961 struct pci_child_platdata
*pplat
;
962 struct fdt_pci_addr addr
;
965 if (!dev_of_valid(dev
))
969 * We could read vendor, device, class if available. But for now we
970 * just check the address.
972 pplat
= dev_get_parent_platdata(dev
);
973 ret
= ofnode_read_pci_addr(dev_ofnode(dev
), FDT_PCI_SPACE_CONFIG
, "reg",
980 /* extract the devfn from fdt_pci_addr */
981 pplat
->devfn
= addr
.phys_hi
& 0xff00;
987 static int pci_bridge_read_config(struct udevice
*bus
, pci_dev_t bdf
,
988 uint offset
, ulong
*valuep
,
989 enum pci_size_t size
)
991 struct pci_controller
*hose
= bus
->uclass_priv
;
993 return pci_bus_read_config(hose
->ctlr
, bdf
, offset
, valuep
, size
);
996 static int pci_bridge_write_config(struct udevice
*bus
, pci_dev_t bdf
,
997 uint offset
, ulong value
,
998 enum pci_size_t size
)
1000 struct pci_controller
*hose
= bus
->uclass_priv
;
1002 return pci_bus_write_config(hose
->ctlr
, bdf
, offset
, value
, size
);
1005 static int skip_to_next_device(struct udevice
*bus
, struct udevice
**devp
)
1007 struct udevice
*dev
;
1011 * Scan through all the PCI controllers. On x86 there will only be one
1012 * but that is not necessarily true on other hardware.
1015 device_find_first_child(bus
, &dev
);
1020 ret
= uclass_next_device(&bus
);
1028 int pci_find_next_device(struct udevice
**devp
)
1030 struct udevice
*child
= *devp
;
1031 struct udevice
*bus
= child
->parent
;
1034 /* First try all the siblings */
1037 device_find_next_child(&child
);
1044 /* We ran out of siblings. Try the next bus */
1045 ret
= uclass_next_device(&bus
);
1049 return bus
? skip_to_next_device(bus
, devp
) : 0;
1052 int pci_find_first_device(struct udevice
**devp
)
1054 struct udevice
*bus
;
1058 ret
= uclass_first_device(UCLASS_PCI
, &bus
);
1062 return skip_to_next_device(bus
, devp
);
1065 ulong
pci_conv_32_to_size(ulong value
, uint offset
, enum pci_size_t size
)
1069 return (value
>> ((offset
& 3) * 8)) & 0xff;
1071 return (value
>> ((offset
& 2) * 8)) & 0xffff;
1077 ulong
pci_conv_size_to_32(ulong old
, ulong value
, uint offset
,
1078 enum pci_size_t size
)
1081 uint val_mask
, shift
;
1096 shift
= (offset
& off_mask
) * 8;
1097 ldata
= (value
& val_mask
) << shift
;
1098 mask
= val_mask
<< shift
;
1099 value
= (old
& ~mask
) | ldata
;
1104 int pci_get_regions(struct udevice
*dev
, struct pci_region
**iop
,
1105 struct pci_region
**memp
, struct pci_region
**prefp
)
1107 struct udevice
*bus
= pci_get_controller(dev
);
1108 struct pci_controller
*hose
= dev_get_uclass_priv(bus
);
1114 for (i
= 0; i
< hose
->region_count
; i
++) {
1115 switch (hose
->regions
[i
].flags
) {
1117 if (!*iop
|| (*iop
)->size
< hose
->regions
[i
].size
)
1118 *iop
= hose
->regions
+ i
;
1120 case PCI_REGION_MEM
:
1121 if (!*memp
|| (*memp
)->size
< hose
->regions
[i
].size
)
1122 *memp
= hose
->regions
+ i
;
1124 case (PCI_REGION_MEM
| PCI_REGION_PREFETCH
):
1125 if (!*prefp
|| (*prefp
)->size
< hose
->regions
[i
].size
)
1126 *prefp
= hose
->regions
+ i
;
1131 return (*iop
!= NULL
) + (*memp
!= NULL
) + (*prefp
!= NULL
);
1134 u32
dm_pci_read_bar32(struct udevice
*dev
, int barnum
)
1139 bar
= PCI_BASE_ADDRESS_0
+ barnum
* 4;
1140 dm_pci_read_config32(dev
, bar
, &addr
);
1141 if (addr
& PCI_BASE_ADDRESS_SPACE_IO
)
1142 return addr
& PCI_BASE_ADDRESS_IO_MASK
;
1144 return addr
& PCI_BASE_ADDRESS_MEM_MASK
;
1147 void dm_pci_write_bar32(struct udevice
*dev
, int barnum
, u32 addr
)
1151 bar
= PCI_BASE_ADDRESS_0
+ barnum
* 4;
1152 dm_pci_write_config32(dev
, bar
, addr
);
1155 static int _dm_pci_bus_to_phys(struct udevice
*ctlr
,
1156 pci_addr_t bus_addr
, unsigned long flags
,
1157 unsigned long skip_mask
, phys_addr_t
*pa
)
1159 struct pci_controller
*hose
= dev_get_uclass_priv(ctlr
);
1160 struct pci_region
*res
;
1163 for (i
= 0; i
< hose
->region_count
; i
++) {
1164 res
= &hose
->regions
[i
];
1166 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
1169 if (res
->flags
& skip_mask
)
1172 if (bus_addr
>= res
->bus_start
&&
1173 (bus_addr
- res
->bus_start
) < res
->size
) {
1174 *pa
= (bus_addr
- res
->bus_start
+ res
->phys_start
);
1182 phys_addr_t
dm_pci_bus_to_phys(struct udevice
*dev
, pci_addr_t bus_addr
,
1183 unsigned long flags
)
1185 phys_addr_t phys_addr
= 0;
1186 struct udevice
*ctlr
;
1189 /* The root controller has the region information */
1190 ctlr
= pci_get_controller(dev
);
1193 * if PCI_REGION_MEM is set we do a two pass search with preference
1194 * on matches that don't have PCI_REGION_SYS_MEMORY set
1196 if ((flags
& PCI_REGION_TYPE
) == PCI_REGION_MEM
) {
1197 ret
= _dm_pci_bus_to_phys(ctlr
, bus_addr
,
1198 flags
, PCI_REGION_SYS_MEMORY
,
1204 ret
= _dm_pci_bus_to_phys(ctlr
, bus_addr
, flags
, 0, &phys_addr
);
1207 puts("pci_hose_bus_to_phys: invalid physical address\n");
1212 int _dm_pci_phys_to_bus(struct udevice
*dev
, phys_addr_t phys_addr
,
1213 unsigned long flags
, unsigned long skip_mask
,
1216 struct pci_region
*res
;
1217 struct udevice
*ctlr
;
1218 pci_addr_t bus_addr
;
1220 struct pci_controller
*hose
;
1222 /* The root controller has the region information */
1223 ctlr
= pci_get_controller(dev
);
1224 hose
= dev_get_uclass_priv(ctlr
);
1226 for (i
= 0; i
< hose
->region_count
; i
++) {
1227 res
= &hose
->regions
[i
];
1229 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
1232 if (res
->flags
& skip_mask
)
1235 bus_addr
= phys_addr
- res
->phys_start
+ res
->bus_start
;
1237 if (bus_addr
>= res
->bus_start
&&
1238 (bus_addr
- res
->bus_start
) < res
->size
) {
1247 pci_addr_t
dm_pci_phys_to_bus(struct udevice
*dev
, phys_addr_t phys_addr
,
1248 unsigned long flags
)
1250 pci_addr_t bus_addr
= 0;
1254 * if PCI_REGION_MEM is set we do a two pass search with preference
1255 * on matches that don't have PCI_REGION_SYS_MEMORY set
1257 if ((flags
& PCI_REGION_TYPE
) == PCI_REGION_MEM
) {
1258 ret
= _dm_pci_phys_to_bus(dev
, phys_addr
, flags
,
1259 PCI_REGION_SYS_MEMORY
, &bus_addr
);
1264 ret
= _dm_pci_phys_to_bus(dev
, phys_addr
, flags
, 0, &bus_addr
);
1267 puts("pci_hose_phys_to_bus: invalid physical address\n");
1272 void *dm_pci_map_bar(struct udevice
*dev
, int bar
, int flags
)
1274 pci_addr_t pci_bus_addr
;
1277 /* read BAR address */
1278 dm_pci_read_config32(dev
, bar
, &bar_response
);
1279 pci_bus_addr
= (pci_addr_t
)(bar_response
& ~0xf);
1282 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1283 * isn't actualy used on any platform because u-boot assumes a static
1284 * linear mapping. In the future, this could read the BAR size
1285 * and pass that as the size if needed.
1287 return dm_pci_bus_to_virt(dev
, pci_bus_addr
, flags
, 0, MAP_NOCACHE
);
1290 UCLASS_DRIVER(pci
) = {
1293 .flags
= DM_UC_FLAG_SEQ_ALIAS
,
1294 .post_bind
= dm_scan_fdt_dev
,
1295 .pre_probe
= pci_uclass_pre_probe
,
1296 .post_probe
= pci_uclass_post_probe
,
1297 .child_post_bind
= pci_uclass_child_post_bind
,
1298 .per_device_auto_alloc_size
= sizeof(struct pci_controller
),
1299 .per_child_platdata_auto_alloc_size
=
1300 sizeof(struct pci_child_platdata
),
1303 static const struct dm_pci_ops pci_bridge_ops
= {
1304 .read_config
= pci_bridge_read_config
,
1305 .write_config
= pci_bridge_write_config
,
1308 static const struct udevice_id pci_bridge_ids
[] = {
1309 { .compatible
= "pci-bridge" },
1313 U_BOOT_DRIVER(pci_bridge_drv
) = {
1314 .name
= "pci_bridge_drv",
1316 .of_match
= pci_bridge_ids
,
1317 .ops
= &pci_bridge_ops
,
1320 UCLASS_DRIVER(pci_generic
) = {
1321 .id
= UCLASS_PCI_GENERIC
,
1322 .name
= "pci_generic",
1325 static const struct udevice_id pci_generic_ids
[] = {
1326 { .compatible
= "pci-generic" },
1330 U_BOOT_DRIVER(pci_generic_drv
) = {
1331 .name
= "pci_generic_drv",
1332 .id
= UCLASS_PCI_GENERIC
,
1333 .of_match
= pci_generic_ids
,
1338 struct udevice
*bus
;
1341 * Enumerate all known controller devices. Enumeration has the side-
1342 * effect of probing them, so PCIe devices will be enumerated too.
1344 for (uclass_first_device(UCLASS_PCI
, &bus
);
1346 uclass_next_device(&bus
)) {