drivers/pci/pci-uclass.c

   1 /*
   2  * Copyright (c) 2014 Google, Inc
   3  * Written by Simon Glass <sjg@chromium.org>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <fdtdec.h>
  12 #include <inttypes.h>
  13 #include <pci.h>
  14 #include <asm/io.h>
  15 #include <dm/lists.h>
  16 #include <dm/device-internal.h>
  17 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  18 #include <asm/fsp/fsp_support.h>
  19 #endif
  20 #include "pci_internal.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 int pci_get_bus(int busnum, struct udevice **busp)
  25 {
  26         int ret;
  27
  28         ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  29
  30         /* Since buses may not be numbered yet try a little harder with bus 0 */
  31         if (ret == -ENODEV) {
  32                 ret = uclass_first_device_err(UCLASS_PCI, busp);
  33                 if (ret)
  34                         return ret;
  35                 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  36         }
  37
  38         return ret;
  39 }
  40
  41 struct udevice *pci_get_controller(struct udevice *dev)
  42 {
  43         while (device_is_on_pci_bus(dev))
  44                 dev = dev->parent;
  45
  46         return dev;
  47 }
  48
  49 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
  50 {
  51         struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  52         struct udevice *bus = dev->parent;
  53
  54         return PCI_ADD_BUS(bus->seq, pplat->devfn);
  55 }
  56
  57 /**
  58  * pci_get_bus_max() - returns the bus number of the last active bus
  59  *
  60  * @return last bus number, or -1 if no active buses
  61  */
  62 static int pci_get_bus_max(void)
  63 {
  64         struct udevice *bus;
  65         struct uclass *uc;
  66         int ret = -1;
  67
  68         ret = uclass_get(UCLASS_PCI, &uc);
  69         uclass_foreach_dev(bus, uc) {
  70                 if (bus->seq > ret)
  71                         ret = bus->seq;
  72         }
  73
  74         debug("%s: ret=%d\n", __func__, ret);
  75
  76         return ret;
  77 }
  78
  79 int pci_last_busno(void)
  80 {
  81         return pci_get_bus_max();
  82 }
  83
  84 int pci_get_ff(enum pci_size_t size)
  85 {
  86         switch (size) {
  87         case PCI_SIZE_8:
  88                 return 0xff;
  89         case PCI_SIZE_16:
  90                 return 0xffff;
  91         default:
  92                 return 0xffffffff;
  93         }
  94 }
  95
  96 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
  97                        struct udevice **devp)
  98 {
  99         struct udevice *dev;
 100
 101         for (device_find_first_child(bus, &dev);
 102              dev;
 103              device_find_next_child(&dev)) {
 104                 struct pci_child_platdata *pplat;
 105
 106                 pplat = dev_get_parent_platdata(dev);
 107                 if (pplat && pplat->devfn == find_devfn) {
 108                         *devp = dev;
 109                         return 0;
 110                 }
 111         }
 112
 113         return -ENODEV;
 114 }
 115
 116 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
 117 {
 118         struct udevice *bus;
 119         int ret;
 120
 121         ret = pci_get_bus(PCI_BUS(bdf), &bus);
 122         if (ret)
 123                 return ret;
 124         return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
 125 }
 126
 127 static int pci_device_matches_ids(struct udevice *dev,
 128                                   struct pci_device_id *ids)
 129 {
 130         struct pci_child_platdata *pplat;
 131         int i;
 132
 133         pplat = dev_get_parent_platdata(dev);
 134         if (!pplat)
 135                 return -EINVAL;
 136         for (i = 0; ids[i].vendor != 0; i++) {
 137                 if (pplat->vendor == ids[i].vendor &&
 138                     pplat->device == ids[i].device)
 139                         return i;
 140         }
 141
 142         return -EINVAL;
 143 }
 144
 145 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
 146                          int *indexp, struct udevice **devp)
 147 {
 148         struct udevice *dev;
 149
 150         /* Scan all devices on this bus */
 151         for (device_find_first_child(bus, &dev);
 152              dev;
 153              device_find_next_child(&dev)) {
 154                 if (pci_device_matches_ids(dev, ids) >= 0) {
 155                         if ((*indexp)-- <= 0) {
 156                                 *devp = dev;
 157                                 return 0;
 158                         }
 159                 }
 160         }
 161
 162         return -ENODEV;
 163 }
 164
 165 int pci_find_device_id(struct pci_device_id *ids, int index,
 166                        struct udevice **devp)
 167 {
 168         struct udevice *bus;
 169
 170         /* Scan all known buses */
 171         for (uclass_first_device(UCLASS_PCI, &bus);
 172              bus;
 173              uclass_next_device(&bus)) {
 174                 if (!pci_bus_find_devices(bus, ids, &index, devp))
 175                         return 0;
 176         }
 177         *devp = NULL;
 178
 179         return -ENODEV;
 180 }
 181
 182 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
 183                                   unsigned int device, int *indexp,
 184                                   struct udevice **devp)
 185 {
 186         struct pci_child_platdata *pplat;
 187         struct udevice *dev;
 188
 189         for (device_find_first_child(bus, &dev);
 190              dev;
 191              device_find_next_child(&dev)) {
 192                 pplat = dev_get_parent_platdata(dev);
 193                 if (pplat->vendor == vendor && pplat->device == device) {
 194                         if (!(*indexp)--) {
 195                                 *devp = dev;
 196                                 return 0;
 197                         }
 198                 }
 199         }
 200
 201         return -ENODEV;
 202 }
 203
 204 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
 205                        struct udevice **devp)
 206 {
 207         struct udevice *bus;
 208
 209         /* Scan all known buses */
 210         for (uclass_first_device(UCLASS_PCI, &bus);
 211              bus;
 212              uclass_next_device(&bus)) {
 213                 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
 214                         return device_probe(*devp);
 215         }
 216         *devp = NULL;
 217
 218         return -ENODEV;
 219 }
 220
 221 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
 222 {
 223         struct udevice *dev;
 224
 225         /* Scan all known buses */
 226         for (pci_find_first_device(&dev);
 227              dev;
 228              pci_find_next_device(&dev)) {
 229                 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
 230
 231                 if (pplat->class == find_class && !index--) {
 232                         *devp = dev;
 233                         return device_probe(*devp);
 234                 }
 235         }
 236         *devp = NULL;
 237
 238         return -ENODEV;
 239 }
 240
 241 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
 242                          unsigned long value, enum pci_size_t size)
 243 {
 244         struct dm_pci_ops *ops;
 245
 246         ops = pci_get_ops(bus);
 247         if (!ops->write_config)
 248                 return -ENOSYS;
 249         return ops->write_config(bus, bdf, offset, value, size);
 250 }
 251
 252 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
 253                             u32 clr, u32 set)
 254 {
 255         ulong val;
 256         int ret;
 257
 258         ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
 259         if (ret)
 260                 return ret;
 261         val &= ~clr;
 262         val |= set;
 263
 264         return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
 265 }
 266
 267 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
 268                      enum pci_size_t size)
 269 {
 270         struct udevice *bus;
 271         int ret;
 272
 273         ret = pci_get_bus(PCI_BUS(bdf), &bus);
 274         if (ret)
 275                 return ret;
 276
 277         return pci_bus_write_config(bus, bdf, offset, value, size);
 278 }
 279
 280 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
 281                         enum pci_size_t size)
 282 {
 283         struct udevice *bus;
 284
 285         for (bus = dev; device_is_on_pci_bus(bus);)
 286                 bus = bus->parent;
 287         return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
 288                                     size);
 289 }
 290
 291 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
 292 {
 293         return pci_write_config(bdf, offset, value, PCI_SIZE_32);
 294 }
 295
 296 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
 297 {
 298         return pci_write_config(bdf, offset, value, PCI_SIZE_16);
 299 }
 300
 301 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
 302 {
 303         return pci_write_config(bdf, offset, value, PCI_SIZE_8);
 304 }
 305
 306 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
 307 {
 308         return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
 309 }
 310
 311 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
 312 {
 313         return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
 314 }
 315
 316 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
 317 {
 318         return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
 319 }
 320
 321 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
 322                         unsigned long *valuep, enum pci_size_t size)
 323 {
 324         struct dm_pci_ops *ops;
 325
 326         ops = pci_get_ops(bus);
 327         if (!ops->read_config)
 328                 return -ENOSYS;
 329         return ops->read_config(bus, bdf, offset, valuep, size);
 330 }
 331
 332 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
 333                     enum pci_size_t size)
 334 {
 335         struct udevice *bus;
 336         int ret;
 337
 338         ret = pci_get_bus(PCI_BUS(bdf), &bus);
 339         if (ret)
 340                 return ret;
 341
 342         return pci_bus_read_config(bus, bdf, offset, valuep, size);
 343 }
 344
 345 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
 346                        enum pci_size_t size)
 347 {
 348         struct udevice *bus;
 349
 350         for (bus = dev; device_is_on_pci_bus(bus);)
 351                 bus = bus->parent;
 352         return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
 353                                    size);
 354 }
 355
 356 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
 357 {
 358         unsigned long value;
 359         int ret;
 360
 361         ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
 362         if (ret)
 363                 return ret;
 364         *valuep = value;
 365
 366         return 0;
 367 }
 368
 369 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
 370 {
 371         unsigned long value;
 372         int ret;
 373
 374         ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
 375         if (ret)
 376                 return ret;
 377         *valuep = value;
 378
 379         return 0;
 380 }
 381
 382 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
 383 {
 384         unsigned long value;
 385         int ret;
 386
 387         ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
 388         if (ret)
 389                 return ret;
 390         *valuep = value;
 391
 392         return 0;
 393 }
 394
 395 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
 396 {
 397         unsigned long value;
 398         int ret;
 399
 400         ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
 401         if (ret)
 402                 return ret;
 403         *valuep = value;
 404
 405         return 0;
 406 }
 407
 408 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
 409 {
 410         unsigned long value;
 411         int ret;
 412
 413         ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
 414         if (ret)
 415                 return ret;
 416         *valuep = value;
 417
 418         return 0;
 419 }
 420
 421 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
 422 {
 423         unsigned long value;
 424         int ret;
 425
 426         ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
 427         if (ret)
 428                 return ret;
 429         *valuep = value;
 430
 431         return 0;
 432 }
 433
 434 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
 435 {
 436         u8 val;
 437         int ret;
 438
 439         ret = dm_pci_read_config8(dev, offset, &val);
 440         if (ret)
 441                 return ret;
 442         val &= ~clr;
 443         val |= set;
 444
 445         return dm_pci_write_config8(dev, offset, val);
 446 }
 447
 448 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
 449 {
 450         u16 val;
 451         int ret;
 452
 453         ret = dm_pci_read_config16(dev, offset, &val);
 454         if (ret)
 455                 return ret;
 456         val &= ~clr;
 457         val |= set;
 458
 459         return dm_pci_write_config16(dev, offset, val);
 460 }
 461
 462 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
 463 {
 464         u32 val;
 465         int ret;
 466
 467         ret = dm_pci_read_config32(dev, offset, &val);
 468         if (ret)
 469                 return ret;
 470         val &= ~clr;
 471         val |= set;
 472
 473         return dm_pci_write_config32(dev, offset, val);
 474 }
 475
 476 static void set_vga_bridge_bits(struct udevice *dev)
 477 {
 478         struct udevice *parent = dev->parent;
 479         u16 bc;
 480
 481         while (parent->seq != 0) {
 482                 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
 483                 bc |= PCI_BRIDGE_CTL_VGA;
 484                 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
 485                 parent = parent->parent;
 486         }
 487 }
 488
 489 int pci_auto_config_devices(struct udevice *bus)
 490 {
 491         struct pci_controller *hose = bus->uclass_priv;
 492         struct pci_child_platdata *pplat;
 493         unsigned int sub_bus;
 494         struct udevice *dev;
 495         int ret;
 496
 497         sub_bus = bus->seq;
 498         debug("%s: start\n", __func__);
 499         pciauto_config_init(hose);
 500         for (ret = device_find_first_child(bus, &dev);
 501              !ret && dev;
 502              ret = device_find_next_child(&dev)) {
 503                 unsigned int max_bus;
 504                 int ret;
 505
 506                 debug("%s: device %s\n", __func__, dev->name);
 507                 ret = dm_pciauto_config_device(dev);
 508                 if (ret < 0)
 509                         return ret;
 510                 max_bus = ret;
 511                 sub_bus = max(sub_bus, max_bus);
 512
 513                 pplat = dev_get_parent_platdata(dev);
 514                 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
 515                         set_vga_bridge_bits(dev);
 516         }
 517         debug("%s: done\n", __func__);
 518
 519         return sub_bus;
 520 }
 521
 522 int dm_pci_hose_probe_bus(struct udevice *bus)
 523 {
 524         int sub_bus;
 525         int ret;
 526
 527         debug("%s\n", __func__);
 528
 529         sub_bus = pci_get_bus_max() + 1;
 530         debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
 531         dm_pciauto_prescan_setup_bridge(bus, sub_bus);
 532
 533         ret = device_probe(bus);
 534         if (ret) {
 535                 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
 536                       ret);
 537                 return ret;
 538         }
 539         if (sub_bus != bus->seq) {
 540                 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
 541                        __func__, bus->name, bus->seq, sub_bus);
 542                 return -EPIPE;
 543         }
 544         sub_bus = pci_get_bus_max();
 545         dm_pciauto_postscan_setup_bridge(bus, sub_bus);
 546
 547         return sub_bus;
 548 }
 549
 550 /**
 551  * pci_match_one_device - Tell if a PCI device structure has a matching
 552  *                        PCI device id structure
 553  * @id: single PCI device id structure to match
 554  * @find: the PCI device id structure to match against
 555  *
 556  * Returns true if the finding pci_device_id structure matched or false if
 557  * there is no match.
 558  */
 559 static bool pci_match_one_id(const struct pci_device_id *id,
 560                              const struct pci_device_id *find)
 561 {
 562         if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
 563             (id->device == PCI_ANY_ID || id->device == find->device) &&
 564             (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
 565             (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
 566             !((id->class ^ find->class) & id->class_mask))
 567                 return true;
 568
 569         return false;
 570 }
 571
 572 /**
 573  * pci_find_and_bind_driver() - Find and bind the right PCI driver
 574  *
 575  * This only looks at certain fields in the descriptor.
 576  *
 577  * @parent:     Parent bus
 578  * @find_id:    Specification of the driver to find
 579  * @bdf:        Bus/device/function addreess - see PCI_BDF()
 580  * @devp:       Returns a pointer to the device created
 581  * @return 0 if OK, -EPERM if the device is not needed before relocation and
 582  *         therefore was not created, other -ve value on error
 583  */
 584 static int pci_find_and_bind_driver(struct udevice *parent,
 585                                     struct pci_device_id *find_id,
 586                                     pci_dev_t bdf, struct udevice **devp)
 587 {
 588         struct pci_driver_entry *start, *entry;
 589         const char *drv;
 590         int n_ents;
 591         int ret;
 592         char name[30], *str;
 593         bool bridge;
 594
 595         *devp = NULL;
 596
 597         debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
 598               find_id->vendor, find_id->device);
 599         start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
 600         n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
 601         for (entry = start; entry != start + n_ents; entry++) {
 602                 const struct pci_device_id *id;
 603                 struct udevice *dev;
 604                 const struct driver *drv;
 605
 606                 for (id = entry->match;
 607                      id->vendor || id->subvendor || id->class_mask;
 608                      id++) {
 609                         if (!pci_match_one_id(id, find_id))
 610                                 continue;
 611
 612                         drv = entry->driver;
 613
 614                         /*
 615                          * In the pre-relocation phase, we only bind devices
 616                          * whose driver has the DM_FLAG_PRE_RELOC set, to save
 617                          * precious memory space as on some platforms as that
 618                          * space is pretty limited (ie: using Cache As RAM).
 619                          */
 620                         if (!(gd->flags & GD_FLG_RELOC) &&
 621                             !(drv->flags & DM_FLAG_PRE_RELOC))
 622                                 return -EPERM;
 623
 624                         /*
 625                          * We could pass the descriptor to the driver as
 626                          * platdata (instead of NULL) and allow its bind()
 627                          * method to return -ENOENT if it doesn't support this
 628                          * device. That way we could continue the search to
 629                          * find another driver. For now this doesn't seem
 630                          * necesssary, so just bind the first match.
 631                          */
 632                         ret = device_bind(parent, drv, drv->name, NULL, -1,
 633                                           &dev);
 634                         if (ret)
 635                                 goto error;
 636                         debug("%s: Match found: %s\n", __func__, drv->name);
 637                         dev->driver_data = find_id->driver_data;
 638                         *devp = dev;
 639                         return 0;
 640                 }
 641         }
 642
 643         bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
 644         /*
 645          * In the pre-relocation phase, we only bind bridge devices to save
 646          * precious memory space as on some platforms as that space is pretty
 647          * limited (ie: using Cache As RAM).
 648          */
 649         if (!(gd->flags & GD_FLG_RELOC) && !bridge)
 650                 return -EPERM;
 651
 652         /* Bind a generic driver so that the device can be used */
 653         sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
 654                 PCI_FUNC(bdf));
 655         str = strdup(name);
 656         if (!str)
 657                 return -ENOMEM;
 658         drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
 659
 660         ret = device_bind_driver(parent, drv, str, devp);
 661         if (ret) {
 662                 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
 663                 free(str);
 664                 return ret;
 665         }
 666         debug("%s: No match found: bound generic driver instead\n", __func__);
 667
 668         return 0;
 669
 670 error:
 671         debug("%s: No match found: error %d\n", __func__, ret);
 672         return ret;
 673 }
 674
 675 int pci_bind_bus_devices(struct udevice *bus)
 676 {
 677         ulong vendor, device;
 678         ulong header_type;
 679         pci_dev_t bdf, end;
 680         bool found_multi;
 681         int ret;
 682
 683         found_multi = false;
 684         end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
 685                       PCI_MAX_PCI_FUNCTIONS - 1);
 686         for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
 687              bdf += PCI_BDF(0, 0, 1)) {
 688                 struct pci_child_platdata *pplat;
 689                 struct udevice *dev;
 690                 ulong class;
 691
 692                 if (PCI_FUNC(bdf) && !found_multi)
 693                         continue;
 694                 /* Check only the first access, we don't expect problems */
 695                 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
 696                                           &header_type, PCI_SIZE_8);
 697                 if (ret)
 698                         goto error;
 699                 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
 700                                     PCI_SIZE_16);
 701                 if (vendor == 0xffff || vendor == 0x0000)
 702                         continue;
 703
 704                 if (!PCI_FUNC(bdf))
 705                         found_multi = header_type & 0x80;
 706
 707                 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
 708                       bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
 709                 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
 710                                     PCI_SIZE_16);
 711                 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
 712                                     PCI_SIZE_32);
 713                 class >>= 8;
 714
 715                 /* Find this device in the device tree */
 716                 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
 717
 718                 /* If nothing in the device tree, bind a device */
 719                 if (ret == -ENODEV) {
 720                         struct pci_device_id find_id;
 721                         ulong val;
 722
 723                         memset(&find_id, '\0', sizeof(find_id));
 724                         find_id.vendor = vendor;
 725                         find_id.device = device;
 726                         find_id.class = class;
 727                         if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
 728                                 pci_bus_read_config(bus, bdf,
 729                                                     PCI_SUBSYSTEM_VENDOR_ID,
 730                                                     &val, PCI_SIZE_32);
 731                                 find_id.subvendor = val & 0xffff;
 732                                 find_id.subdevice = val >> 16;
 733                         }
 734                         ret = pci_find_and_bind_driver(bus, &find_id, bdf,
 735                                                        &dev);
 736                 }
 737                 if (ret == -EPERM)
 738                         continue;
 739                 else if (ret)
 740                         return ret;
 741
 742                 /* Update the platform data */
 743                 pplat = dev_get_parent_platdata(dev);
 744                 pplat->devfn = PCI_MASK_BUS(bdf);
 745                 pplat->vendor = vendor;
 746                 pplat->device = device;
 747                 pplat->class = class;
 748         }
 749
 750         return 0;
 751 error:
 752         printf("Cannot read bus configuration: %d\n", ret);
 753
 754         return ret;
 755 }
 756
 757 static int decode_regions(struct pci_controller *hose, const void *blob,
 758                           int parent_node, int node)
 759 {
 760         int pci_addr_cells, addr_cells, size_cells;
 761         phys_addr_t base = 0, size;
 762         int cells_per_record;
 763         const u32 *prop;
 764         int len;
 765         int i;
 766
 767         prop = fdt_getprop(blob, node, "ranges", &len);
 768         if (!prop)
 769                 return -EINVAL;
 770         pci_addr_cells = fdt_address_cells(blob, node);
 771         addr_cells = fdt_address_cells(blob, parent_node);
 772         size_cells = fdt_size_cells(blob, node);
 773
 774         /* PCI addresses are always 3-cells */
 775         len /= sizeof(u32);
 776         cells_per_record = pci_addr_cells + addr_cells + size_cells;
 777         hose->region_count = 0;
 778         debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
 779               cells_per_record);
 780         for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
 781                 u64 pci_addr, addr, size;
 782                 int space_code;
 783                 u32 flags;
 784                 int type;
 785                 int pos;
 786
 787                 if (len < cells_per_record)
 788                         break;
 789                 flags = fdt32_to_cpu(prop[0]);
 790                 space_code = (flags >> 24) & 3;
 791                 pci_addr = fdtdec_get_number(prop + 1, 2);
 792                 prop += pci_addr_cells;
 793                 addr = fdtdec_get_number(prop, addr_cells);
 794                 prop += addr_cells;
 795                 size = fdtdec_get_number(prop, size_cells);
 796                 prop += size_cells;
 797                 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
 798                       ", size=%" PRIx64 ", space_code=%d\n", __func__,
 799                       hose->region_count, pci_addr, addr, size, space_code);
 800                 if (space_code & 2) {
 801                         type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
 802                                         PCI_REGION_MEM;
 803                 } else if (space_code & 1) {
 804                         type = PCI_REGION_IO;
 805                 } else {
 806                         continue;
 807                 }
 808                 pos = -1;
 809                 for (i = 0; i < hose->region_count; i++) {
 810                         if (hose->regions[i].flags == type)
 811                                 pos = i;
 812                 }
 813                 if (pos == -1)
 814                         pos = hose->region_count++;
 815                 debug(" - type=%d, pos=%d\n", type, pos);
 816                 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
 817         }
 818
 819         /* Add a region for our local memory */
 820         size = gd->ram_size;
 821 #ifdef CONFIG_SYS_SDRAM_BASE
 822         base = CONFIG_SYS_SDRAM_BASE;
 823 #endif
 824         if (gd->pci_ram_top && gd->pci_ram_top < base + size)
 825                 size = gd->pci_ram_top - base;
 826         pci_set_region(hose->regions + hose->region_count++, base, base,
 827                        size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 828
 829         return 0;
 830 }
 831
 832 static int pci_uclass_pre_probe(struct udevice *bus)
 833 {
 834         struct pci_controller *hose;
 835         int ret;
 836
 837         debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
 838               bus->parent->name);
 839         hose = bus->uclass_priv;
 840
 841         /* For bridges, use the top-level PCI controller */
 842         if (!device_is_on_pci_bus(bus)) {
 843                 hose->ctlr = bus;
 844                 ret = decode_regions(hose, gd->fdt_blob,
 845                                      dev_of_offset(bus->parent),
 846                                      dev_of_offset(bus));
 847                 if (ret) {
 848                         debug("%s: Cannot decode regions\n", __func__);
 849                         return ret;
 850                 }
 851         } else {
 852                 struct pci_controller *parent_hose;
 853
 854                 parent_hose = dev_get_uclass_priv(bus->parent);
 855                 hose->ctlr = parent_hose->bus;
 856         }
 857         hose->bus = bus;
 858         hose->first_busno = bus->seq;
 859         hose->last_busno = bus->seq;
 860
 861         return 0;
 862 }
 863
 864 static int pci_uclass_post_probe(struct udevice *bus)
 865 {
 866         int ret;
 867
 868         debug("%s: probing bus %d\n", __func__, bus->seq);
 869         ret = pci_bind_bus_devices(bus);
 870         if (ret)
 871                 return ret;
 872
 873 #ifdef CONFIG_PCI_PNP
 874         ret = pci_auto_config_devices(bus);
 875         if (ret < 0)
 876                 return ret;
 877 #endif
 878
 879 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
 880         /*
 881          * Per Intel FSP specification, we should call FSP notify API to
 882          * inform FSP that PCI enumeration has been done so that FSP will
 883          * do any necessary initialization as required by the chipset's
 884          * BIOS Writer's Guide (BWG).
 885          *
 886          * Unfortunately we have to put this call here as with driver model,
 887          * the enumeration is all done on a lazy basis as needed, so until
 888          * something is touched on PCI it won't happen.
 889          *
 890          * Note we only call this 1) after U-Boot is relocated, and 2)
 891          * root bus has finished probing.
 892          */
 893         if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
 894                 ret = fsp_init_phase_pci();
 895                 if (ret)
 896                         return ret;
 897         }
 898 #endif
 899
 900         return 0;
 901 }
 902
 903 static int pci_uclass_child_post_bind(struct udevice *dev)
 904 {
 905         struct pci_child_platdata *pplat;
 906         struct fdt_pci_addr addr;
 907         int ret;
 908
 909         if (dev_of_offset(dev) == -1)
 910                 return 0;
 911
 912         /*
 913          * We could read vendor, device, class if available. But for now we
 914          * just check the address.
 915          */
 916         pplat = dev_get_parent_platdata(dev);
 917         ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev),
 918                                   FDT_PCI_SPACE_CONFIG, "reg", &addr);
 919
 920         if (ret) {
 921                 if (ret != -ENOENT)
 922                         return -EINVAL;
 923         } else {
 924                 /* extract the devfn from fdt_pci_addr */
 925                 pplat->devfn = addr.phys_hi & 0xff00;
 926         }
 927
 928         return 0;
 929 }
 930
 931 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
 932                                   uint offset, ulong *valuep,
 933                                   enum pci_size_t size)
 934 {
 935         struct pci_controller *hose = bus->uclass_priv;
 936
 937         return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
 938 }
 939
 940 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
 941                                    uint offset, ulong value,
 942                                    enum pci_size_t size)
 943 {
 944         struct pci_controller *hose = bus->uclass_priv;
 945
 946         return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
 947 }
 948
 949 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
 950 {
 951         struct udevice *dev;
 952         int ret = 0;
 953
 954         /*
 955          * Scan through all the PCI controllers. On x86 there will only be one
 956          * but that is not necessarily true on other hardware.
 957          */
 958         do {
 959                 device_find_first_child(bus, &dev);
 960                 if (dev) {
 961                         *devp = dev;
 962                         return 0;
 963                 }
 964                 ret = uclass_next_device(&bus);
 965                 if (ret)
 966                         return ret;
 967         } while (bus);
 968
 969         return 0;
 970 }
 971
 972 int pci_find_next_device(struct udevice **devp)
 973 {
 974         struct udevice *child = *devp;
 975         struct udevice *bus = child->parent;
 976         int ret;
 977
 978         /* First try all the siblings */
 979         *devp = NULL;
 980         while (child) {
 981                 device_find_next_child(&child);
 982                 if (child) {
 983                         *devp = child;
 984                         return 0;
 985                 }
 986         }
 987
 988         /* We ran out of siblings. Try the next bus */
 989         ret = uclass_next_device(&bus);
 990         if (ret)
 991                 return ret;
 992
 993         return bus ? skip_to_next_device(bus, devp) : 0;
 994 }
 995
 996 int pci_find_first_device(struct udevice **devp)
 997 {
 998         struct udevice *bus;
 999         int ret;
1000
1001         *devp = NULL;
1002         ret = uclass_first_device(UCLASS_PCI, &bus);
1003         if (ret)
1004                 return ret;
1005
1006         return skip_to_next_device(bus, devp);
1007 }
1008
1009 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1010 {
1011         switch (size) {
1012         case PCI_SIZE_8:
1013                 return (value >> ((offset & 3) * 8)) & 0xff;
1014         case PCI_SIZE_16:
1015                 return (value >> ((offset & 2) * 8)) & 0xffff;
1016         default:
1017                 return value;
1018         }
1019 }
1020
1021 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1022                           enum pci_size_t size)
1023 {
1024         uint off_mask;
1025         uint val_mask, shift;
1026         ulong ldata, mask;
1027
1028         switch (size) {
1029         case PCI_SIZE_8:
1030                 off_mask = 3;
1031                 val_mask = 0xff;
1032                 break;
1033         case PCI_SIZE_16:
1034                 off_mask = 2;
1035                 val_mask = 0xffff;
1036                 break;
1037         default:
1038                 return value;
1039         }
1040         shift = (offset & off_mask) * 8;
1041         ldata = (value & val_mask) << shift;
1042         mask = val_mask << shift;
1043         value = (old & ~mask) | ldata;
1044
1045         return value;
1046 }
1047
1048 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1049                     struct pci_region **memp, struct pci_region **prefp)
1050 {
1051         struct udevice *bus = pci_get_controller(dev);
1052         struct pci_controller *hose = dev_get_uclass_priv(bus);
1053         int i;
1054
1055         *iop = NULL;
1056         *memp = NULL;
1057         *prefp = NULL;
1058         for (i = 0; i < hose->region_count; i++) {
1059                 switch (hose->regions[i].flags) {
1060                 case PCI_REGION_IO:
1061                         if (!*iop || (*iop)->size < hose->regions[i].size)
1062                                 *iop = hose->regions + i;
1063                         break;
1064                 case PCI_REGION_MEM:
1065                         if (!*memp || (*memp)->size < hose->regions[i].size)
1066                                 *memp = hose->regions + i;
1067                         break;
1068                 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1069                         if (!*prefp || (*prefp)->size < hose->regions[i].size)
1070                                 *prefp = hose->regions + i;
1071                         break;
1072                 }
1073         }
1074
1075         return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1076 }
1077
1078 u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1079 {
1080         u32 addr;
1081         int bar;
1082
1083         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1084         dm_pci_read_config32(dev, bar, &addr);
1085         if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1086                 return addr & PCI_BASE_ADDRESS_IO_MASK;
1087         else
1088                 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1089 }
1090
1091 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1092 {
1093         int bar;
1094
1095         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1096         dm_pci_write_config32(dev, bar, addr);
1097 }
1098
1099 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1100                                pci_addr_t bus_addr, unsigned long flags,
1101                                unsigned long skip_mask, phys_addr_t *pa)
1102 {
1103         struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1104         struct pci_region *res;
1105         int i;
1106
1107         for (i = 0; i < hose->region_count; i++) {
1108                 res = &hose->regions[i];
1109
1110                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1111                         continue;
1112
1113                 if (res->flags & skip_mask)
1114                         continue;
1115
1116                 if (bus_addr >= res->bus_start &&
1117                     (bus_addr - res->bus_start) < res->size) {
1118                         *pa = (bus_addr - res->bus_start + res->phys_start);
1119                         return 0;
1120                 }
1121         }
1122
1123         return 1;
1124 }
1125
1126 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1127                                unsigned long flags)
1128 {
1129         phys_addr_t phys_addr = 0;
1130         struct udevice *ctlr;
1131         int ret;
1132
1133         /* The root controller has the region information */
1134         ctlr = pci_get_controller(dev);
1135
1136         /*
1137          * if PCI_REGION_MEM is set we do a two pass search with preference
1138          * on matches that don't have PCI_REGION_SYS_MEMORY set
1139          */
1140         if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1141                 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1142                                           flags, PCI_REGION_SYS_MEMORY,
1143                                           &phys_addr);
1144                 if (!ret)
1145                         return phys_addr;
1146         }
1147
1148         ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1149
1150         if (ret)
1151                 puts("pci_hose_bus_to_phys: invalid physical address\n");
1152
1153         return phys_addr;
1154 }
1155
1156 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1157                         unsigned long flags, unsigned long skip_mask,
1158                         pci_addr_t *ba)
1159 {
1160         struct pci_region *res;
1161         struct udevice *ctlr;
1162         pci_addr_t bus_addr;
1163         int i;
1164         struct pci_controller *hose;
1165
1166         /* The root controller has the region information */
1167         ctlr = pci_get_controller(dev);
1168         hose = dev_get_uclass_priv(ctlr);
1169
1170         for (i = 0; i < hose->region_count; i++) {
1171                 res = &hose->regions[i];
1172
1173                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1174                         continue;
1175
1176                 if (res->flags & skip_mask)
1177                         continue;
1178
1179                 bus_addr = phys_addr - res->phys_start + res->bus_start;
1180
1181                 if (bus_addr >= res->bus_start &&
1182                     (bus_addr - res->bus_start) < res->size) {
1183                         *ba = bus_addr;
1184                         return 0;
1185                 }
1186         }
1187
1188         return 1;
1189 }
1190
1191 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1192                               unsigned long flags)
1193 {
1194         pci_addr_t bus_addr = 0;
1195         int ret;
1196
1197         /*
1198          * if PCI_REGION_MEM is set we do a two pass search with preference
1199          * on matches that don't have PCI_REGION_SYS_MEMORY set
1200          */
1201         if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1202                 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1203                                           PCI_REGION_SYS_MEMORY, &bus_addr);
1204                 if (!ret)
1205                         return bus_addr;
1206         }
1207
1208         ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1209
1210         if (ret)
1211                 puts("pci_hose_phys_to_bus: invalid physical address\n");
1212
1213         return bus_addr;
1214 }
1215
1216 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1217 {
1218         pci_addr_t pci_bus_addr;
1219         u32 bar_response;
1220
1221         /* read BAR address */
1222         dm_pci_read_config32(dev, bar, &bar_response);
1223         pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1224
1225         /*
1226          * Pass "0" as the length argument to pci_bus_to_virt.  The arg
1227          * isn't actualy used on any platform because u-boot assumes a static
1228          * linear mapping.  In the future, this could read the BAR size
1229          * and pass that as the size if needed.
1230          */
1231         return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1232 }
1233
1234 UCLASS_DRIVER(pci) = {
1235         .id             = UCLASS_PCI,
1236         .name           = "pci",
1237         .flags          = DM_UC_FLAG_SEQ_ALIAS,
1238         .post_bind      = dm_scan_fdt_dev,
1239         .pre_probe      = pci_uclass_pre_probe,
1240         .post_probe     = pci_uclass_post_probe,
1241         .child_post_bind = pci_uclass_child_post_bind,
1242         .per_device_auto_alloc_size = sizeof(struct pci_controller),
1243         .per_child_platdata_auto_alloc_size =
1244                         sizeof(struct pci_child_platdata),
1245 };
1246
1247 static const struct dm_pci_ops pci_bridge_ops = {
1248         .read_config    = pci_bridge_read_config,
1249         .write_config   = pci_bridge_write_config,
1250 };
1251
1252 static const struct udevice_id pci_bridge_ids[] = {
1253         { .compatible = "pci-bridge" },
1254         { }
1255 };
1256
1257 U_BOOT_DRIVER(pci_bridge_drv) = {
1258         .name           = "pci_bridge_drv",
1259         .id             = UCLASS_PCI,
1260         .of_match       = pci_bridge_ids,
1261         .ops            = &pci_bridge_ops,
1262 };
1263
1264 UCLASS_DRIVER(pci_generic) = {
1265         .id             = UCLASS_PCI_GENERIC,
1266         .name           = "pci_generic",
1267 };
1268
1269 static const struct udevice_id pci_generic_ids[] = {
1270         { .compatible = "pci-generic" },
1271         { }
1272 };
1273
1274 U_BOOT_DRIVER(pci_generic_drv) = {
1275         .name           = "pci_generic_drv",
1276         .id             = UCLASS_PCI_GENERIC,
1277         .of_match       = pci_generic_ids,
1278 };
1279
1280 void pci_init(void)
1281 {
1282         struct udevice *bus;
1283
1284         /*
1285          * Enumerate all known controller devices. Enumeration has the side-
1286          * effect of probing them, so PCIe devices will be enumerated too.
1287          */
1288         for (uclass_first_device(UCLASS_PCI, &bus);
1289              bus;
1290              uclass_next_device(&bus)) {
1291                 ;
1292         }
1293 }