2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
17 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
18 #include <asm/fsp/fsp_support.h>
20 #include "pci_internal.h"
22 DECLARE_GLOBAL_DATA_PTR
;
24 int pci_get_bus(int busnum
, struct udevice
**busp
)
28 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, busp
);
30 /* Since buses may not be numbered yet try a little harder with bus 0 */
32 ret
= uclass_first_device_err(UCLASS_PCI
, busp
);
35 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, busp
);
41 struct udevice
*pci_get_controller(struct udevice
*dev
)
43 while (device_is_on_pci_bus(dev
))
49 pci_dev_t
dm_pci_get_bdf(struct udevice
*dev
)
51 struct pci_child_platdata
*pplat
= dev_get_parent_platdata(dev
);
52 struct udevice
*bus
= dev
->parent
;
54 return PCI_ADD_BUS(bus
->seq
, pplat
->devfn
);
58 * pci_get_bus_max() - returns the bus number of the last active bus
60 * @return last bus number, or -1 if no active buses
62 static int pci_get_bus_max(void)
68 ret
= uclass_get(UCLASS_PCI
, &uc
);
69 uclass_foreach_dev(bus
, uc
) {
74 debug("%s: ret=%d\n", __func__
, ret
);
79 int pci_last_busno(void)
81 return pci_get_bus_max();
84 int pci_get_ff(enum pci_size_t size
)
96 int pci_bus_find_devfn(struct udevice
*bus
, pci_dev_t find_devfn
,
97 struct udevice
**devp
)
101 for (device_find_first_child(bus
, &dev
);
103 device_find_next_child(&dev
)) {
104 struct pci_child_platdata
*pplat
;
106 pplat
= dev_get_parent_platdata(dev
);
107 if (pplat
&& pplat
->devfn
== find_devfn
) {
116 int dm_pci_bus_find_bdf(pci_dev_t bdf
, struct udevice
**devp
)
121 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
124 return pci_bus_find_devfn(bus
, PCI_MASK_BUS(bdf
), devp
);
127 static int pci_device_matches_ids(struct udevice
*dev
,
128 struct pci_device_id
*ids
)
130 struct pci_child_platdata
*pplat
;
133 pplat
= dev_get_parent_platdata(dev
);
136 for (i
= 0; ids
[i
].vendor
!= 0; i
++) {
137 if (pplat
->vendor
== ids
[i
].vendor
&&
138 pplat
->device
== ids
[i
].device
)
145 int pci_bus_find_devices(struct udevice
*bus
, struct pci_device_id
*ids
,
146 int *indexp
, struct udevice
**devp
)
150 /* Scan all devices on this bus */
151 for (device_find_first_child(bus
, &dev
);
153 device_find_next_child(&dev
)) {
154 if (pci_device_matches_ids(dev
, ids
) >= 0) {
155 if ((*indexp
)-- <= 0) {
165 int pci_find_device_id(struct pci_device_id
*ids
, int index
,
166 struct udevice
**devp
)
170 /* Scan all known buses */
171 for (uclass_first_device(UCLASS_PCI
, &bus
);
173 uclass_next_device(&bus
)) {
174 if (!pci_bus_find_devices(bus
, ids
, &index
, devp
))
182 static int dm_pci_bus_find_device(struct udevice
*bus
, unsigned int vendor
,
183 unsigned int device
, int *indexp
,
184 struct udevice
**devp
)
186 struct pci_child_platdata
*pplat
;
189 for (device_find_first_child(bus
, &dev
);
191 device_find_next_child(&dev
)) {
192 pplat
= dev_get_parent_platdata(dev
);
193 if (pplat
->vendor
== vendor
&& pplat
->device
== device
) {
204 int dm_pci_find_device(unsigned int vendor
, unsigned int device
, int index
,
205 struct udevice
**devp
)
209 /* Scan all known buses */
210 for (uclass_first_device(UCLASS_PCI
, &bus
);
212 uclass_next_device(&bus
)) {
213 if (!dm_pci_bus_find_device(bus
, vendor
, device
, &index
, devp
))
214 return device_probe(*devp
);
221 int dm_pci_find_class(uint find_class
, int index
, struct udevice
**devp
)
225 /* Scan all known buses */
226 for (pci_find_first_device(&dev
);
228 pci_find_next_device(&dev
)) {
229 struct pci_child_platdata
*pplat
= dev_get_parent_platdata(dev
);
231 if (pplat
->class == find_class
&& !index
--) {
233 return device_probe(*devp
);
241 int pci_bus_write_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
242 unsigned long value
, enum pci_size_t size
)
244 struct dm_pci_ops
*ops
;
246 ops
= pci_get_ops(bus
);
247 if (!ops
->write_config
)
249 return ops
->write_config(bus
, bdf
, offset
, value
, size
);
252 int pci_bus_clrset_config32(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
258 ret
= pci_bus_read_config(bus
, bdf
, offset
, &val
, PCI_SIZE_32
);
264 return pci_bus_write_config(bus
, bdf
, offset
, val
, PCI_SIZE_32
);
267 int pci_write_config(pci_dev_t bdf
, int offset
, unsigned long value
,
268 enum pci_size_t size
)
273 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
277 return pci_bus_write_config(bus
, bdf
, offset
, value
, size
);
280 int dm_pci_write_config(struct udevice
*dev
, int offset
, unsigned long value
,
281 enum pci_size_t size
)
285 for (bus
= dev
; device_is_on_pci_bus(bus
);)
287 return pci_bus_write_config(bus
, dm_pci_get_bdf(dev
), offset
, value
,
291 int pci_write_config32(pci_dev_t bdf
, int offset
, u32 value
)
293 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_32
);
296 int pci_write_config16(pci_dev_t bdf
, int offset
, u16 value
)
298 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_16
);
301 int pci_write_config8(pci_dev_t bdf
, int offset
, u8 value
)
303 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_8
);
306 int dm_pci_write_config8(struct udevice
*dev
, int offset
, u8 value
)
308 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_8
);
311 int dm_pci_write_config16(struct udevice
*dev
, int offset
, u16 value
)
313 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_16
);
316 int dm_pci_write_config32(struct udevice
*dev
, int offset
, u32 value
)
318 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_32
);
321 int pci_bus_read_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
322 unsigned long *valuep
, enum pci_size_t size
)
324 struct dm_pci_ops
*ops
;
326 ops
= pci_get_ops(bus
);
327 if (!ops
->read_config
)
329 return ops
->read_config(bus
, bdf
, offset
, valuep
, size
);
332 int pci_read_config(pci_dev_t bdf
, int offset
, unsigned long *valuep
,
333 enum pci_size_t size
)
338 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
342 return pci_bus_read_config(bus
, bdf
, offset
, valuep
, size
);
345 int dm_pci_read_config(struct udevice
*dev
, int offset
, unsigned long *valuep
,
346 enum pci_size_t size
)
350 for (bus
= dev
; device_is_on_pci_bus(bus
);)
352 return pci_bus_read_config(bus
, dm_pci_get_bdf(dev
), offset
, valuep
,
356 int pci_read_config32(pci_dev_t bdf
, int offset
, u32
*valuep
)
361 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_32
);
369 int pci_read_config16(pci_dev_t bdf
, int offset
, u16
*valuep
)
374 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_16
);
382 int pci_read_config8(pci_dev_t bdf
, int offset
, u8
*valuep
)
387 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_8
);
395 int dm_pci_read_config8(struct udevice
*dev
, int offset
, u8
*valuep
)
400 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_8
);
408 int dm_pci_read_config16(struct udevice
*dev
, int offset
, u16
*valuep
)
413 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_16
);
421 int dm_pci_read_config32(struct udevice
*dev
, int offset
, u32
*valuep
)
426 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_32
);
434 int dm_pci_clrset_config8(struct udevice
*dev
, int offset
, u32 clr
, u32 set
)
439 ret
= dm_pci_read_config8(dev
, offset
, &val
);
445 return dm_pci_write_config8(dev
, offset
, val
);
448 int dm_pci_clrset_config16(struct udevice
*dev
, int offset
, u32 clr
, u32 set
)
453 ret
= dm_pci_read_config16(dev
, offset
, &val
);
459 return dm_pci_write_config16(dev
, offset
, val
);
462 int dm_pci_clrset_config32(struct udevice
*dev
, int offset
, u32 clr
, u32 set
)
467 ret
= dm_pci_read_config32(dev
, offset
, &val
);
473 return dm_pci_write_config32(dev
, offset
, val
);
476 static void set_vga_bridge_bits(struct udevice
*dev
)
478 struct udevice
*parent
= dev
->parent
;
481 while (parent
->seq
!= 0) {
482 dm_pci_read_config16(parent
, PCI_BRIDGE_CONTROL
, &bc
);
483 bc
|= PCI_BRIDGE_CTL_VGA
;
484 dm_pci_write_config16(parent
, PCI_BRIDGE_CONTROL
, bc
);
485 parent
= parent
->parent
;
489 int pci_auto_config_devices(struct udevice
*bus
)
491 struct pci_controller
*hose
= bus
->uclass_priv
;
492 struct pci_child_platdata
*pplat
;
493 unsigned int sub_bus
;
498 debug("%s: start\n", __func__
);
499 pciauto_config_init(hose
);
500 for (ret
= device_find_first_child(bus
, &dev
);
502 ret
= device_find_next_child(&dev
)) {
503 unsigned int max_bus
;
506 debug("%s: device %s\n", __func__
, dev
->name
);
507 ret
= dm_pciauto_config_device(dev
);
511 sub_bus
= max(sub_bus
, max_bus
);
513 pplat
= dev_get_parent_platdata(dev
);
514 if (pplat
->class == (PCI_CLASS_DISPLAY_VGA
<< 8))
515 set_vga_bridge_bits(dev
);
517 debug("%s: done\n", __func__
);
522 int dm_pci_hose_probe_bus(struct udevice
*bus
)
527 debug("%s\n", __func__
);
529 sub_bus
= pci_get_bus_max() + 1;
530 debug("%s: bus = %d/%s\n", __func__
, sub_bus
, bus
->name
);
531 dm_pciauto_prescan_setup_bridge(bus
, sub_bus
);
533 ret
= device_probe(bus
);
535 debug("%s: Cannot probe bus %s: %d\n", __func__
, bus
->name
,
539 if (sub_bus
!= bus
->seq
) {
540 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
541 __func__
, bus
->name
, bus
->seq
, sub_bus
);
544 sub_bus
= pci_get_bus_max();
545 dm_pciauto_postscan_setup_bridge(bus
, sub_bus
);
551 * pci_match_one_device - Tell if a PCI device structure has a matching
552 * PCI device id structure
553 * @id: single PCI device id structure to match
554 * @find: the PCI device id structure to match against
556 * Returns true if the finding pci_device_id structure matched or false if
559 static bool pci_match_one_id(const struct pci_device_id
*id
,
560 const struct pci_device_id
*find
)
562 if ((id
->vendor
== PCI_ANY_ID
|| id
->vendor
== find
->vendor
) &&
563 (id
->device
== PCI_ANY_ID
|| id
->device
== find
->device
) &&
564 (id
->subvendor
== PCI_ANY_ID
|| id
->subvendor
== find
->subvendor
) &&
565 (id
->subdevice
== PCI_ANY_ID
|| id
->subdevice
== find
->subdevice
) &&
566 !((id
->class ^ find
->class) & id
->class_mask
))
573 * pci_find_and_bind_driver() - Find and bind the right PCI driver
575 * This only looks at certain fields in the descriptor.
577 * @parent: Parent bus
578 * @find_id: Specification of the driver to find
579 * @bdf: Bus/device/function addreess - see PCI_BDF()
580 * @devp: Returns a pointer to the device created
581 * @return 0 if OK, -EPERM if the device is not needed before relocation and
582 * therefore was not created, other -ve value on error
584 static int pci_find_and_bind_driver(struct udevice
*parent
,
585 struct pci_device_id
*find_id
,
586 pci_dev_t bdf
, struct udevice
**devp
)
588 struct pci_driver_entry
*start
, *entry
;
597 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__
,
598 find_id
->vendor
, find_id
->device
);
599 start
= ll_entry_start(struct pci_driver_entry
, pci_driver_entry
);
600 n_ents
= ll_entry_count(struct pci_driver_entry
, pci_driver_entry
);
601 for (entry
= start
; entry
!= start
+ n_ents
; entry
++) {
602 const struct pci_device_id
*id
;
604 const struct driver
*drv
;
606 for (id
= entry
->match
;
607 id
->vendor
|| id
->subvendor
|| id
->class_mask
;
609 if (!pci_match_one_id(id
, find_id
))
615 * In the pre-relocation phase, we only bind devices
616 * whose driver has the DM_FLAG_PRE_RELOC set, to save
617 * precious memory space as on some platforms as that
618 * space is pretty limited (ie: using Cache As RAM).
620 if (!(gd
->flags
& GD_FLG_RELOC
) &&
621 !(drv
->flags
& DM_FLAG_PRE_RELOC
))
625 * We could pass the descriptor to the driver as
626 * platdata (instead of NULL) and allow its bind()
627 * method to return -ENOENT if it doesn't support this
628 * device. That way we could continue the search to
629 * find another driver. For now this doesn't seem
630 * necesssary, so just bind the first match.
632 ret
= device_bind(parent
, drv
, drv
->name
, NULL
, -1,
636 debug("%s: Match found: %s\n", __func__
, drv
->name
);
637 dev
->driver_data
= find_id
->driver_data
;
643 bridge
= (find_id
->class >> 8) == PCI_CLASS_BRIDGE_PCI
;
645 * In the pre-relocation phase, we only bind bridge devices to save
646 * precious memory space as on some platforms as that space is pretty
647 * limited (ie: using Cache As RAM).
649 if (!(gd
->flags
& GD_FLG_RELOC
) && !bridge
)
652 /* Bind a generic driver so that the device can be used */
653 sprintf(name
, "pci_%x:%x.%x", parent
->seq
, PCI_DEV(bdf
),
658 drv
= bridge
? "pci_bridge_drv" : "pci_generic_drv";
660 ret
= device_bind_driver(parent
, drv
, str
, devp
);
662 debug("%s: Failed to bind generic driver: %d\n", __func__
, ret
);
666 debug("%s: No match found: bound generic driver instead\n", __func__
);
671 debug("%s: No match found: error %d\n", __func__
, ret
);
675 int pci_bind_bus_devices(struct udevice
*bus
)
677 ulong vendor
, device
;
684 end
= PCI_BDF(bus
->seq
, PCI_MAX_PCI_DEVICES
- 1,
685 PCI_MAX_PCI_FUNCTIONS
- 1);
686 for (bdf
= PCI_BDF(bus
->seq
, 0, 0); bdf
<= end
;
687 bdf
+= PCI_BDF(0, 0, 1)) {
688 struct pci_child_platdata
*pplat
;
692 if (PCI_FUNC(bdf
) && !found_multi
)
694 /* Check only the first access, we don't expect problems */
695 ret
= pci_bus_read_config(bus
, bdf
, PCI_HEADER_TYPE
,
696 &header_type
, PCI_SIZE_8
);
699 pci_bus_read_config(bus
, bdf
, PCI_VENDOR_ID
, &vendor
,
701 if (vendor
== 0xffff || vendor
== 0x0000)
705 found_multi
= header_type
& 0x80;
707 debug("%s: bus %d/%s: found device %x, function %d\n", __func__
,
708 bus
->seq
, bus
->name
, PCI_DEV(bdf
), PCI_FUNC(bdf
));
709 pci_bus_read_config(bus
, bdf
, PCI_DEVICE_ID
, &device
,
711 pci_bus_read_config(bus
, bdf
, PCI_CLASS_REVISION
, &class,
715 /* Find this device in the device tree */
716 ret
= pci_bus_find_devfn(bus
, PCI_MASK_BUS(bdf
), &dev
);
718 /* If nothing in the device tree, bind a device */
719 if (ret
== -ENODEV
) {
720 struct pci_device_id find_id
;
723 memset(&find_id
, '\0', sizeof(find_id
));
724 find_id
.vendor
= vendor
;
725 find_id
.device
= device
;
726 find_id
.class = class;
727 if ((header_type
& 0x7f) == PCI_HEADER_TYPE_NORMAL
) {
728 pci_bus_read_config(bus
, bdf
,
729 PCI_SUBSYSTEM_VENDOR_ID
,
731 find_id
.subvendor
= val
& 0xffff;
732 find_id
.subdevice
= val
>> 16;
734 ret
= pci_find_and_bind_driver(bus
, &find_id
, bdf
,
742 /* Update the platform data */
743 pplat
= dev_get_parent_platdata(dev
);
744 pplat
->devfn
= PCI_MASK_BUS(bdf
);
745 pplat
->vendor
= vendor
;
746 pplat
->device
= device
;
747 pplat
->class = class;
752 printf("Cannot read bus configuration: %d\n", ret
);
757 static int decode_regions(struct pci_controller
*hose
, const void *blob
,
758 int parent_node
, int node
)
760 int pci_addr_cells
, addr_cells
, size_cells
;
761 phys_addr_t base
= 0, size
;
762 int cells_per_record
;
767 prop
= fdt_getprop(blob
, node
, "ranges", &len
);
770 pci_addr_cells
= fdt_address_cells(blob
, node
);
771 addr_cells
= fdt_address_cells(blob
, parent_node
);
772 size_cells
= fdt_size_cells(blob
, node
);
774 /* PCI addresses are always 3-cells */
776 cells_per_record
= pci_addr_cells
+ addr_cells
+ size_cells
;
777 hose
->region_count
= 0;
778 debug("%s: len=%d, cells_per_record=%d\n", __func__
, len
,
780 for (i
= 0; i
< MAX_PCI_REGIONS
; i
++, len
-= cells_per_record
) {
781 u64 pci_addr
, addr
, size
;
787 if (len
< cells_per_record
)
789 flags
= fdt32_to_cpu(prop
[0]);
790 space_code
= (flags
>> 24) & 3;
791 pci_addr
= fdtdec_get_number(prop
+ 1, 2);
792 prop
+= pci_addr_cells
;
793 addr
= fdtdec_get_number(prop
, addr_cells
);
795 size
= fdtdec_get_number(prop
, size_cells
);
797 debug("%s: region %d, pci_addr=%" PRIx64
", addr=%" PRIx64
798 ", size=%" PRIx64
", space_code=%d\n", __func__
,
799 hose
->region_count
, pci_addr
, addr
, size
, space_code
);
800 if (space_code
& 2) {
801 type
= flags
& (1U << 30) ? PCI_REGION_PREFETCH
:
803 } else if (space_code
& 1) {
804 type
= PCI_REGION_IO
;
809 for (i
= 0; i
< hose
->region_count
; i
++) {
810 if (hose
->regions
[i
].flags
== type
)
814 pos
= hose
->region_count
++;
815 debug(" - type=%d, pos=%d\n", type
, pos
);
816 pci_set_region(hose
->regions
+ pos
, pci_addr
, addr
, size
, type
);
819 /* Add a region for our local memory */
821 #ifdef CONFIG_SYS_SDRAM_BASE
822 base
= CONFIG_SYS_SDRAM_BASE
;
824 if (gd
->pci_ram_top
&& gd
->pci_ram_top
< base
+ size
)
825 size
= gd
->pci_ram_top
- base
;
826 pci_set_region(hose
->regions
+ hose
->region_count
++, base
, base
,
827 size
, PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
832 static int pci_uclass_pre_probe(struct udevice
*bus
)
834 struct pci_controller
*hose
;
837 debug("%s, bus=%d/%s, parent=%s\n", __func__
, bus
->seq
, bus
->name
,
839 hose
= bus
->uclass_priv
;
841 /* For bridges, use the top-level PCI controller */
842 if (!device_is_on_pci_bus(bus
)) {
844 ret
= decode_regions(hose
, gd
->fdt_blob
,
845 dev_of_offset(bus
->parent
),
848 debug("%s: Cannot decode regions\n", __func__
);
852 struct pci_controller
*parent_hose
;
854 parent_hose
= dev_get_uclass_priv(bus
->parent
);
855 hose
->ctlr
= parent_hose
->bus
;
858 hose
->first_busno
= bus
->seq
;
859 hose
->last_busno
= bus
->seq
;
864 static int pci_uclass_post_probe(struct udevice
*bus
)
868 debug("%s: probing bus %d\n", __func__
, bus
->seq
);
869 ret
= pci_bind_bus_devices(bus
);
873 #ifdef CONFIG_PCI_PNP
874 ret
= pci_auto_config_devices(bus
);
879 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
881 * Per Intel FSP specification, we should call FSP notify API to
882 * inform FSP that PCI enumeration has been done so that FSP will
883 * do any necessary initialization as required by the chipset's
884 * BIOS Writer's Guide (BWG).
886 * Unfortunately we have to put this call here as with driver model,
887 * the enumeration is all done on a lazy basis as needed, so until
888 * something is touched on PCI it won't happen.
890 * Note we only call this 1) after U-Boot is relocated, and 2)
891 * root bus has finished probing.
893 if ((gd
->flags
& GD_FLG_RELOC
) && (bus
->seq
== 0)) {
894 ret
= fsp_init_phase_pci();
903 static int pci_uclass_child_post_bind(struct udevice
*dev
)
905 struct pci_child_platdata
*pplat
;
906 struct fdt_pci_addr addr
;
909 if (dev_of_offset(dev
) == -1)
913 * We could read vendor, device, class if available. But for now we
914 * just check the address.
916 pplat
= dev_get_parent_platdata(dev
);
917 ret
= fdtdec_get_pci_addr(gd
->fdt_blob
, dev_of_offset(dev
),
918 FDT_PCI_SPACE_CONFIG
, "reg", &addr
);
924 /* extract the devfn from fdt_pci_addr */
925 pplat
->devfn
= addr
.phys_hi
& 0xff00;
931 static int pci_bridge_read_config(struct udevice
*bus
, pci_dev_t bdf
,
932 uint offset
, ulong
*valuep
,
933 enum pci_size_t size
)
935 struct pci_controller
*hose
= bus
->uclass_priv
;
937 return pci_bus_read_config(hose
->ctlr
, bdf
, offset
, valuep
, size
);
940 static int pci_bridge_write_config(struct udevice
*bus
, pci_dev_t bdf
,
941 uint offset
, ulong value
,
942 enum pci_size_t size
)
944 struct pci_controller
*hose
= bus
->uclass_priv
;
946 return pci_bus_write_config(hose
->ctlr
, bdf
, offset
, value
, size
);
949 static int skip_to_next_device(struct udevice
*bus
, struct udevice
**devp
)
955 * Scan through all the PCI controllers. On x86 there will only be one
956 * but that is not necessarily true on other hardware.
959 device_find_first_child(bus
, &dev
);
964 ret
= uclass_next_device(&bus
);
972 int pci_find_next_device(struct udevice
**devp
)
974 struct udevice
*child
= *devp
;
975 struct udevice
*bus
= child
->parent
;
978 /* First try all the siblings */
981 device_find_next_child(&child
);
988 /* We ran out of siblings. Try the next bus */
989 ret
= uclass_next_device(&bus
);
993 return bus
? skip_to_next_device(bus
, devp
) : 0;
996 int pci_find_first_device(struct udevice
**devp
)
1002 ret
= uclass_first_device(UCLASS_PCI
, &bus
);
1006 return skip_to_next_device(bus
, devp
);
1009 ulong
pci_conv_32_to_size(ulong value
, uint offset
, enum pci_size_t size
)
1013 return (value
>> ((offset
& 3) * 8)) & 0xff;
1015 return (value
>> ((offset
& 2) * 8)) & 0xffff;
1021 ulong
pci_conv_size_to_32(ulong old
, ulong value
, uint offset
,
1022 enum pci_size_t size
)
1025 uint val_mask
, shift
;
1040 shift
= (offset
& off_mask
) * 8;
1041 ldata
= (value
& val_mask
) << shift
;
1042 mask
= val_mask
<< shift
;
1043 value
= (old
& ~mask
) | ldata
;
1048 int pci_get_regions(struct udevice
*dev
, struct pci_region
**iop
,
1049 struct pci_region
**memp
, struct pci_region
**prefp
)
1051 struct udevice
*bus
= pci_get_controller(dev
);
1052 struct pci_controller
*hose
= dev_get_uclass_priv(bus
);
1058 for (i
= 0; i
< hose
->region_count
; i
++) {
1059 switch (hose
->regions
[i
].flags
) {
1061 if (!*iop
|| (*iop
)->size
< hose
->regions
[i
].size
)
1062 *iop
= hose
->regions
+ i
;
1064 case PCI_REGION_MEM
:
1065 if (!*memp
|| (*memp
)->size
< hose
->regions
[i
].size
)
1066 *memp
= hose
->regions
+ i
;
1068 case (PCI_REGION_MEM
| PCI_REGION_PREFETCH
):
1069 if (!*prefp
|| (*prefp
)->size
< hose
->regions
[i
].size
)
1070 *prefp
= hose
->regions
+ i
;
1075 return (*iop
!= NULL
) + (*memp
!= NULL
) + (*prefp
!= NULL
);
1078 u32
dm_pci_read_bar32(struct udevice
*dev
, int barnum
)
1083 bar
= PCI_BASE_ADDRESS_0
+ barnum
* 4;
1084 dm_pci_read_config32(dev
, bar
, &addr
);
1085 if (addr
& PCI_BASE_ADDRESS_SPACE_IO
)
1086 return addr
& PCI_BASE_ADDRESS_IO_MASK
;
1088 return addr
& PCI_BASE_ADDRESS_MEM_MASK
;
1091 void dm_pci_write_bar32(struct udevice
*dev
, int barnum
, u32 addr
)
1095 bar
= PCI_BASE_ADDRESS_0
+ barnum
* 4;
1096 dm_pci_write_config32(dev
, bar
, addr
);
1099 static int _dm_pci_bus_to_phys(struct udevice
*ctlr
,
1100 pci_addr_t bus_addr
, unsigned long flags
,
1101 unsigned long skip_mask
, phys_addr_t
*pa
)
1103 struct pci_controller
*hose
= dev_get_uclass_priv(ctlr
);
1104 struct pci_region
*res
;
1107 for (i
= 0; i
< hose
->region_count
; i
++) {
1108 res
= &hose
->regions
[i
];
1110 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
1113 if (res
->flags
& skip_mask
)
1116 if (bus_addr
>= res
->bus_start
&&
1117 (bus_addr
- res
->bus_start
) < res
->size
) {
1118 *pa
= (bus_addr
- res
->bus_start
+ res
->phys_start
);
1126 phys_addr_t
dm_pci_bus_to_phys(struct udevice
*dev
, pci_addr_t bus_addr
,
1127 unsigned long flags
)
1129 phys_addr_t phys_addr
= 0;
1130 struct udevice
*ctlr
;
1133 /* The root controller has the region information */
1134 ctlr
= pci_get_controller(dev
);
1137 * if PCI_REGION_MEM is set we do a two pass search with preference
1138 * on matches that don't have PCI_REGION_SYS_MEMORY set
1140 if ((flags
& PCI_REGION_TYPE
) == PCI_REGION_MEM
) {
1141 ret
= _dm_pci_bus_to_phys(ctlr
, bus_addr
,
1142 flags
, PCI_REGION_SYS_MEMORY
,
1148 ret
= _dm_pci_bus_to_phys(ctlr
, bus_addr
, flags
, 0, &phys_addr
);
1151 puts("pci_hose_bus_to_phys: invalid physical address\n");
1156 int _dm_pci_phys_to_bus(struct udevice
*dev
, phys_addr_t phys_addr
,
1157 unsigned long flags
, unsigned long skip_mask
,
1160 struct pci_region
*res
;
1161 struct udevice
*ctlr
;
1162 pci_addr_t bus_addr
;
1164 struct pci_controller
*hose
;
1166 /* The root controller has the region information */
1167 ctlr
= pci_get_controller(dev
);
1168 hose
= dev_get_uclass_priv(ctlr
);
1170 for (i
= 0; i
< hose
->region_count
; i
++) {
1171 res
= &hose
->regions
[i
];
1173 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
1176 if (res
->flags
& skip_mask
)
1179 bus_addr
= phys_addr
- res
->phys_start
+ res
->bus_start
;
1181 if (bus_addr
>= res
->bus_start
&&
1182 (bus_addr
- res
->bus_start
) < res
->size
) {
1191 pci_addr_t
dm_pci_phys_to_bus(struct udevice
*dev
, phys_addr_t phys_addr
,
1192 unsigned long flags
)
1194 pci_addr_t bus_addr
= 0;
1198 * if PCI_REGION_MEM is set we do a two pass search with preference
1199 * on matches that don't have PCI_REGION_SYS_MEMORY set
1201 if ((flags
& PCI_REGION_TYPE
) == PCI_REGION_MEM
) {
1202 ret
= _dm_pci_phys_to_bus(dev
, phys_addr
, flags
,
1203 PCI_REGION_SYS_MEMORY
, &bus_addr
);
1208 ret
= _dm_pci_phys_to_bus(dev
, phys_addr
, flags
, 0, &bus_addr
);
1211 puts("pci_hose_phys_to_bus: invalid physical address\n");
1216 void *dm_pci_map_bar(struct udevice
*dev
, int bar
, int flags
)
1218 pci_addr_t pci_bus_addr
;
1221 /* read BAR address */
1222 dm_pci_read_config32(dev
, bar
, &bar_response
);
1223 pci_bus_addr
= (pci_addr_t
)(bar_response
& ~0xf);
1226 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1227 * isn't actualy used on any platform because u-boot assumes a static
1228 * linear mapping. In the future, this could read the BAR size
1229 * and pass that as the size if needed.
1231 return dm_pci_bus_to_virt(dev
, pci_bus_addr
, flags
, 0, MAP_NOCACHE
);
1234 UCLASS_DRIVER(pci
) = {
1237 .flags
= DM_UC_FLAG_SEQ_ALIAS
,
1238 .post_bind
= dm_scan_fdt_dev
,
1239 .pre_probe
= pci_uclass_pre_probe
,
1240 .post_probe
= pci_uclass_post_probe
,
1241 .child_post_bind
= pci_uclass_child_post_bind
,
1242 .per_device_auto_alloc_size
= sizeof(struct pci_controller
),
1243 .per_child_platdata_auto_alloc_size
=
1244 sizeof(struct pci_child_platdata
),
1247 static const struct dm_pci_ops pci_bridge_ops
= {
1248 .read_config
= pci_bridge_read_config
,
1249 .write_config
= pci_bridge_write_config
,
1252 static const struct udevice_id pci_bridge_ids
[] = {
1253 { .compatible
= "pci-bridge" },
1257 U_BOOT_DRIVER(pci_bridge_drv
) = {
1258 .name
= "pci_bridge_drv",
1260 .of_match
= pci_bridge_ids
,
1261 .ops
= &pci_bridge_ops
,
1264 UCLASS_DRIVER(pci_generic
) = {
1265 .id
= UCLASS_PCI_GENERIC
,
1266 .name
= "pci_generic",
1269 static const struct udevice_id pci_generic_ids
[] = {
1270 { .compatible
= "pci-generic" },
1274 U_BOOT_DRIVER(pci_generic_drv
) = {
1275 .name
= "pci_generic_drv",
1276 .id
= UCLASS_PCI_GENERIC
,
1277 .of_match
= pci_generic_ids
,
1282 struct udevice
*bus
;
1285 * Enumerate all known controller devices. Enumeration has the side-
1286 * effect of probing them, so PCIe devices will be enumerated too.
1288 for (uclass_first_device(UCLASS_PCI
, &bus
);
1290 uclass_next_device(&bus
)) {