2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/processor.h>
22 #define PCI_HOSE_OP(rw, size, type) \
23 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
25 int offset, type value) \
27 return hose->rw##_##size(hose, dev, offset, value); \
30 PCI_HOSE_OP(read
, byte
, u8
*)
31 PCI_HOSE_OP(read
, word
, u16
*)
32 PCI_HOSE_OP(read
, dword
, u32
*)
33 PCI_HOSE_OP(write
, byte
, u8
)
34 PCI_HOSE_OP(write
, word
, u16
)
35 PCI_HOSE_OP(write
, dword
, u32
)
37 #define PCI_OP(rw, size, type, error_code) \
38 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
40 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
48 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
51 PCI_OP(read
, byte
, u8
*, *value
= 0xff)
52 PCI_OP(read
, word
, u16
*, *value
= 0xffff)
53 PCI_OP(read
, dword
, u32
*, *value
= 0xffffffff)
54 PCI_OP(write
, byte
, u8
, )
55 PCI_OP(write
, word
, u16
, )
56 PCI_OP(write
, dword
, u32
, )
58 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
59 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
61 int offset, type val) \
65 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
70 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
75 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
76 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
78 int offset, type val) \
80 u32 val32, mask, ldata, shift; \
82 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
85 shift = ((offset & (int)off_mask) * 8); \
86 ldata = (((unsigned long)val) & val_mask) << shift; \
87 mask = val_mask << shift; \
88 val32 = (val32 & ~mask) | ldata; \
90 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
96 PCI_READ_VIA_DWORD_OP(byte
, u8
*, 0x03)
97 PCI_READ_VIA_DWORD_OP(word
, u16
*, 0x02)
98 PCI_WRITE_VIA_DWORD_OP(byte
, u8
, 0x03, 0x000000ff)
99 PCI_WRITE_VIA_DWORD_OP(word
, u16
, 0x02, 0x0000ffff)
101 /* Get a virtual address associated with a BAR region */
102 void *pci_map_bar(pci_dev_t pdev
, int bar
, int flags
)
104 pci_addr_t pci_bus_addr
;
107 /* read BAR address */
108 pci_read_config_dword(pdev
, bar
, &bar_response
);
109 pci_bus_addr
= (pci_addr_t
)(bar_response
& ~0xf);
112 * Pass "0" as the length argument to pci_bus_to_virt. The arg
113 * isn't actualy used on any platform because u-boot assumes a static
114 * linear mapping. In the future, this could read the BAR size
115 * and pass that as the size if needed.
117 return pci_bus_to_virt(pdev
, pci_bus_addr
, flags
, 0, MAP_NOCACHE
);
124 static struct pci_controller
* hose_head
;
126 void pci_register_hose(struct pci_controller
* hose
)
128 struct pci_controller
**phose
= &hose_head
;
131 phose
= &(*phose
)->next
;
138 struct pci_controller
*pci_bus_to_hose(int bus
)
140 struct pci_controller
*hose
;
142 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
143 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
147 printf("pci_bus_to_hose() failed\n");
151 struct pci_controller
*find_hose_by_cfg_addr(void *cfg_addr
)
153 struct pci_controller
*hose
;
155 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
156 if (hose
->cfg_addr
== cfg_addr
)
163 int pci_last_busno(void)
165 struct pci_controller
*hose
= hose_head
;
173 return hose
->last_busno
;
176 pci_dev_t
pci_find_devices(struct pci_device_id
*ids
, int index
)
178 struct pci_controller
* hose
;
182 int i
, bus
, found_multi
= 0;
184 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
185 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
186 for (bus
= hose
->last_busno
; bus
>= hose
->first_busno
; bus
--)
188 for (bus
= hose
->first_busno
; bus
<= hose
->last_busno
; bus
++)
190 for (bdf
= PCI_BDF(bus
, 0, 0);
191 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
192 bdf
< PCI_BDF(bus
, PCI_MAX_PCI_DEVICES
- 1,
193 PCI_MAX_PCI_FUNCTIONS
- 1);
195 bdf
< PCI_BDF(bus
+ 1, 0, 0);
197 bdf
+= PCI_BDF(0, 0, 1)) {
198 if (pci_skip_dev(hose
, bdf
))
201 if (!PCI_FUNC(bdf
)) {
202 pci_read_config_byte(bdf
,
206 found_multi
= header_type
& 0x80;
212 pci_read_config_word(bdf
,
215 pci_read_config_word(bdf
,
219 for (i
= 0; ids
[i
].vendor
!= 0; i
++) {
220 if (vendor
== ids
[i
].vendor
&&
221 device
== ids
[i
].device
) {
234 pci_dev_t
pci_find_device(unsigned int vendor
, unsigned int device
, int index
)
236 static struct pci_device_id ids
[2] = {{}, {0, 0}};
238 ids
[0].vendor
= vendor
;
239 ids
[0].device
= device
;
241 return pci_find_devices(ids
, index
);
248 int __pci_hose_phys_to_bus(struct pci_controller
*hose
,
249 phys_addr_t phys_addr
,
251 unsigned long skip_mask
,
254 struct pci_region
*res
;
258 for (i
= 0; i
< hose
->region_count
; i
++) {
259 res
= &hose
->regions
[i
];
261 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
264 if (res
->flags
& skip_mask
)
267 bus_addr
= phys_addr
- res
->phys_start
+ res
->bus_start
;
269 if (bus_addr
>= res
->bus_start
&&
270 bus_addr
< res
->bus_start
+ res
->size
) {
279 pci_addr_t
pci_hose_phys_to_bus (struct pci_controller
*hose
,
280 phys_addr_t phys_addr
,
283 pci_addr_t bus_addr
= 0;
287 puts("pci_hose_phys_to_bus: invalid hose\n");
292 * if PCI_REGION_MEM is set we do a two pass search with preference
293 * on matches that don't have PCI_REGION_SYS_MEMORY set
295 if ((flags
& PCI_REGION_MEM
) == PCI_REGION_MEM
) {
296 ret
= __pci_hose_phys_to_bus(hose
, phys_addr
,
297 flags
, PCI_REGION_SYS_MEMORY
, &bus_addr
);
302 ret
= __pci_hose_phys_to_bus(hose
, phys_addr
, flags
, 0, &bus_addr
);
305 puts("pci_hose_phys_to_bus: invalid physical address\n");
310 int __pci_hose_bus_to_phys(struct pci_controller
*hose
,
313 unsigned long skip_mask
,
316 struct pci_region
*res
;
319 for (i
= 0; i
< hose
->region_count
; i
++) {
320 res
= &hose
->regions
[i
];
322 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
325 if (res
->flags
& skip_mask
)
328 if (bus_addr
>= res
->bus_start
&&
329 (bus_addr
- res
->bus_start
) < res
->size
) {
330 *pa
= (bus_addr
- res
->bus_start
+ res
->phys_start
);
338 phys_addr_t
pci_hose_bus_to_phys(struct pci_controller
* hose
,
342 phys_addr_t phys_addr
= 0;
346 puts("pci_hose_bus_to_phys: invalid hose\n");
351 * if PCI_REGION_MEM is set we do a two pass search with preference
352 * on matches that don't have PCI_REGION_SYS_MEMORY set
354 if ((flags
& PCI_REGION_MEM
) == PCI_REGION_MEM
) {
355 ret
= __pci_hose_bus_to_phys(hose
, bus_addr
,
356 flags
, PCI_REGION_SYS_MEMORY
, &phys_addr
);
361 ret
= __pci_hose_bus_to_phys(hose
, bus_addr
, flags
, 0, &phys_addr
);
364 puts("pci_hose_bus_to_phys: invalid physical address\n");
373 int pci_hose_config_device(struct pci_controller
*hose
,
377 unsigned long command
)
380 unsigned int old_command
;
381 pci_addr_t bar_value
;
384 int bar
, found_mem64
;
386 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io
,
389 pci_hose_write_config_dword(hose
, dev
, PCI_COMMAND
, 0);
391 for (bar
= PCI_BASE_ADDRESS_0
; bar
<= PCI_BASE_ADDRESS_5
; bar
+= 4) {
392 pci_hose_write_config_dword(hose
, dev
, bar
, 0xffffffff);
393 pci_hose_read_config_dword(hose
, dev
, bar
, &bar_response
);
400 /* Check the BAR type and set our address mask */
401 if (bar_response
& PCI_BASE_ADDRESS_SPACE
) {
402 bar_size
= ~(bar_response
& PCI_BASE_ADDRESS_IO_MASK
) + 1;
403 /* round up region base address to a multiple of size */
404 io
= ((io
- 1) | (bar_size
- 1)) + 1;
406 /* compute new region base address */
409 if ((bar_response
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
) ==
410 PCI_BASE_ADDRESS_MEM_TYPE_64
) {
411 u32 bar_response_upper
;
413 pci_hose_write_config_dword(hose
, dev
, bar
+ 4,
415 pci_hose_read_config_dword(hose
, dev
, bar
+ 4,
416 &bar_response_upper
);
418 bar64
= ((u64
)bar_response_upper
<< 32) | bar_response
;
420 bar_size
= ~(bar64
& PCI_BASE_ADDRESS_MEM_MASK
) + 1;
423 bar_size
= (u32
)(~(bar_response
& PCI_BASE_ADDRESS_MEM_MASK
) + 1);
426 /* round up region base address to multiple of size */
427 mem
= ((mem
- 1) | (bar_size
- 1)) + 1;
429 /* compute new region base address */
430 mem
= mem
+ bar_size
;
433 /* Write it out and update our limit */
434 pci_hose_write_config_dword (hose
, dev
, bar
, (u32
)bar_value
);
438 #ifdef CONFIG_SYS_PCI_64BIT
439 pci_hose_write_config_dword(hose
, dev
, bar
,
440 (u32
)(bar_value
>> 32));
442 pci_hose_write_config_dword(hose
, dev
, bar
, 0x00000000);
447 /* Configure Cache Line Size Register */
448 pci_hose_write_config_byte(hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
450 /* Configure Latency Timer */
451 pci_hose_write_config_byte(hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
453 /* Disable interrupt line, if device says it wants to use interrupts */
454 pci_hose_read_config_byte(hose
, dev
, PCI_INTERRUPT_PIN
, &pin
);
456 pci_hose_write_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
, 0xff);
459 pci_hose_read_config_dword(hose
, dev
, PCI_COMMAND
, &old_command
);
460 pci_hose_write_config_dword(hose
, dev
, PCI_COMMAND
,
461 (old_command
& 0xffff0000) | command
);
470 struct pci_config_table
*pci_find_config(struct pci_controller
*hose
,
471 unsigned short class,
478 struct pci_config_table
*table
;
480 for (table
= hose
->config_table
; table
&& table
->vendor
; table
++) {
481 if ((table
->vendor
== PCI_ANY_ID
|| table
->vendor
== vendor
) &&
482 (table
->device
== PCI_ANY_ID
|| table
->device
== device
) &&
483 (table
->class == PCI_ANY_ID
|| table
->class == class) &&
484 (table
->bus
== PCI_ANY_ID
|| table
->bus
== bus
) &&
485 (table
->dev
== PCI_ANY_ID
|| table
->dev
== dev
) &&
486 (table
->func
== PCI_ANY_ID
|| table
->func
== func
)) {
494 void pci_cfgfunc_config_device(struct pci_controller
*hose
,
496 struct pci_config_table
*entry
)
498 pci_hose_config_device(hose
, dev
, entry
->priv
[0], entry
->priv
[1],
502 void pci_cfgfunc_do_nothing(struct pci_controller
*hose
,
503 pci_dev_t dev
, struct pci_config_table
*entry
)
508 * HJF: Changed this to return int. I think this is required
509 * to get the correct result when scanning bridges
511 extern int pciauto_config_device(struct pci_controller
*hose
, pci_dev_t dev
);
513 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
514 const char * pci_class_str(u8
class)
517 case PCI_CLASS_NOT_DEFINED
:
518 return "Build before PCI Rev2.0";
520 case PCI_BASE_CLASS_STORAGE
:
521 return "Mass storage controller";
523 case PCI_BASE_CLASS_NETWORK
:
524 return "Network controller";
526 case PCI_BASE_CLASS_DISPLAY
:
527 return "Display controller";
529 case PCI_BASE_CLASS_MULTIMEDIA
:
530 return "Multimedia device";
532 case PCI_BASE_CLASS_MEMORY
:
533 return "Memory controller";
535 case PCI_BASE_CLASS_BRIDGE
:
536 return "Bridge device";
538 case PCI_BASE_CLASS_COMMUNICATION
:
539 return "Simple comm. controller";
541 case PCI_BASE_CLASS_SYSTEM
:
542 return "Base system peripheral";
544 case PCI_BASE_CLASS_INPUT
:
545 return "Input device";
547 case PCI_BASE_CLASS_DOCKING
:
548 return "Docking station";
550 case PCI_BASE_CLASS_PROCESSOR
:
553 case PCI_BASE_CLASS_SERIAL
:
554 return "Serial bus controller";
556 case PCI_BASE_CLASS_INTELLIGENT
:
557 return "Intelligent controller";
559 case PCI_BASE_CLASS_SATELLITE
:
560 return "Satellite controller";
562 case PCI_BASE_CLASS_CRYPT
:
563 return "Cryptographic device";
565 case PCI_BASE_CLASS_SIGNAL_PROCESSING
:
568 case PCI_CLASS_OTHERS
:
569 return "Does not fit any class";
576 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
578 __weak
int pci_skip_dev(struct pci_controller
*hose
, pci_dev_t dev
)
581 * Check if pci device should be skipped in configuration
583 if (dev
== PCI_BDF(hose
->first_busno
, 0, 0)) {
584 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
586 * Only skip configuration if "pciconfighost" is not set
588 if (getenv("pciconfighost") == NULL
)
598 #ifdef CONFIG_PCI_SCAN_SHOW
599 __weak
int pci_print_dev(struct pci_controller
*hose
, pci_dev_t dev
)
601 if (dev
== PCI_BDF(hose
->first_busno
, 0, 0))
606 #endif /* CONFIG_PCI_SCAN_SHOW */
608 int pci_hose_scan_bus(struct pci_controller
*hose
, int bus
)
610 unsigned int sub_bus
, found_multi
= 0;
611 unsigned short vendor
, device
, class;
612 unsigned char header_type
;
613 #ifndef CONFIG_PCI_PNP
614 struct pci_config_table
*cfg
;
617 #ifdef CONFIG_PCI_SCAN_SHOW
618 static int indent
= 0;
623 for (dev
= PCI_BDF(bus
,0,0);
624 dev
< PCI_BDF(bus
, PCI_MAX_PCI_DEVICES
- 1,
625 PCI_MAX_PCI_FUNCTIONS
- 1);
626 dev
+= PCI_BDF(0, 0, 1)) {
628 if (pci_skip_dev(hose
, dev
))
631 if (PCI_FUNC(dev
) && !found_multi
)
634 pci_hose_read_config_byte(hose
, dev
, PCI_HEADER_TYPE
, &header_type
);
636 pci_hose_read_config_word(hose
, dev
, PCI_VENDOR_ID
, &vendor
);
638 if (vendor
== 0xffff || vendor
== 0x0000)
642 found_multi
= header_type
& 0x80;
644 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
645 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
));
647 pci_hose_read_config_word(hose
, dev
, PCI_DEVICE_ID
, &device
);
648 pci_hose_read_config_word(hose
, dev
, PCI_CLASS_DEVICE
, &class);
650 #ifdef CONFIG_PCI_FIXUP_DEV
651 board_pci_fixup_dev(hose
, dev
, vendor
, device
, class);
654 #ifdef CONFIG_PCI_SCAN_SHOW
657 /* Print leading space, including bus indentation */
658 printf("%*c", indent
+ 1, ' ');
660 if (pci_print_dev(hose
, dev
)) {
661 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
662 PCI_BUS(dev
), PCI_DEV(dev
), 6 - indent
, PCI_FUNC(dev
),
663 vendor
, device
, pci_class_str(class >> 8));
667 #ifdef CONFIG_PCI_PNP
668 sub_bus
= max((unsigned int)pciauto_config_device(hose
, dev
),
671 cfg
= pci_find_config(hose
, class, vendor
, device
,
672 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
));
674 cfg
->config_device(hose
, dev
, cfg
);
675 sub_bus
= max(sub_bus
,
676 (unsigned int)hose
->current_busno
);
680 #ifdef CONFIG_PCI_SCAN_SHOW
685 hose
->fixup_irq(hose
, dev
);
691 int pci_hose_scan(struct pci_controller
*hose
)
693 #if defined(CONFIG_PCI_BOOTDELAY)
694 static int pcidelay_done
;
698 if (!pcidelay_done
) {
699 /* wait "pcidelay" ms (if defined)... */
700 s
= getenv("pcidelay");
702 int val
= simple_strtoul(s
, NULL
, 10);
703 for (i
= 0; i
< val
; i
++)
708 #endif /* CONFIG_PCI_BOOTDELAY */
711 * Start scan at current_busno.
712 * PCIe will start scan at first_busno+1.
714 /* For legacy support, ensure current >= first */
715 if (hose
->first_busno
> hose
->current_busno
)
716 hose
->current_busno
= hose
->first_busno
;
717 #ifdef CONFIG_PCI_PNP
718 pciauto_config_init(hose
);
720 return pci_hose_scan_bus(hose
, hose
->current_busno
);
727 /* now call board specific pci_init()... */
731 /* Returns the address of the requested capability structure within the
732 * device's PCI configuration space or 0 in case the device does not
735 int pci_hose_find_capability(struct pci_controller
*hose
, pci_dev_t dev
,
741 pci_hose_read_config_byte(hose
, dev
, PCI_HEADER_TYPE
, &hdr_type
);
743 pos
= pci_hose_find_cap_start(hose
, dev
, hdr_type
& 0x7F);
746 pos
= pci_find_cap(hose
, dev
, pos
, cap
);
751 /* Find the header pointer to the Capabilities*/
752 int pci_hose_find_cap_start(struct pci_controller
*hose
, pci_dev_t dev
,
757 pci_hose_read_config_word(hose
, dev
, PCI_STATUS
, &status
);
759 if (!(status
& PCI_STATUS_CAP_LIST
))
763 case PCI_HEADER_TYPE_NORMAL
:
764 case PCI_HEADER_TYPE_BRIDGE
:
765 return PCI_CAPABILITY_LIST
;
766 case PCI_HEADER_TYPE_CARDBUS
:
767 return PCI_CB_CAPABILITY_LIST
;
773 int pci_find_cap(struct pci_controller
*hose
, pci_dev_t dev
, int pos
, int cap
)
775 int ttl
= PCI_FIND_CAP_TTL
;
780 pci_hose_read_config_byte(hose
, dev
, pos
, &next_pos
);
781 if (next_pos
< CAP_START_POS
)
784 pos
= (int) next_pos
;
785 pci_hose_read_config_byte(hose
, dev
,
786 pos
+ PCI_CAP_LIST_ID
, &id
);
791 pos
+= PCI_CAP_LIST_NEXT
;