2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/processor.h>
38 #define PCI_HOSE_OP(rw, size, type) \
39 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
41 int offset, type value) \
43 return hose->rw##_##size(hose, dev, offset, value); \
46 PCI_HOSE_OP(read
, byte
, u8
*)
47 PCI_HOSE_OP(read
, word
, u16
*)
48 PCI_HOSE_OP(read
, dword
, u32
*)
49 PCI_HOSE_OP(write
, byte
, u8
)
50 PCI_HOSE_OP(write
, word
, u16
)
51 PCI_HOSE_OP(write
, dword
, u32
)
54 #define PCI_OP(rw, size, type, error_code) \
55 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
57 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
65 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
68 PCI_OP(read
, byte
, u8
*, *value
= 0xff)
69 PCI_OP(read
, word
, u16
*, *value
= 0xffff)
70 PCI_OP(read
, dword
, u32
*, *value
= 0xffffffff)
71 PCI_OP(write
, byte
, u8
, )
72 PCI_OP(write
, word
, u16
, )
73 PCI_OP(write
, dword
, u32
, )
74 #endif /* CONFIG_IXP425 */
76 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
77 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
79 int offset, type val) \
83 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
88 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
93 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
94 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
96 int offset, type val) \
98 u32 val32, mask, ldata, shift; \
100 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
103 shift = ((offset & (int)off_mask) * 8); \
104 ldata = (((unsigned long)val) & val_mask) << shift; \
105 mask = val_mask << shift; \
106 val32 = (val32 & ~mask) | ldata; \
108 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
114 PCI_READ_VIA_DWORD_OP(byte
, u8
*, 0x03)
115 PCI_READ_VIA_DWORD_OP(word
, u16
*, 0x02)
116 PCI_WRITE_VIA_DWORD_OP(byte
, u8
, 0x03, 0x000000ff)
117 PCI_WRITE_VIA_DWORD_OP(word
, u16
, 0x02, 0x0000ffff)
123 static struct pci_controller
* hose_head
= NULL
;
125 void pci_register_hose(struct pci_controller
* hose
)
127 struct pci_controller
**phose
= &hose_head
;
130 phose
= &(*phose
)->next
;
137 struct pci_controller
*pci_bus_to_hose (int bus
)
139 struct pci_controller
*hose
;
141 for (hose
= hose_head
; hose
; hose
= hose
->next
)
142 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
145 printf("pci_bus_to_hose() failed\n");
149 #ifndef CONFIG_IXP425
150 pci_dev_t
pci_find_devices(struct pci_device_id
*ids
, int index
)
152 struct pci_controller
* hose
;
156 int i
, bus
, found_multi
= 0;
158 for (hose
= hose_head
; hose
; hose
= hose
->next
)
160 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
161 for (bus
= hose
->last_busno
; bus
>= hose
->first_busno
; bus
--)
163 for (bus
= hose
->first_busno
; bus
<= hose
->last_busno
; bus
++)
165 for (bdf
= PCI_BDF(bus
,0,0);
166 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
167 bdf
< PCI_BDF(bus
,PCI_MAX_PCI_DEVICES
-1,PCI_MAX_PCI_FUNCTIONS
-1);
169 bdf
< PCI_BDF(bus
+1,0,0);
171 bdf
+= PCI_BDF(0,0,1))
173 if (!PCI_FUNC(bdf
)) {
174 pci_read_config_byte(bdf
,
178 found_multi
= header_type
& 0x80;
184 pci_read_config_word(bdf
,
187 pci_read_config_word(bdf
,
191 for (i
=0; ids
[i
].vendor
!= 0; i
++)
192 if (vendor
== ids
[i
].vendor
&&
193 device
== ids
[i
].device
)
205 #endif /* CONFIG_IXP425 */
207 pci_dev_t
pci_find_device(unsigned int vendor
, unsigned int device
, int index
)
209 static struct pci_device_id ids
[2] = {{}, {0, 0}};
211 ids
[0].vendor
= vendor
;
212 ids
[0].device
= device
;
214 return pci_find_devices(ids
, index
);
221 pci_addr_t
pci_hose_phys_to_bus (struct pci_controller
*hose
,
222 phys_addr_t phys_addr
,
225 struct pci_region
*res
;
230 printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
234 for (i
= 0; i
< hose
->region_count
; i
++) {
235 res
= &hose
->regions
[i
];
237 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
240 bus_addr
= phys_addr
- res
->phys_start
+ res
->bus_start
;
242 if (bus_addr
>= res
->bus_start
&&
243 bus_addr
< res
->bus_start
+ res
->size
) {
248 printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
254 phys_addr_t
pci_hose_bus_to_phys(struct pci_controller
* hose
,
258 struct pci_region
*res
;
262 printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
266 for (i
= 0; i
< hose
->region_count
; i
++) {
267 res
= &hose
->regions
[i
];
269 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
272 if (bus_addr
>= res
->bus_start
&&
273 bus_addr
< res
->bus_start
+ res
->size
) {
274 return bus_addr
- res
->bus_start
+ res
->phys_start
;
278 printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
288 int pci_hose_config_device(struct pci_controller
*hose
,
292 unsigned long command
)
294 unsigned int bar_response
, old_command
;
295 pci_addr_t bar_value
;
298 int bar
, found_mem64
;
300 debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
301 io
, (u64
)mem
, command
);
303 pci_hose_write_config_dword (hose
, dev
, PCI_COMMAND
, 0);
305 for (bar
= PCI_BASE_ADDRESS_0
; bar
< PCI_BASE_ADDRESS_5
; bar
+= 4) {
306 pci_hose_write_config_dword (hose
, dev
, bar
, 0xffffffff);
307 pci_hose_read_config_dword (hose
, dev
, bar
, &bar_response
);
314 /* Check the BAR type and set our address mask */
315 if (bar_response
& PCI_BASE_ADDRESS_SPACE
) {
316 bar_size
= ~(bar_response
& PCI_BASE_ADDRESS_IO_MASK
) + 1;
317 /* round up region base address to a multiple of size */
318 io
= ((io
- 1) | (bar_size
- 1)) + 1;
320 /* compute new region base address */
323 if ((bar_response
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
) ==
324 PCI_BASE_ADDRESS_MEM_TYPE_64
) {
325 u32 bar_response_upper
;
327 pci_hose_write_config_dword(hose
, dev
, bar
+4, 0xffffffff);
328 pci_hose_read_config_dword(hose
, dev
, bar
+4, &bar_response_upper
);
330 bar64
= ((u64
)bar_response_upper
<< 32) | bar_response
;
332 bar_size
= ~(bar64
& PCI_BASE_ADDRESS_MEM_MASK
) + 1;
335 bar_size
= (u32
)(~(bar_response
& PCI_BASE_ADDRESS_MEM_MASK
) + 1);
338 /* round up region base address to multiple of size */
339 mem
= ((mem
- 1) | (bar_size
- 1)) + 1;
341 /* compute new region base address */
342 mem
= mem
+ bar_size
;
345 /* Write it out and update our limit */
346 pci_hose_write_config_dword (hose
, dev
, bar
, (u32
)bar_value
);
350 #ifdef CONFIG_SYS_PCI_64BIT
351 pci_hose_write_config_dword(hose
, dev
, bar
, (u32
)(bar_value
>>32));
353 pci_hose_write_config_dword (hose
, dev
, bar
, 0x00000000);
358 /* Configure Cache Line Size Register */
359 pci_hose_write_config_byte (hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
361 /* Configure Latency Timer */
362 pci_hose_write_config_byte (hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
364 /* Disable interrupt line, if device says it wants to use interrupts */
365 pci_hose_read_config_byte (hose
, dev
, PCI_INTERRUPT_PIN
, &pin
);
367 pci_hose_write_config_byte (hose
, dev
, PCI_INTERRUPT_LINE
, 0xff);
370 pci_hose_read_config_dword (hose
, dev
, PCI_COMMAND
, &old_command
);
371 pci_hose_write_config_dword (hose
, dev
, PCI_COMMAND
,
372 (old_command
& 0xffff0000) | command
);
381 struct pci_config_table
*pci_find_config(struct pci_controller
*hose
,
382 unsigned short class,
389 struct pci_config_table
*table
;
391 for (table
= hose
->config_table
; table
&& table
->vendor
; table
++) {
392 if ((table
->vendor
== PCI_ANY_ID
|| table
->vendor
== vendor
) &&
393 (table
->device
== PCI_ANY_ID
|| table
->device
== device
) &&
394 (table
->class == PCI_ANY_ID
|| table
->class == class) &&
395 (table
->bus
== PCI_ANY_ID
|| table
->bus
== bus
) &&
396 (table
->dev
== PCI_ANY_ID
|| table
->dev
== dev
) &&
397 (table
->func
== PCI_ANY_ID
|| table
->func
== func
)) {
405 void pci_cfgfunc_config_device(struct pci_controller
*hose
,
407 struct pci_config_table
*entry
)
409 pci_hose_config_device(hose
, dev
, entry
->priv
[0], entry
->priv
[1], entry
->priv
[2]);
412 void pci_cfgfunc_do_nothing(struct pci_controller
*hose
,
413 pci_dev_t dev
, struct pci_config_table
*entry
)
421 /* HJF: Changed this to return int. I think this is required
422 * to get the correct result when scanning bridges
424 extern int pciauto_config_device(struct pci_controller
*hose
, pci_dev_t dev
);
425 extern void pciauto_config_init(struct pci_controller
*hose
);
427 int __pci_skip_dev(struct pci_controller
*hose
, pci_dev_t dev
)
430 * Check if pci device should be skipped in configuration
432 if (dev
== PCI_BDF(hose
->first_busno
, 0, 0)) {
433 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
435 * Only skip configuration if "pciconfighost" is not set
437 if (getenv("pciconfighost") == NULL
)
446 int pci_skip_dev(struct pci_controller
*hose
, pci_dev_t dev
)
447 __attribute__((weak
, alias("__pci_skip_dev")));
449 #ifdef CONFIG_PCI_SCAN_SHOW
450 int __pci_print_dev(struct pci_controller
*hose
, pci_dev_t dev
)
452 if (dev
== PCI_BDF(hose
->first_busno
, 0, 0))
457 int pci_print_dev(struct pci_controller
*hose
, pci_dev_t dev
)
458 __attribute__((weak
, alias("__pci_print_dev")));
459 #endif /* CONFIG_PCI_SCAN_SHOW */
461 int pci_hose_scan_bus(struct pci_controller
*hose
, int bus
)
463 unsigned int sub_bus
, found_multi
=0;
464 unsigned short vendor
, device
, class;
465 unsigned char header_type
;
466 struct pci_config_table
*cfg
;
471 for (dev
= PCI_BDF(bus
,0,0);
472 dev
< PCI_BDF(bus
,PCI_MAX_PCI_DEVICES
-1,PCI_MAX_PCI_FUNCTIONS
-1);
473 dev
+= PCI_BDF(0,0,1)) {
475 if (pci_skip_dev(hose
, dev
))
478 if (PCI_FUNC(dev
) && !found_multi
)
481 pci_hose_read_config_byte(hose
, dev
, PCI_HEADER_TYPE
, &header_type
);
483 pci_hose_read_config_word(hose
, dev
, PCI_VENDOR_ID
, &vendor
);
485 if (vendor
!= 0xffff && vendor
!= 0x0000) {
488 found_multi
= header_type
& 0x80;
490 debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
491 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
) );
493 pci_hose_read_config_word(hose
, dev
, PCI_DEVICE_ID
, &device
);
494 pci_hose_read_config_word(hose
, dev
, PCI_CLASS_DEVICE
, &class);
496 cfg
= pci_find_config(hose
, class, vendor
, device
,
497 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
));
499 cfg
->config_device(hose
, dev
, cfg
);
500 sub_bus
= max(sub_bus
, hose
->current_busno
);
501 #ifdef CONFIG_PCI_PNP
503 int n
= pciauto_config_device(hose
, dev
);
505 sub_bus
= max(sub_bus
, n
);
509 hose
->fixup_irq(hose
, dev
);
511 #ifdef CONFIG_PCI_SCAN_SHOW
512 if (pci_print_dev(hose
, dev
)) {
513 unsigned char int_line
;
515 pci_hose_read_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
,
517 printf(" %02x %02x %04x %04x %04x %02x\n",
518 PCI_BUS(dev
), PCI_DEV(dev
), vendor
, device
, class,
528 int pci_hose_scan(struct pci_controller
*hose
)
530 /* Start scan at current_busno.
531 * PCIe will start scan at first_busno+1.
533 /* For legacy support, ensure current>=first */
534 if (hose
->first_busno
> hose
->current_busno
)
535 hose
->current_busno
= hose
->first_busno
;
536 #ifdef CONFIG_PCI_PNP
537 pciauto_config_init(hose
);
539 return pci_hose_scan_bus(hose
, hose
->current_busno
);
544 #if defined(CONFIG_PCI_BOOTDELAY)
548 /* wait "pcidelay" ms (if defined)... */
549 s
= getenv ("pcidelay");
551 int val
= simple_strtoul (s
, NULL
, 10);
552 for (i
=0; i
<val
; i
++)
555 #endif /* CONFIG_PCI_BOOTDELAY */
557 /* now call board specific pci_init()... */