drivers/pci/pci_auto.c

   1 /*
   2  * arch/ppc/kernel/pci_auto.c
   3  *
   4  * PCI autoconfiguration library
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Copyright 2000 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <common.h>
  17
  18 #include <pci.h>
  19
  20 #undef DEBUG
  21 #ifdef DEBUG
  22 #define DEBUGF(x...) printf(x)
  23 #else
  24 #define DEBUGF(x...)
  25 #endif /* DEBUG */
  26
  27 #define PCIAUTO_IDE_MODE_MASK           0x05
  28
  29 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  30 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  31 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  32 #endif
  33
  34 /*
  35  *
  36  */
  37
  38 void pciauto_region_init(struct pci_region* res)
  39 {
  40         /*
  41          * Avoid allocating PCI resources from address 0 -- this is illegal
  42          * according to PCI 2.1 and moreover, this is known to cause Linux IDE
  43          * drivers to fail. Use a reasonable starting value of 0x1000 instead.
  44          */
  45         res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
  46 }
  47
  48 void pciauto_region_align(struct pci_region *res, pci_size_t size)
  49 {
  50         res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
  51 }
  52
  53 int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar)
  54 {
  55         pci_addr_t addr;
  56
  57         if (!res) {
  58                 DEBUGF("No resource");
  59                 goto error;
  60         }
  61
  62         addr = ((res->bus_lower - 1) | (size - 1)) + 1;
  63
  64         if (addr - res->bus_start + size > res->size) {
  65                 DEBUGF("No room in resource");
  66                 goto error;
  67         }
  68
  69         res->bus_lower = addr + size;
  70
  71         DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
  72
  73         *bar = addr;
  74         return 0;
  75
  76  error:
  77         *bar = (pci_addr_t)-1;
  78         return -1;
  79 }
  80
  81 /*
  82  *
  83  */
  84
  85 void pciauto_setup_device(struct pci_controller *hose,
  86                           pci_dev_t dev, int bars_num,
  87                           struct pci_region *mem,
  88                           struct pci_region *prefetch,
  89                           struct pci_region *io)
  90 {
  91         unsigned int bar_response;
  92         pci_addr_t bar_value;
  93         pci_size_t bar_size;
  94         unsigned int cmdstat = 0;
  95         struct pci_region *bar_res;
  96         int bar, bar_nr = 0;
  97         int found_mem64 = 0;
  98
  99         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
 100         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
 101
 102         for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
 103                 /* Tickle the BAR and get the response */
 104                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
 105                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
 106
 107                 /* If BAR is not implemented go to the next BAR */
 108                 if (!bar_response)
 109                         continue;
 110
 111                 found_mem64 = 0;
 112
 113                 /* Check the BAR type and set our address mask */
 114                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 115                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
 116                                    & 0xffff) + 1;
 117                         bar_res = io;
 118
 119                         DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
 120                 } else {
 121                         if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 122                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
 123                                 u32 bar_response_upper;
 124                                 u64 bar64;
 125                                 pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
 126                                 pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
 127
 128                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 129
 130                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 131                                 found_mem64 = 1;
 132                         } else {
 133                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 134                         }
 135                         if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
 136                                 bar_res = prefetch;
 137                         else
 138                                 bar_res = mem;
 139
 140                         DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
 141                 }
 142
 143                 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
 144                         /* Write it out and update our limit */
 145                         pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
 146
 147                         if (found_mem64) {
 148                                 bar += 4;
 149 #ifdef CONFIG_SYS_PCI_64BIT
 150                                 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 151 #else
 152                                 /*
 153                                  * If we are a 64-bit decoder then increment to the
 154                                  * upper 32 bits of the bar and force it to locate
 155                                  * in the lower 4GB of memory.
 156                                  */
 157                                 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 158 #endif
 159                         }
 160
 161                         cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 162                                 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 163                 }
 164
 165                 DEBUGF("\n");
 166
 167                 bar_nr++;
 168         }
 169
 170         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
 171         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 172                 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 173         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 174 }
 175
 176 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 177                                          pci_dev_t dev, int sub_bus)
 178 {
 179         struct pci_region *pci_mem = hose->pci_mem;
 180         struct pci_region *pci_prefetch = hose->pci_prefetch;
 181         struct pci_region *pci_io = hose->pci_io;
 182         unsigned int cmdstat;
 183
 184         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
 185
 186         /* Configure bus number registers */
 187         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
 188                                    PCI_BUS(dev) - hose->first_busno);
 189         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
 190                                    sub_bus - hose->first_busno);
 191         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 192
 193         if (pci_mem) {
 194                 /* Round memory allocator to 1MB boundary */
 195                 pciauto_region_align(pci_mem, 0x100000);
 196
 197                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 198                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
 199                                         (pci_mem->bus_lower & 0xfff00000) >> 16);
 200
 201                 cmdstat |= PCI_COMMAND_MEMORY;
 202         }
 203
 204         if (pci_prefetch) {
 205                 /* Round memory allocator to 1MB boundary */
 206                 pciauto_region_align(pci_prefetch, 0x100000);
 207
 208                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 209                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 210                                         (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 211
 212                 cmdstat |= PCI_COMMAND_MEMORY;
 213         } else {
 214                 /* We don't support prefetchable memory for now, so disable */
 215                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
 216                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 217         }
 218
 219         if (pci_io) {
 220                 /* Round I/O allocator to 4KB boundary */
 221                 pciauto_region_align(pci_io, 0x1000);
 222
 223                 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
 224                                         (pci_io->bus_lower & 0x0000f000) >> 8);
 225                 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
 226                                         (pci_io->bus_lower & 0xffff0000) >> 16);
 227
 228                 cmdstat |= PCI_COMMAND_IO;
 229         }
 230
 231         /* Enable memory and I/O accesses, enable bus master */
 232         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
 233 }
 234
 235 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 236                                           pci_dev_t dev, int sub_bus)
 237 {
 238         struct pci_region *pci_mem = hose->pci_mem;
 239         struct pci_region *pci_prefetch = hose->pci_prefetch;
 240         struct pci_region *pci_io = hose->pci_io;
 241
 242         /* Configure bus number registers */
 243         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
 244                                    sub_bus - hose->first_busno);
 245
 246         if (pci_mem) {
 247                 /* Round memory allocator to 1MB boundary */
 248                 pciauto_region_align(pci_mem, 0x100000);
 249
 250                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
 251                                         (pci_mem->bus_lower-1) >> 16);
 252         }
 253
 254         if (pci_prefetch) {
 255                 /* Round memory allocator to 1MB boundary */
 256                 pciauto_region_align(pci_prefetch, 0x100000);
 257
 258                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
 259                                         (pci_prefetch->bus_lower-1) >> 16);
 260         }
 261
 262         if (pci_io) {
 263                 /* Round I/O allocator to 4KB boundary */
 264                 pciauto_region_align(pci_io, 0x1000);
 265
 266                 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
 267                                         ((pci_io->bus_lower-1) & 0x0000f000) >> 8);
 268                 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
 269                                         ((pci_io->bus_lower-1) & 0xffff0000) >> 16);
 270         }
 271 }
 272
 273 /*
 274  *
 275  */
 276
 277 void pciauto_config_init(struct pci_controller *hose)
 278 {
 279         int i;
 280
 281         hose->pci_io = hose->pci_mem = NULL;
 282
 283         for (i=0; i<hose->region_count; i++) {
 284                 switch(hose->regions[i].flags) {
 285                 case PCI_REGION_IO:
 286                         if (!hose->pci_io ||
 287                             hose->pci_io->size < hose->regions[i].size)
 288                                 hose->pci_io = hose->regions + i;
 289                         break;
 290                 case PCI_REGION_MEM:
 291                         if (!hose->pci_mem ||
 292                             hose->pci_mem->size < hose->regions[i].size)
 293                                 hose->pci_mem = hose->regions + i;
 294                         break;
 295                 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
 296                         if (!hose->pci_prefetch ||
 297                             hose->pci_prefetch->size < hose->regions[i].size)
 298                                 hose->pci_prefetch = hose->regions + i;
 299                         break;
 300                 }
 301         }
 302
 303
 304         if (hose->pci_mem) {
 305                 pciauto_region_init(hose->pci_mem);
 306
 307                 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
 308                        "\t\tPhysical Memory [%llx-%llxx]\n",
 309                     (u64)hose->pci_mem->bus_start,
 310                     (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
 311                     (u64)hose->pci_mem->phys_start,
 312                     (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
 313         }
 314
 315         if (hose->pci_prefetch) {
 316                 pciauto_region_init(hose->pci_prefetch);
 317
 318                 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
 319                        "\t\tPhysical Memory [%llx-%llx]\n",
 320                     (u64)hose->pci_prefetch->bus_start,
 321                     (u64)(hose->pci_prefetch->bus_start +
 322                             hose->pci_prefetch->size - 1),
 323                     (u64)hose->pci_prefetch->phys_start,
 324                     (u64)(hose->pci_prefetch->phys_start +
 325                             hose->pci_prefetch->size - 1));
 326         }
 327
 328         if (hose->pci_io) {
 329                 pciauto_region_init(hose->pci_io);
 330
 331                 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
 332                        "\t\tPhysical Memory: [%llx-%llx]\n",
 333                     (u64)hose->pci_io->bus_start,
 334                     (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
 335                     (u64)hose->pci_io->phys_start,
 336                     (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
 337
 338         }
 339 }
 340
 341 /* HJF: Changed this to return int. I think this is required
 342  * to get the correct result when scanning bridges
 343  */
 344 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 345 {
 346         unsigned int sub_bus = PCI_BUS(dev);
 347         unsigned short class;
 348         unsigned char prg_iface;
 349         int n;
 350
 351         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 352
 353         switch(class) {
 354         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 355                 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
 356                 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
 357                                      hose->pci_prefetch, hose->pci_io);
 358                 break;
 359
 360         case PCI_CLASS_BRIDGE_PCI:
 361                 hose->current_busno++;
 362                 pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
 363
 364                 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
 365
 366                 /* Passing in current_busno allows for sibling P2P bridges */
 367                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 368                 /*
 369                  * need to figure out if this is a subordinate bridge on the bus
 370                  * to be able to properly set the pri/sec/sub bridge registers.
 371                  */
 372                 n = pci_hose_scan_bus(hose, hose->current_busno);
 373
 374                 /* figure out the deepest we've gone for this leg */
 375                 sub_bus = max(n, sub_bus);
 376                 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 377
 378                 sub_bus = hose->current_busno;
 379                 break;
 380
 381         case PCI_CLASS_STORAGE_IDE:
 382                 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
 383                 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 384                         DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
 385                         return sub_bus;
 386                 }
 387
 388                 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
 389                 break;
 390
 391         case PCI_CLASS_BRIDGE_CARDBUS:
 392                 /* just do a minimal setup of the bridge, let the OS take care of the rest */
 393                 pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
 394
 395                 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
 396
 397                 hose->current_busno++;
 398                 break;
 399
 400 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 401         case PCI_CLASS_BRIDGE_OTHER:
 402                 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
 403                        PCI_DEV(dev));
 404                 break;
 405 #endif
 406 #ifdef CONFIG_MPC834X
 407         case PCI_CLASS_BRIDGE_OTHER:
 408                 /*
 409                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 410                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 411                  * device claiming resources io/mem/irq.. we only allow for
 412                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 413                  */
 414                 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
 415                 pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
 416                 break;
 417 #endif
 418         default:
 419                 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
 420                 break;
 421         }
 422
 423         return sub_bus;
 424 }