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Merge git://git.denx.de/u-boot-fsl-qoriq
[people/ms/u-boot.git] / drivers / pci / pci_tegra.c
1 /*
2 * Copyright (c) 2010, CompuLab, Ltd.
3 * Author: Mike Rapoport <mike@compulab.co.il>
4 *
5 * Based on NVIDIA PCIe driver
6 * Copyright (c) 2008-2009, NVIDIA Corporation.
7 *
8 * Copyright (c) 2013-2014, NVIDIA Corporation.
9 *
10 * SPDX-License-Identifier: GPL-2.0
11 */
12
13 #define pr_fmt(fmt) "tegra-pcie: " fmt
14
15 #include <common.h>
16 #include <clk.h>
17 #include <dm.h>
18 #include <errno.h>
19 #include <malloc.h>
20 #include <pci.h>
21 #include <power-domain.h>
22 #include <reset.h>
23
24 #include <asm/io.h>
25 #include <asm/gpio.h>
26
27 #include <linux/ioport.h>
28 #include <linux/list.h>
29
30 #ifndef CONFIG_TEGRA186
31 #include <asm/arch/clock.h>
32 #include <asm/arch/powergate.h>
33 #include <asm/arch-tegra/xusb-padctl.h>
34 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
35 #endif
36
37 /*
38 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
39 * should not be present. These are needed because newer Tegra SoCs support
40 * only the standard clock/reset APIs, whereas older Tegra SoCs support only
41 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
42 * fixed to implement the standard APIs, and all drivers converted to solely
43 * use the new standard APIs, with no ifdefs.
44 */
45
46 DECLARE_GLOBAL_DATA_PTR;
47
48 #define AFI_AXI_BAR0_SZ 0x00
49 #define AFI_AXI_BAR1_SZ 0x04
50 #define AFI_AXI_BAR2_SZ 0x08
51 #define AFI_AXI_BAR3_SZ 0x0c
52 #define AFI_AXI_BAR4_SZ 0x10
53 #define AFI_AXI_BAR5_SZ 0x14
54
55 #define AFI_AXI_BAR0_START 0x18
56 #define AFI_AXI_BAR1_START 0x1c
57 #define AFI_AXI_BAR2_START 0x20
58 #define AFI_AXI_BAR3_START 0x24
59 #define AFI_AXI_BAR4_START 0x28
60 #define AFI_AXI_BAR5_START 0x2c
61
62 #define AFI_FPCI_BAR0 0x30
63 #define AFI_FPCI_BAR1 0x34
64 #define AFI_FPCI_BAR2 0x38
65 #define AFI_FPCI_BAR3 0x3c
66 #define AFI_FPCI_BAR4 0x40
67 #define AFI_FPCI_BAR5 0x44
68
69 #define AFI_CACHE_BAR0_SZ 0x48
70 #define AFI_CACHE_BAR0_ST 0x4c
71 #define AFI_CACHE_BAR1_SZ 0x50
72 #define AFI_CACHE_BAR1_ST 0x54
73
74 #define AFI_MSI_BAR_SZ 0x60
75 #define AFI_MSI_FPCI_BAR_ST 0x64
76 #define AFI_MSI_AXI_BAR_ST 0x68
77
78 #define AFI_CONFIGURATION 0xac
79 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
80
81 #define AFI_FPCI_ERROR_MASKS 0xb0
82
83 #define AFI_INTR_MASK 0xb4
84 #define AFI_INTR_MASK_INT_MASK (1 << 0)
85 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
86
87 #define AFI_SM_INTR_ENABLE 0xc4
88 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
89 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
90 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
91 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
92 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
93 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
94 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
95 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
96
97 #define AFI_AFI_INTR_ENABLE 0xc8
98 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
99 #define AFI_INTR_EN_INI_DECERR (1 << 1)
100 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
101 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
102 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
103 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
104 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
105 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
106 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
107
108 #define AFI_PCIE_CONFIG 0x0f8
109 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
110 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
111 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
112 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
113 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
114 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
115 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
116 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
117 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
118 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
119 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20)
120 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20)
121 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20)
122
123 #define AFI_FUSE 0x104
124 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
125
126 #define AFI_PEX0_CTRL 0x110
127 #define AFI_PEX1_CTRL 0x118
128 #define AFI_PEX2_CTRL 0x128
129 #define AFI_PEX2_CTRL_T186 0x19c
130 #define AFI_PEX_CTRL_RST (1 << 0)
131 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
132 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
133 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
134
135 #define AFI_PLLE_CONTROL 0x160
136 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
137 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
138
139 #define AFI_PEXBIAS_CTRL_0 0x168
140
141 #define PADS_CTL_SEL 0x0000009C
142
143 #define PADS_CTL 0x000000A0
144 #define PADS_CTL_IDDQ_1L (1 << 0)
145 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
146 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
147
148 #define PADS_PLL_CTL_TEGRA20 0x000000B8
149 #define PADS_PLL_CTL_TEGRA30 0x000000B4
150 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
151 #define PADS_PLL_CTL_LOCKDET (0x1 << 8)
152 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
153 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
154 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
155 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
156 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
157 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
158 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
159 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
160
161 #define PADS_REFCLK_CFG0 0x000000C8
162 #define PADS_REFCLK_CFG1 0x000000CC
163
164 /*
165 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
166 * entries, one entry per PCIe port. These field definitions and desired
167 * values aren't in the TRM, but do come from NVIDIA.
168 */
169 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
170 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
171 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
172 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
173
174 #define RP_VEND_XP 0x00000F00
175 #define RP_VEND_XP_DL_UP (1 << 30)
176
177 #define RP_VEND_CTL2 0x00000FA8
178 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
179
180 #define RP_PRIV_MISC 0x00000FE0
181 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
182 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
183
184 #define RP_LINK_CONTROL_STATUS 0x00000090
185 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
186 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
187
188 enum tegra_pci_id {
189 TEGRA20_PCIE,
190 TEGRA30_PCIE,
191 TEGRA124_PCIE,
192 TEGRA210_PCIE,
193 TEGRA186_PCIE,
194 };
195
196 struct tegra_pcie_port {
197 struct tegra_pcie *pcie;
198
199 struct fdt_resource regs;
200 unsigned int num_lanes;
201 unsigned int index;
202
203 struct list_head list;
204 };
205
206 struct tegra_pcie_soc {
207 unsigned int num_ports;
208 unsigned long pads_pll_ctl;
209 unsigned long tx_ref_sel;
210 unsigned long afi_pex2_ctrl;
211 u32 pads_refclk_cfg0;
212 u32 pads_refclk_cfg1;
213 bool has_pex_clkreq_en;
214 bool has_pex_bias_ctrl;
215 bool has_cml_clk;
216 bool has_gen2;
217 bool force_pca_enable;
218 };
219
220 struct tegra_pcie {
221 struct pci_controller hose;
222
223 struct resource pads;
224 struct resource afi;
225 struct resource cs;
226
227 struct list_head ports;
228 unsigned long xbar;
229
230 const struct tegra_pcie_soc *soc;
231
232 #ifdef CONFIG_TEGRA186
233 struct clk clk_afi;
234 struct clk clk_pex;
235 struct reset_ctl reset_afi;
236 struct reset_ctl reset_pex;
237 struct reset_ctl reset_pcie_x;
238 struct power_domain pwrdom;
239 #else
240 struct tegra_xusb_phy *phy;
241 #endif
242 };
243
244 static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
245 unsigned long offset)
246 {
247 writel(value, pcie->afi.start + offset);
248 }
249
250 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
251 {
252 return readl(pcie->afi.start + offset);
253 }
254
255 static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
256 unsigned long offset)
257 {
258 writel(value, pcie->pads.start + offset);
259 }
260
261 #ifndef CONFIG_TEGRA186
262 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
263 {
264 return readl(pcie->pads.start + offset);
265 }
266 #endif
267
268 static unsigned long rp_readl(struct tegra_pcie_port *port,
269 unsigned long offset)
270 {
271 return readl(port->regs.start + offset);
272 }
273
274 static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
275 unsigned long offset)
276 {
277 writel(value, port->regs.start + offset);
278 }
279
280 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where)
281 {
282 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) |
283 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) |
284 (where & 0xfc);
285 }
286
287 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
288 int where, unsigned long *address)
289 {
290 unsigned int bus = PCI_BUS(bdf);
291
292 if (bus == 0) {
293 unsigned int dev = PCI_DEV(bdf);
294 struct tegra_pcie_port *port;
295
296 list_for_each_entry(port, &pcie->ports, list) {
297 if (port->index + 1 == dev) {
298 *address = port->regs.start + (where & ~3);
299 return 0;
300 }
301 }
302 return -EFAULT;
303 } else {
304 #ifdef CONFIG_TEGRA20
305 unsigned int dev = PCI_DEV(bdf);
306 if (dev != 0)
307 return -EFAULT;
308 #endif
309
310 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
311 return 0;
312 }
313 }
314
315 static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf,
316 uint offset, ulong *valuep,
317 enum pci_size_t size)
318 {
319 struct tegra_pcie *pcie = dev_get_priv(bus);
320 unsigned long address, value;
321 int err;
322
323 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
324 if (err < 0) {
325 value = 0xffffffff;
326 goto done;
327 }
328
329 value = readl(address);
330
331 #ifdef CONFIG_TEGRA20
332 /* fixup root port class */
333 if (PCI_BUS(bdf) == 0) {
334 if ((offset & ~3) == PCI_CLASS_REVISION) {
335 value &= ~0x00ff0000;
336 value |= PCI_CLASS_BRIDGE_PCI << 16;
337 }
338 }
339 #endif
340
341 done:
342 *valuep = pci_conv_32_to_size(value, offset, size);
343
344 return 0;
345 }
346
347 static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf,
348 uint offset, ulong value,
349 enum pci_size_t size)
350 {
351 struct tegra_pcie *pcie = dev_get_priv(bus);
352 unsigned long address;
353 ulong old;
354 int err;
355
356 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
357 if (err < 0)
358 return 0;
359
360 old = readl(address);
361 value = pci_conv_size_to_32(old, value, offset, size);
362 writel(value, address);
363
364 return 0;
365 }
366
367 static int tegra_pcie_port_parse_dt(ofnode node, struct tegra_pcie_port *port)
368 {
369 const u32 *addr;
370 int len;
371
372 addr = ofnode_get_property(node, "assigned-addresses", &len);
373 if (!addr) {
374 error("property \"assigned-addresses\" not found");
375 return -FDT_ERR_NOTFOUND;
376 }
377
378 port->regs.start = fdt32_to_cpu(addr[2]);
379 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
380
381 return 0;
382 }
383
384 static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes,
385 enum tegra_pci_id id, unsigned long *xbar)
386 {
387 switch (id) {
388 case TEGRA20_PCIE:
389 switch (lanes) {
390 case 0x00000004:
391 debug("single-mode configuration\n");
392 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
393 return 0;
394
395 case 0x00000202:
396 debug("dual-mode configuration\n");
397 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
398 return 0;
399 }
400 break;
401 case TEGRA30_PCIE:
402 switch (lanes) {
403 case 0x00000204:
404 debug("4x1, 2x1 configuration\n");
405 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
406 return 0;
407
408 case 0x00020202:
409 debug("2x3 configuration\n");
410 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
411 return 0;
412
413 case 0x00010104:
414 debug("4x1, 1x2 configuration\n");
415 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
416 return 0;
417 }
418 break;
419 case TEGRA124_PCIE:
420 case TEGRA210_PCIE:
421 switch (lanes) {
422 case 0x0000104:
423 debug("4x1, 1x1 configuration\n");
424 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
425 return 0;
426
427 case 0x0000102:
428 debug("2x1, 1x1 configuration\n");
429 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
430 return 0;
431 }
432 break;
433 case TEGRA186_PCIE:
434 switch (lanes) {
435 case 0x0010004:
436 debug("x4 x1 configuration\n");
437 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401;
438 return 0;
439
440 case 0x0010102:
441 debug("x2 x1 x1 configuration\n");
442 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211;
443 return 0;
444
445 case 0x0010101:
446 debug("x1 x1 x1 configuration\n");
447 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111;
448 return 0;
449 }
450 break;
451 default:
452 break;
453 }
454
455 return -FDT_ERR_NOTFOUND;
456 }
457
458 static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes)
459 {
460 struct fdt_pci_addr addr;
461 int err;
462
463 err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1);
464 if (err < 0) {
465 error("failed to parse \"nvidia,num-lanes\" property");
466 return err;
467 }
468
469 *lanes = err;
470
471 err = ofnode_read_pci_addr(node, 0, "reg", &addr);
472 if (err < 0) {
473 error("failed to parse \"reg\" property");
474 return err;
475 }
476
477 *index = PCI_DEV(addr.phys_hi) - 1;
478
479 return 0;
480 }
481
482 int __weak tegra_pcie_board_init(void)
483 {
484 return 0;
485 }
486
487 static int tegra_pcie_parse_dt(struct udevice *dev, enum tegra_pci_id id,
488 struct tegra_pcie *pcie)
489 {
490 ofnode subnode;
491 u32 lanes = 0;
492 int err;
493
494 err = dev_read_resource(dev, 0, &pcie->pads);
495 if (err < 0) {
496 error("resource \"pads\" not found");
497 return err;
498 }
499
500 err = dev_read_resource(dev, 1, &pcie->afi);
501 if (err < 0) {
502 error("resource \"afi\" not found");
503 return err;
504 }
505
506 err = dev_read_resource(dev, 2, &pcie->cs);
507 if (err < 0) {
508 error("resource \"cs\" not found");
509 return err;
510 }
511
512 err = tegra_pcie_board_init();
513 if (err < 0) {
514 error("tegra_pcie_board_init() failed: err=%d", err);
515 return err;
516 }
517
518 #ifndef CONFIG_TEGRA186
519 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
520 if (pcie->phy) {
521 err = tegra_xusb_phy_prepare(pcie->phy);
522 if (err < 0) {
523 error("failed to prepare PHY: %d", err);
524 return err;
525 }
526 }
527 #endif
528
529 dev_for_each_subnode(subnode, dev) {
530 unsigned int index = 0, num_lanes = 0;
531 struct tegra_pcie_port *port;
532
533 err = tegra_pcie_parse_port_info(subnode, &index, &num_lanes);
534 if (err < 0) {
535 error("failed to obtain root port info");
536 continue;
537 }
538
539 lanes |= num_lanes << (index << 3);
540
541 if (!ofnode_is_available(subnode))
542 continue;
543
544 port = malloc(sizeof(*port));
545 if (!port)
546 continue;
547
548 memset(port, 0, sizeof(*port));
549 port->num_lanes = num_lanes;
550 port->index = index;
551
552 err = tegra_pcie_port_parse_dt(subnode, port);
553 if (err < 0) {
554 free(port);
555 continue;
556 }
557
558 list_add_tail(&port->list, &pcie->ports);
559 port->pcie = pcie;
560 }
561
562 err = tegra_pcie_get_xbar_config(dev_ofnode(dev), lanes, id,
563 &pcie->xbar);
564 if (err < 0) {
565 error("invalid lane configuration");
566 return err;
567 }
568
569 return 0;
570 }
571
572 #ifdef CONFIG_TEGRA186
573 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
574 {
575 int ret;
576
577 ret = power_domain_on(&pcie->pwrdom);
578 if (ret) {
579 error("power_domain_on() failed: %d\n", ret);
580 return ret;
581 }
582
583 ret = clk_enable(&pcie->clk_afi);
584 if (ret) {
585 error("clk_enable(afi) failed: %d\n", ret);
586 return ret;
587 }
588
589 ret = clk_enable(&pcie->clk_pex);
590 if (ret) {
591 error("clk_enable(pex) failed: %d\n", ret);
592 return ret;
593 }
594
595 ret = reset_deassert(&pcie->reset_afi);
596 if (ret) {
597 error("reset_deassert(afi) failed: %d\n", ret);
598 return ret;
599 }
600
601 ret = reset_deassert(&pcie->reset_pex);
602 if (ret) {
603 error("reset_deassert(pex) failed: %d\n", ret);
604 return ret;
605 }
606
607 return 0;
608 }
609 #else
610 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
611 {
612 const struct tegra_pcie_soc *soc = pcie->soc;
613 unsigned long value;
614 int err;
615
616 /* reset PCIEXCLK logic, AFI controller and PCIe controller */
617 reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
618 reset_set_enable(PERIPH_ID_AFI, 1);
619 reset_set_enable(PERIPH_ID_PCIE, 1);
620
621 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
622 if (err < 0) {
623 error("failed to power off PCIe partition: %d", err);
624 return err;
625 }
626
627 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
628 PERIPH_ID_PCIE);
629 if (err < 0) {
630 error("failed to power up PCIe partition: %d", err);
631 return err;
632 }
633
634 /* take AFI controller out of reset */
635 reset_set_enable(PERIPH_ID_AFI, 0);
636
637 /* enable AFI clock */
638 clock_enable(PERIPH_ID_AFI);
639
640 if (soc->has_cml_clk) {
641 /* enable CML clock */
642 value = readl(NV_PA_CLK_RST_BASE + 0x48c);
643 value |= (1 << 0);
644 value &= ~(1 << 1);
645 writel(value, NV_PA_CLK_RST_BASE + 0x48c);
646 }
647
648 err = tegra_plle_enable();
649 if (err < 0) {
650 error("failed to enable PLLE: %d\n", err);
651 return err;
652 }
653
654 return 0;
655 }
656
657 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
658 {
659 const struct tegra_pcie_soc *soc = pcie->soc;
660 unsigned long start = get_timer(0);
661 u32 value;
662
663 while (get_timer(start) < timeout) {
664 value = pads_readl(pcie, soc->pads_pll_ctl);
665 if (value & PADS_PLL_CTL_LOCKDET)
666 return 0;
667 }
668
669 return -ETIMEDOUT;
670 }
671
672 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
673 {
674 const struct tegra_pcie_soc *soc = pcie->soc;
675 u32 value;
676 int err;
677
678 /* initialize internal PHY, enable up to 16 PCIe lanes */
679 pads_writel(pcie, 0, PADS_CTL_SEL);
680
681 /* override IDDQ to 1 on all 4 lanes */
682 value = pads_readl(pcie, PADS_CTL);
683 value |= PADS_CTL_IDDQ_1L;
684 pads_writel(pcie, value, PADS_CTL);
685
686 /*
687 * Set up PHY PLL inputs select PLLE output as refclock, set TX
688 * ref sel to div10 (not div5).
689 */
690 value = pads_readl(pcie, soc->pads_pll_ctl);
691 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
692 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
693 pads_writel(pcie, value, soc->pads_pll_ctl);
694
695 /* reset PLL */
696 value = pads_readl(pcie, soc->pads_pll_ctl);
697 value &= ~PADS_PLL_CTL_RST_B4SM;
698 pads_writel(pcie, value, soc->pads_pll_ctl);
699
700 udelay(20);
701
702 /* take PLL out of reset */
703 value = pads_readl(pcie, soc->pads_pll_ctl);
704 value |= PADS_PLL_CTL_RST_B4SM;
705 pads_writel(pcie, value, soc->pads_pll_ctl);
706
707 /* wait for the PLL to lock */
708 err = tegra_pcie_pll_wait(pcie, 500);
709 if (err < 0) {
710 error("PLL failed to lock: %d", err);
711 return err;
712 }
713
714 /* turn off IDDQ override */
715 value = pads_readl(pcie, PADS_CTL);
716 value &= ~PADS_CTL_IDDQ_1L;
717 pads_writel(pcie, value, PADS_CTL);
718
719 /* enable TX/RX data */
720 value = pads_readl(pcie, PADS_CTL);
721 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
722 pads_writel(pcie, value, PADS_CTL);
723
724 return 0;
725 }
726 #endif
727
728 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
729 {
730 const struct tegra_pcie_soc *soc = pcie->soc;
731 struct tegra_pcie_port *port;
732 u32 value;
733 int err;
734
735 #ifdef CONFIG_TEGRA186
736 {
737 #else
738 if (pcie->phy) {
739 #endif
740 value = afi_readl(pcie, AFI_PLLE_CONTROL);
741 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
742 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
743 afi_writel(pcie, value, AFI_PLLE_CONTROL);
744 }
745
746 if (soc->has_pex_bias_ctrl)
747 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
748
749 value = afi_readl(pcie, AFI_PCIE_CONFIG);
750 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
751 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
752
753 list_for_each_entry(port, &pcie->ports, list)
754 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
755
756 afi_writel(pcie, value, AFI_PCIE_CONFIG);
757
758 value = afi_readl(pcie, AFI_FUSE);
759
760 if (soc->has_gen2)
761 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
762 else
763 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
764
765 afi_writel(pcie, value, AFI_FUSE);
766
767 #ifndef CONFIG_TEGRA186
768 if (pcie->phy)
769 err = tegra_xusb_phy_enable(pcie->phy);
770 else
771 err = tegra_pcie_phy_enable(pcie);
772
773 if (err < 0) {
774 error("failed to power on PHY: %d\n", err);
775 return err;
776 }
777 #endif
778
779 /* take the PCIEXCLK logic out of reset */
780 #ifdef CONFIG_TEGRA186
781 err = reset_deassert(&pcie->reset_pcie_x);
782 if (err) {
783 error("reset_deassert(pcie_x) failed: %d\n", err);
784 return err;
785 }
786 #else
787 reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
788 #endif
789
790 /* finally enable PCIe */
791 value = afi_readl(pcie, AFI_CONFIGURATION);
792 value |= AFI_CONFIGURATION_EN_FPCI;
793 afi_writel(pcie, value, AFI_CONFIGURATION);
794
795 /* disable all interrupts */
796 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
797 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
798 afi_writel(pcie, 0, AFI_INTR_MASK);
799 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
800
801 return 0;
802 }
803
804 static int tegra_pcie_setup_translations(struct udevice *bus)
805 {
806 struct tegra_pcie *pcie = dev_get_priv(bus);
807 unsigned long fpci, axi, size;
808 struct pci_region *io, *mem, *pref;
809 int count;
810
811 /* BAR 0: type 1 extended configuration space */
812 fpci = 0xfe100000;
813 size = resource_size(&pcie->cs);
814 axi = pcie->cs.start;
815
816 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
817 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
818 afi_writel(pcie, fpci, AFI_FPCI_BAR0);
819
820 count = pci_get_regions(bus, &io, &mem, &pref);
821 if (count != 3)
822 return -EINVAL;
823
824 /* BAR 1: downstream I/O */
825 fpci = 0xfdfc0000;
826 size = io->size;
827 axi = io->phys_start;
828
829 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
830 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
831 afi_writel(pcie, fpci, AFI_FPCI_BAR1);
832
833 /* BAR 2: prefetchable memory */
834 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
835 size = pref->size;
836 axi = pref->phys_start;
837
838 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
839 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
840 afi_writel(pcie, fpci, AFI_FPCI_BAR2);
841
842 /* BAR 3: non-prefetchable memory */
843 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
844 size = mem->size;
845 axi = mem->phys_start;
846
847 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
848 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
849 afi_writel(pcie, fpci, AFI_FPCI_BAR3);
850
851 /* NULL out the remaining BARs as they are not used */
852 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
853 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
854 afi_writel(pcie, 0, AFI_FPCI_BAR4);
855
856 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
857 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
858 afi_writel(pcie, 0, AFI_FPCI_BAR5);
859
860 /* map all upstream transactions as uncached */
861 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
862 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
863 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
864 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
865
866 /* MSI translations are setup only when needed */
867 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
868 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
869 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
870 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
871
872 return 0;
873 }
874
875 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
876 {
877 unsigned long ret = 0;
878
879 switch (port->index) {
880 case 0:
881 ret = AFI_PEX0_CTRL;
882 break;
883
884 case 1:
885 ret = AFI_PEX1_CTRL;
886 break;
887
888 case 2:
889 ret = port->pcie->soc->afi_pex2_ctrl;
890 break;
891 }
892
893 return ret;
894 }
895
896 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
897 {
898 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
899 unsigned long value;
900
901 /* pulse reset signel */
902 value = afi_readl(port->pcie, ctrl);
903 value &= ~AFI_PEX_CTRL_RST;
904 afi_writel(port->pcie, value, ctrl);
905
906 udelay(2000);
907
908 value = afi_readl(port->pcie, ctrl);
909 value |= AFI_PEX_CTRL_RST;
910 afi_writel(port->pcie, value, ctrl);
911 }
912
913 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
914 {
915 struct tegra_pcie *pcie = port->pcie;
916 const struct tegra_pcie_soc *soc = pcie->soc;
917 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
918 unsigned long value;
919
920 /* enable reference clock */
921 value = afi_readl(pcie, ctrl);
922 value |= AFI_PEX_CTRL_REFCLK_EN;
923
924 if (pcie->soc->has_pex_clkreq_en)
925 value |= AFI_PEX_CTRL_CLKREQ_EN;
926
927 value |= AFI_PEX_CTRL_OVERRIDE_EN;
928
929 afi_writel(pcie, value, ctrl);
930
931 tegra_pcie_port_reset(port);
932
933 if (soc->force_pca_enable) {
934 value = rp_readl(port, RP_VEND_CTL2);
935 value |= RP_VEND_CTL2_PCA_ENABLE;
936 rp_writel(port, value, RP_VEND_CTL2);
937 }
938
939 /* configure the reference clock driver */
940 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
941 if (soc->num_ports > 2)
942 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
943 }
944
945 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
946 {
947 unsigned int retries = 3;
948 unsigned long value;
949
950 value = rp_readl(port, RP_PRIV_MISC);
951 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
952 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
953 rp_writel(port, value, RP_PRIV_MISC);
954
955 do {
956 unsigned int timeout = 200;
957
958 do {
959 value = rp_readl(port, RP_VEND_XP);
960 if (value & RP_VEND_XP_DL_UP)
961 break;
962
963 udelay(2000);
964 } while (--timeout);
965
966 if (!timeout) {
967 debug("link %u down, retrying\n", port->index);
968 goto retry;
969 }
970
971 timeout = 200;
972
973 do {
974 value = rp_readl(port, RP_LINK_CONTROL_STATUS);
975 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
976 return true;
977
978 udelay(2000);
979 } while (--timeout);
980
981 retry:
982 tegra_pcie_port_reset(port);
983 } while (--retries);
984
985 return false;
986 }
987
988 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
989 {
990 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
991 unsigned long value;
992
993 /* assert port reset */
994 value = afi_readl(port->pcie, ctrl);
995 value &= ~AFI_PEX_CTRL_RST;
996 afi_writel(port->pcie, value, ctrl);
997
998 /* disable reference clock */
999 value = afi_readl(port->pcie, ctrl);
1000 value &= ~AFI_PEX_CTRL_REFCLK_EN;
1001 afi_writel(port->pcie, value, ctrl);
1002 }
1003
1004 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
1005 {
1006 list_del(&port->list);
1007 free(port);
1008 }
1009
1010 static int tegra_pcie_enable(struct tegra_pcie *pcie)
1011 {
1012 struct tegra_pcie_port *port, *tmp;
1013
1014 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1015 debug("probing port %u, using %u lanes\n", port->index,
1016 port->num_lanes);
1017
1018 tegra_pcie_port_enable(port);
1019
1020 if (tegra_pcie_port_check_link(port))
1021 continue;
1022
1023 debug("link %u down, ignoring\n", port->index);
1024
1025 tegra_pcie_port_disable(port);
1026 tegra_pcie_port_free(port);
1027 }
1028
1029 return 0;
1030 }
1031
1032 static const struct tegra_pcie_soc pci_tegra_soc[] = {
1033 [TEGRA20_PCIE] = {
1034 .num_ports = 2,
1035 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
1036 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
1037 .pads_refclk_cfg0 = 0xfa5cfa5c,
1038 .has_pex_clkreq_en = false,
1039 .has_pex_bias_ctrl = false,
1040 .has_cml_clk = false,
1041 .has_gen2 = false,
1042 },
1043 [TEGRA30_PCIE] = {
1044 .num_ports = 3,
1045 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1046 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1047 .afi_pex2_ctrl = AFI_PEX2_CTRL,
1048 .pads_refclk_cfg0 = 0xfa5cfa5c,
1049 .pads_refclk_cfg1 = 0xfa5cfa5c,
1050 .has_pex_clkreq_en = true,
1051 .has_pex_bias_ctrl = true,
1052 .has_cml_clk = true,
1053 .has_gen2 = false,
1054 },
1055 [TEGRA124_PCIE] = {
1056 .num_ports = 2,
1057 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1058 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1059 .pads_refclk_cfg0 = 0x44ac44ac,
1060 .has_pex_clkreq_en = true,
1061 .has_pex_bias_ctrl = true,
1062 .has_cml_clk = true,
1063 .has_gen2 = true,
1064 },
1065 [TEGRA210_PCIE] = {
1066 .num_ports = 2,
1067 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1068 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1069 .pads_refclk_cfg0 = 0x90b890b8,
1070 .has_pex_clkreq_en = true,
1071 .has_pex_bias_ctrl = true,
1072 .has_cml_clk = true,
1073 .has_gen2 = true,
1074 .force_pca_enable = true,
1075 },
1076 [TEGRA186_PCIE] = {
1077 .num_ports = 3,
1078 .afi_pex2_ctrl = AFI_PEX2_CTRL_T186,
1079 .pads_refclk_cfg0 = 0x80b880b8,
1080 .pads_refclk_cfg1 = 0x000480b8,
1081 .has_pex_clkreq_en = true,
1082 .has_pex_bias_ctrl = true,
1083 .has_gen2 = true,
1084 },
1085 };
1086
1087 static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
1088 {
1089 struct tegra_pcie *pcie = dev_get_priv(dev);
1090 enum tegra_pci_id id;
1091
1092 id = dev_get_driver_data(dev);
1093 pcie->soc = &pci_tegra_soc[id];
1094
1095 INIT_LIST_HEAD(&pcie->ports);
1096
1097 if (tegra_pcie_parse_dt(dev, id, pcie))
1098 return -EINVAL;
1099
1100 return 0;
1101 }
1102
1103 static int pci_tegra_probe(struct udevice *dev)
1104 {
1105 struct tegra_pcie *pcie = dev_get_priv(dev);
1106 int err;
1107
1108 #ifdef CONFIG_TEGRA186
1109 err = clk_get_by_name(dev, "afi", &pcie->clk_afi);
1110 if (err) {
1111 debug("clk_get_by_name(afi) failed: %d\n", err);
1112 return err;
1113 }
1114
1115 err = clk_get_by_name(dev, "pex", &pcie->clk_pex);
1116 if (err) {
1117 debug("clk_get_by_name(pex) failed: %d\n", err);
1118 return err;
1119 }
1120
1121 err = reset_get_by_name(dev, "afi", &pcie->reset_afi);
1122 if (err) {
1123 debug("reset_get_by_name(afi) failed: %d\n", err);
1124 return err;
1125 }
1126
1127 err = reset_get_by_name(dev, "pex", &pcie->reset_pex);
1128 if (err) {
1129 debug("reset_get_by_name(pex) failed: %d\n", err);
1130 return err;
1131 }
1132
1133 err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x);
1134 if (err) {
1135 debug("reset_get_by_name(pcie_x) failed: %d\n", err);
1136 return err;
1137 }
1138
1139 err = power_domain_get(dev, &pcie->pwrdom);
1140 if (err) {
1141 debug("power_domain_get() failed: %d\n", err);
1142 return err;
1143 }
1144 #endif
1145
1146 err = tegra_pcie_power_on(pcie);
1147 if (err < 0) {
1148 error("failed to power on");
1149 return err;
1150 }
1151
1152 err = tegra_pcie_enable_controller(pcie);
1153 if (err < 0) {
1154 error("failed to enable controller");
1155 return err;
1156 }
1157
1158 err = tegra_pcie_setup_translations(dev);
1159 if (err < 0) {
1160 error("failed to decode ranges");
1161 return err;
1162 }
1163
1164 err = tegra_pcie_enable(pcie);
1165 if (err < 0) {
1166 error("failed to enable PCIe");
1167 return err;
1168 }
1169
1170 return 0;
1171 }
1172
1173 static const struct dm_pci_ops pci_tegra_ops = {
1174 .read_config = pci_tegra_read_config,
1175 .write_config = pci_tegra_write_config,
1176 };
1177
1178 static const struct udevice_id pci_tegra_ids[] = {
1179 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
1180 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
1181 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
1182 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
1183 { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE },
1184 { }
1185 };
1186
1187 U_BOOT_DRIVER(pci_tegra) = {
1188 .name = "pci_tegra",
1189 .id = UCLASS_PCI,
1190 .of_match = pci_tegra_ids,
1191 .ops = &pci_tegra_ops,
1192 .ofdata_to_platdata = pci_tegra_ofdata_to_platdata,
1193 .probe = pci_tegra_probe,
1194 .priv_auto_alloc_size = sizeof(struct tegra_pcie),
1195 };
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