drivers/pci/pcie_layerscape.c

   1 /*
   2  * Copyright 2017 NXP
   3  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   4  * Layerscape PCIe driver
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/arch/fsl_serdes.h>
  11 #include <pci.h>
  12 #include <asm/io.h>
  13 #include <errno.h>
  14 #include <malloc.h>
  15 #include <dm.h>
  16 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  17         defined(CONFIG_ARM)
  18 #include <asm/arch/clock.h>
  19 #endif
  20 #include "pcie_layerscape.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 LIST_HEAD(ls_pcie_list);
  25
  26 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
  27 {
  28         return in_le32(pcie->dbi + offset);
  29 }
  30
  31 static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
  32                        unsigned int offset)
  33 {
  34         out_le32(pcie->dbi + offset, value);
  35 }
  36
  37 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
  38 {
  39         if (pcie->big_endian)
  40                 return in_be32(pcie->ctrl + offset);
  41         else
  42                 return in_le32(pcie->ctrl + offset);
  43 }
  44
  45 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
  46                         unsigned int offset)
  47 {
  48         if (pcie->big_endian)
  49                 out_be32(pcie->ctrl + offset, value);
  50         else
  51                 out_le32(pcie->ctrl + offset, value);
  52 }
  53
  54 static int ls_pcie_ltssm(struct ls_pcie *pcie)
  55 {
  56         u32 state;
  57         uint svr;
  58
  59         svr = get_svr();
  60         if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
  61                 state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
  62                 state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
  63         } else {
  64                 state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK;
  65         }
  66
  67         return state;
  68 }
  69
  70 static int ls_pcie_link_up(struct ls_pcie *pcie)
  71 {
  72         int ltssm;
  73
  74         ltssm = ls_pcie_ltssm(pcie);
  75         if (ltssm < LTSSM_PCIE_L0)
  76                 return 0;
  77
  78         return 1;
  79 }
  80
  81 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
  82 {
  83         dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
  84                    PCIE_ATU_VIEWPORT);
  85         dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
  86 }
  87
  88 static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
  89 {
  90         dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
  91                    PCIE_ATU_VIEWPORT);
  92         dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
  93 }
  94
  95 static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
  96                                       u64 phys, u64 bus_addr, pci_size_t size)
  97 {
  98         dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
  99         dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
 100         dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
 101         dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
 102         dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
 103         dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
 104         dbi_writel(pcie, type, PCIE_ATU_CR1);
 105         dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 106 }
 107
 108 /* Use bar match mode and MEM type as default */
 109 static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
 110                                      int bar, u64 phys)
 111 {
 112         dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
 113         dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
 114         dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
 115         dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
 116         dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
 117                    PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
 118 }
 119
 120 static void ls_pcie_dump_atu(struct ls_pcie *pcie)
 121 {
 122         int i;
 123
 124         for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
 125                 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
 126                            PCIE_ATU_VIEWPORT);
 127                 debug("iATU%d:\n", i);
 128                 debug("\tLOWER PHYS 0x%08x\n",
 129                       dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
 130                 debug("\tUPPER PHYS 0x%08x\n",
 131                       dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
 132                 debug("\tLOWER BUS  0x%08x\n",
 133                       dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
 134                 debug("\tUPPER BUS  0x%08x\n",
 135                       dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
 136                 debug("\tLIMIT      0x%08x\n",
 137                       readl(pcie->dbi + PCIE_ATU_LIMIT));
 138                 debug("\tCR1        0x%08x\n",
 139                       dbi_readl(pcie, PCIE_ATU_CR1));
 140                 debug("\tCR2        0x%08x\n",
 141                       dbi_readl(pcie, PCIE_ATU_CR2));
 142         }
 143 }
 144
 145 static void ls_pcie_setup_atu(struct ls_pcie *pcie)
 146 {
 147         struct pci_region *io, *mem, *pref;
 148         unsigned long long offset = 0;
 149         int idx = 0;
 150         uint svr;
 151
 152         svr = get_svr();
 153         if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
 154                 offset = LS1021_PCIE_SPACE_OFFSET +
 155                          LS1021_PCIE_SPACE_SIZE * pcie->idx;
 156         }
 157
 158         /* ATU 0 : OUTBOUND : CFG0 */
 159         ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
 160                                  PCIE_ATU_TYPE_CFG0,
 161                                  pcie->cfg_res.start + offset,
 162                                  0,
 163                                  fdt_resource_size(&pcie->cfg_res) / 2);
 164         /* ATU 1 : OUTBOUND : CFG1 */
 165         ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
 166                                  PCIE_ATU_TYPE_CFG1,
 167                                  pcie->cfg_res.start + offset +
 168                                  fdt_resource_size(&pcie->cfg_res) / 2,
 169                                  0,
 170                                  fdt_resource_size(&pcie->cfg_res) / 2);
 171
 172         pci_get_regions(pcie->bus, &io, &mem, &pref);
 173         idx = PCIE_ATU_REGION_INDEX1 + 1;
 174
 175         /* Fix the pcie memory map for LS2088A series SoCs */
 176         svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 177         if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 178             svr == SVR_LS2048A || svr == SVR_LS2044A ||
 179             svr == SVR_LS2081A || svr == SVR_LS2041A) {
 180                 if (io)
 181                         io->phys_start = (io->phys_start &
 182                                          (PCIE_PHYS_SIZE - 1)) +
 183                                          LS2088A_PCIE1_PHYS_ADDR +
 184                                          LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 185                 if (mem)
 186                         mem->phys_start = (mem->phys_start &
 187                                          (PCIE_PHYS_SIZE - 1)) +
 188                                          LS2088A_PCIE1_PHYS_ADDR +
 189                                          LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 190                 if (pref)
 191                         pref->phys_start = (pref->phys_start &
 192                                          (PCIE_PHYS_SIZE - 1)) +
 193                                          LS2088A_PCIE1_PHYS_ADDR +
 194                                          LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 195         }
 196
 197         if (io)
 198                 /* ATU : OUTBOUND : IO */
 199                 ls_pcie_atu_outbound_set(pcie, idx++,
 200                                          PCIE_ATU_TYPE_IO,
 201                                          io->phys_start + offset,
 202                                          io->bus_start,
 203                                          io->size);
 204
 205         if (mem)
 206                 /* ATU : OUTBOUND : MEM */
 207                 ls_pcie_atu_outbound_set(pcie, idx++,
 208                                          PCIE_ATU_TYPE_MEM,
 209                                          mem->phys_start + offset,
 210                                          mem->bus_start,
 211                                          mem->size);
 212
 213         if (pref)
 214                 /* ATU : OUTBOUND : pref */
 215                 ls_pcie_atu_outbound_set(pcie, idx++,
 216                                          PCIE_ATU_TYPE_MEM,
 217                                          pref->phys_start + offset,
 218                                          pref->bus_start,
 219                                          pref->size);
 220
 221         ls_pcie_dump_atu(pcie);
 222 }
 223
 224 /* Return 0 if the address is valid, -errno if not valid */
 225 static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
 226 {
 227         struct udevice *bus = pcie->bus;
 228
 229         if (!pcie->enabled)
 230                 return -ENXIO;
 231
 232         if (PCI_BUS(bdf) < bus->seq)
 233                 return -EINVAL;
 234
 235         if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
 236                 return -EINVAL;
 237
 238         if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
 239                 return -EINVAL;
 240
 241         return 0;
 242 }
 243
 244 void *ls_pcie_conf_address(struct ls_pcie *pcie, pci_dev_t bdf,
 245                                    int offset)
 246 {
 247         struct udevice *bus = pcie->bus;
 248         u32 busdev;
 249
 250         if (PCI_BUS(bdf) == bus->seq)
 251                 return pcie->dbi + offset;
 252
 253         busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) |
 254                  PCIE_ATU_DEV(PCI_DEV(bdf)) |
 255                  PCIE_ATU_FUNC(PCI_FUNC(bdf));
 256
 257         if (PCI_BUS(bdf) == bus->seq + 1) {
 258                 ls_pcie_cfg0_set_busdev(pcie, busdev);
 259                 return pcie->cfg0 + offset;
 260         } else {
 261                 ls_pcie_cfg1_set_busdev(pcie, busdev);
 262                 return pcie->cfg1 + offset;
 263         }
 264 }
 265
 266 static int ls_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
 267                                uint offset, ulong *valuep,
 268                                enum pci_size_t size)
 269 {
 270         struct ls_pcie *pcie = dev_get_priv(bus);
 271         void *address;
 272
 273         if (ls_pcie_addr_valid(pcie, bdf)) {
 274                 *valuep = pci_get_ff(size);
 275                 return 0;
 276         }
 277
 278         address = ls_pcie_conf_address(pcie, bdf, offset);
 279
 280         switch (size) {
 281         case PCI_SIZE_8:
 282                 *valuep = readb(address);
 283                 return 0;
 284         case PCI_SIZE_16:
 285                 *valuep = readw(address);
 286                 return 0;
 287         case PCI_SIZE_32:
 288                 *valuep = readl(address);
 289                 return 0;
 290         default:
 291                 return -EINVAL;
 292         }
 293 }
 294
 295 static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
 296                                 uint offset, ulong value,
 297                                 enum pci_size_t size)
 298 {
 299         struct ls_pcie *pcie = dev_get_priv(bus);
 300         void *address;
 301
 302         if (ls_pcie_addr_valid(pcie, bdf))
 303                 return 0;
 304
 305         address = ls_pcie_conf_address(pcie, bdf, offset);
 306
 307         switch (size) {
 308         case PCI_SIZE_8:
 309                 writeb(value, address);
 310                 return 0;
 311         case PCI_SIZE_16:
 312                 writew(value, address);
 313                 return 0;
 314         case PCI_SIZE_32:
 315                 writel(value, address);
 316                 return 0;
 317         default:
 318                 return -EINVAL;
 319         }
 320 }
 321
 322 /* Clear multi-function bit */
 323 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
 324 {
 325         writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
 326 }
 327
 328 /* Fix class value */
 329 static void ls_pcie_fix_class(struct ls_pcie *pcie)
 330 {
 331         writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
 332 }
 333
 334 /* Drop MSG TLP except for Vendor MSG */
 335 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
 336 {
 337         u32 val;
 338
 339         val = dbi_readl(pcie, PCIE_STRFMR1);
 340         val &= 0xDFFFFFFF;
 341         dbi_writel(pcie, val, PCIE_STRFMR1);
 342 }
 343
 344 /* Disable all bars in RC mode */
 345 static void ls_pcie_disable_bars(struct ls_pcie *pcie)
 346 {
 347         u32 sriov;
 348
 349         sriov = in_le32(pcie->dbi + PCIE_SRIOV);
 350
 351         /*
 352          * TODO: For PCIe controller with SRIOV, the method to disable bars
 353          * is different and more complex, so will add later.
 354          */
 355         if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV)
 356                 return;
 357
 358         dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
 359         dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
 360         dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
 361 }
 362
 363 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
 364 {
 365         ls_pcie_setup_atu(pcie);
 366
 367         dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
 368         ls_pcie_fix_class(pcie);
 369         ls_pcie_clear_multifunction(pcie);
 370         ls_pcie_drop_msg_tlp(pcie);
 371         dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
 372
 373         ls_pcie_disable_bars(pcie);
 374 }
 375
 376 static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
 377 {
 378         u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
 379
 380         /* ATU 0 : INBOUND : map BAR0 */
 381         ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
 382         /* ATU 1 : INBOUND : map BAR1 */
 383         phys += PCIE_BAR1_SIZE;
 384         ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
 385         /* ATU 2 : INBOUND : map BAR2 */
 386         phys += PCIE_BAR2_SIZE;
 387         ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
 388         /* ATU 3 : INBOUND : map BAR4 */
 389         phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
 390         ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
 391
 392         /* ATU 0 : OUTBOUND : map MEM */
 393         ls_pcie_atu_outbound_set(pcie, 0,
 394                                  PCIE_ATU_TYPE_MEM,
 395                                  pcie->cfg_res.start,
 396                                  0,
 397                                  CONFIG_SYS_PCI_MEMORY_SIZE);
 398 }
 399
 400 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
 401 static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
 402 {
 403         /* The least inbound window is 4KiB */
 404         if (size < 4 * 1024)
 405                 return;
 406
 407         switch (bar) {
 408         case 0:
 409                 writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
 410                 break;
 411         case 1:
 412                 writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
 413                 break;
 414         case 2:
 415                 writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
 416                 writel(0, bar_base + PCI_BASE_ADDRESS_3);
 417                 break;
 418         case 4:
 419                 writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
 420                 writel(0, bar_base + PCI_BASE_ADDRESS_5);
 421                 break;
 422         default:
 423                 break;
 424         }
 425 }
 426
 427 static void ls_pcie_ep_setup_bars(void *bar_base)
 428 {
 429         /* BAR0 - 32bit - 4K configuration */
 430         ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
 431         /* BAR1 - 32bit - 8K MSIX*/
 432         ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
 433         /* BAR2 - 64bit - 4K MEM desciptor */
 434         ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
 435         /* BAR4 - 64bit - 1M MEM*/
 436         ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
 437 }
 438
 439 static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
 440 {
 441         ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
 442 }
 443
 444 static void ls_pcie_setup_ep(struct ls_pcie *pcie)
 445 {
 446         u32 sriov;
 447
 448         sriov = readl(pcie->dbi + PCIE_SRIOV);
 449         if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
 450                 int pf, vf;
 451
 452                 for (pf = 0; pf < PCIE_PF_NUM; pf++) {
 453                         for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
 454                                 ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
 455                                             PCIE_PF_VF_CTRL);
 456
 457                                 ls_pcie_ep_setup_bars(pcie->dbi);
 458                                 ls_pcie_ep_setup_atu(pcie);
 459                         }
 460                 }
 461                 /* Disable CFG2 */
 462                 ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
 463         } else {
 464                 ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
 465                 ls_pcie_ep_setup_atu(pcie);
 466         }
 467
 468         ls_pcie_ep_enable_cfg(pcie);
 469 }
 470
 471 static int ls_pcie_probe(struct udevice *dev)
 472 {
 473         struct ls_pcie *pcie = dev_get_priv(dev);
 474         const void *fdt = gd->fdt_blob;
 475         int node = dev_of_offset(dev);
 476         u8 header_type;
 477         u16 link_sta;
 478         bool ep_mode;
 479         uint svr;
 480         int ret;
 481
 482         pcie->bus = dev;
 483
 484         ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
 485                                      "dbi", &pcie->dbi_res);
 486         if (ret) {
 487                 printf("ls-pcie: resource \"dbi\" not found\n");
 488                 return ret;
 489         }
 490
 491         pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
 492
 493         list_add(&pcie->list, &ls_pcie_list);
 494
 495         pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
 496         if (!pcie->enabled) {
 497                 printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
 498                 return 0;
 499         }
 500
 501         pcie->dbi = map_physmem(pcie->dbi_res.start,
 502                                 fdt_resource_size(&pcie->dbi_res),
 503                                 MAP_NOCACHE);
 504
 505         ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
 506                                      "lut", &pcie->lut_res);
 507         if (!ret)
 508                 pcie->lut = map_physmem(pcie->lut_res.start,
 509                                         fdt_resource_size(&pcie->lut_res),
 510                                         MAP_NOCACHE);
 511
 512         ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
 513                                      "ctrl", &pcie->ctrl_res);
 514         if (!ret)
 515                 pcie->ctrl = map_physmem(pcie->ctrl_res.start,
 516                                          fdt_resource_size(&pcie->ctrl_res),
 517                                          MAP_NOCACHE);
 518         if (!pcie->ctrl)
 519                 pcie->ctrl = pcie->lut;
 520
 521         if (!pcie->ctrl) {
 522                 printf("%s: NOT find CTRL\n", dev->name);
 523                 return -1;
 524         }
 525
 526         ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
 527                                      "config", &pcie->cfg_res);
 528         if (ret) {
 529                 printf("%s: resource \"config\" not found\n", dev->name);
 530                 return ret;
 531         }
 532
 533         /*
 534          * Fix the pcie memory map address and PF control registers address
 535          * for LS2088A series SoCs
 536          */
 537         svr = get_svr();
 538         svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 539         if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 540             svr == SVR_LS2048A || svr == SVR_LS2044A ||
 541             svr == SVR_LS2081A || svr == SVR_LS2041A) {
 542                 pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
 543                                         LS2088A_PCIE_PHYS_SIZE * pcie->idx;
 544                 pcie->ctrl = pcie->lut + 0x40000;
 545         }
 546
 547         pcie->cfg0 = map_physmem(pcie->cfg_res.start,
 548                                  fdt_resource_size(&pcie->cfg_res),
 549                                  MAP_NOCACHE);
 550         pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
 551
 552         pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
 553
 554         debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
 555               dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
 556               (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
 557               pcie->big_endian);
 558
 559         header_type = readb(pcie->dbi + PCI_HEADER_TYPE);
 560         ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
 561         printf("PCIe%u: %s %s", pcie->idx, dev->name,
 562                ep_mode ? "Endpoint" : "Root Complex");
 563
 564         if (ep_mode)
 565                 ls_pcie_setup_ep(pcie);
 566         else
 567                 ls_pcie_setup_ctrl(pcie);
 568
 569         if (!ls_pcie_link_up(pcie)) {
 570                 /* Let the user know there's no PCIe link */
 571                 printf(": no link\n");
 572                 return 0;
 573         }
 574
 575         /* Print the negotiated PCIe link width */
 576         link_sta = readw(pcie->dbi + PCIE_LINK_STA);
 577         printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
 578                link_sta & PCIE_LINK_SPEED_MASK);
 579
 580         return 0;
 581 }
 582
 583 static const struct dm_pci_ops ls_pcie_ops = {
 584         .read_config    = ls_pcie_read_config,
 585         .write_config   = ls_pcie_write_config,
 586 };
 587
 588 static const struct udevice_id ls_pcie_ids[] = {
 589         { .compatible = "fsl,ls-pcie" },
 590         { }
 591 };
 592
 593 U_BOOT_DRIVER(pci_layerscape) = {
 594         .name = "pci_layerscape",
 595         .id = UCLASS_PCI,
 596         .of_match = ls_pcie_ids,
 597         .ops = &ls_pcie_ops,
 598         .probe  = ls_pcie_probe,
 599         .priv_auto_alloc_size = sizeof(struct ls_pcie),
 600 };