2 * (C) Copyright 2004 Tundra Semiconductor Corp.
3 * Alex Bounine <alexandreb@tundra.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * PCI initialisation for the Tsi108 EMU board.
34 #if defined(CONFIG_OF_LIBFDT)
36 #include <fdt_support.h>
39 struct pci_controller local_hose
;
41 void tsi108_clear_pci_error (void)
43 u32 err_stat
, err_addr
, pci_stat
;
46 * Quietly clear errors signalled as result of PCI/X configuration read
49 /* Read PB Error Log Registers */
50 err_stat
= *(volatile u32
*)(CONFIG_SYS_TSI108_CSR_BASE
+
51 TSI108_PB_REG_OFFSET
+ PB_ERRCS
);
52 err_addr
= *(volatile u32
*)(CONFIG_SYS_TSI108_CSR_BASE
+
53 TSI108_PB_REG_OFFSET
+ PB_AERR
);
54 if (err_stat
& PB_ERRCS_ES
) {
55 /* Clear PCI/X bus errors if applicable */
56 if ((err_addr
& 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE
) {
57 /* Clear error flag */
58 *(u32
*) (CONFIG_SYS_TSI108_CSR_BASE
+
59 TSI108_PB_REG_OFFSET
+ PB_ERRCS
) =
62 /* Clear read error reported in PB_ISR */
63 *(u32
*) (CONFIG_SYS_TSI108_CSR_BASE
+
64 TSI108_PB_REG_OFFSET
+ PB_ISR
) =
67 /* Clear errors reported by PCI CSR (Normally Master Abort) */
68 pci_stat
= *(volatile u32
*)(CONFIG_SYS_TSI108_CSR_BASE
+
69 TSI108_PCI_REG_OFFSET
+
71 *(volatile u32
*)(CONFIG_SYS_TSI108_CSR_BASE
+
72 TSI108_PCI_REG_OFFSET
+ PCI_CSR
) =
75 *(volatile u32
*)(CONFIG_SYS_TSI108_CSR_BASE
+
76 TSI108_PCI_REG_OFFSET
+
77 PCI_IRP_STAT
) = PCI_IRP_STAT_P_CSR
;
84 unsigned int __get_pci_config_dword (u32 addr
)
88 __asm__
__volatile__ (" lwbrx %0,0,%1\n"
91 ".section .fixup,\"ax\"\n"
94 ".section __ex_table,\"a\"\n"
97 ".text":"=r"(retval
):"r"(addr
));
102 static int tsi108_read_config_dword (struct pci_controller
*hose
,
103 pci_dev_t dev
, int offset
, u32
* value
)
105 dev
&= (CONFIG_SYS_PCI_CFG_SIZE
- 1);
106 dev
|= (CONFIG_SYS_PCI_CFG_BASE
| (offset
& 0xfc));
107 *value
= __get_pci_config_dword(dev
);
108 if (0xFFFFFFFF == *value
)
109 tsi108_clear_pci_error ();
113 static int tsi108_write_config_dword (struct pci_controller
*hose
,
114 pci_dev_t dev
, int offset
, u32 value
)
116 dev
&= (CONFIG_SYS_PCI_CFG_SIZE
- 1);
117 dev
|= (CONFIG_SYS_PCI_CFG_BASE
| (offset
& 0xfc));
119 out_le32 ((volatile unsigned *)dev
, value
);
124 void pci_init_board (void)
126 struct pci_controller
*hose
= (struct pci_controller
*)&local_hose
;
128 hose
->first_busno
= 0;
129 hose
->last_busno
= 0xff;
131 pci_set_region (hose
->regions
+ 0,
132 CONFIG_SYS_PCI_MEMORY_BUS
,
133 CONFIG_SYS_PCI_MEMORY_PHYS
,
134 CONFIG_SYS_PCI_MEMORY_SIZE
, PCI_REGION_MEM
| PCI_REGION_MEMORY
);
136 /* PCI memory space */
137 pci_set_region (hose
->regions
+ 1,
138 CONFIG_SYS_PCI_MEM_BUS
,
139 CONFIG_SYS_PCI_MEM_PHYS
, CONFIG_SYS_PCI_MEM_SIZE
, PCI_REGION_MEM
);
142 pci_set_region (hose
->regions
+ 2,
143 CONFIG_SYS_PCI_IO_BUS
,
144 CONFIG_SYS_PCI_IO_PHYS
, CONFIG_SYS_PCI_IO_SIZE
, PCI_REGION_IO
);
146 hose
->region_count
= 3;
149 pci_hose_read_config_byte_via_dword
,
150 pci_hose_read_config_word_via_dword
,
151 tsi108_read_config_dword
,
152 pci_hose_write_config_byte_via_dword
,
153 pci_hose_write_config_word_via_dword
,
154 tsi108_write_config_dword
);
156 pci_register_hose (hose
);
158 hose
->last_busno
= pci_hose_scan (hose
);
160 debug ("Done PCI initialization\n");
164 #if defined(CONFIG_OF_LIBFDT)
165 void ft_pci_setup(void *blob
, bd_t
*bd
)
171 nodeoffset
= fdt_path_offset(blob
, "/aliases");
172 if (nodeoffset
>= 0) {
173 path
= fdt_getprop(blob
, nodeoffset
, "pci", NULL
);
175 tmp
[0] = cpu_to_be32(local_hose
.first_busno
);
176 tmp
[1] = cpu_to_be32(local_hose
.last_busno
);
177 do_fixup_by_path(blob
, path
, "bus-range",
178 &tmp
, sizeof(tmp
), 1);
182 #endif /* CONFIG_OF_LIBFDT */