2 * Pin Control driver for SuperH Pin Function Controller.
4 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 * Copyright (C) 2008 Magnus Damm
7 * Copyright (C) 2009 - 2012 Paul Mundt
8 * Copyright (C) 2017 Marek Vasut
10 * SPDX-License-Identifier: GPL-2.0
13 #define DRV_NAME "sh-pfc"
18 #include <dm/pinctrl.h>
20 #include <linux/sizes.h>
24 DECLARE_GLOBAL_DATA_PTR
;
37 struct sh_pfc_pin_config
{
41 struct sh_pfc_pinctrl
{
44 struct sh_pfc_pin_config
*configs
;
46 const char *func_prop_name
;
47 const char *groups_prop_name
;
48 const char *pins_prop_name
;
51 struct sh_pfc_pin_range
{
56 struct sh_pfc_pinctrl_priv
{
58 struct sh_pfc_pinctrl pmx
;
61 int sh_pfc_get_pin_index(struct sh_pfc
*pfc
, unsigned int pin
)
66 for (i
= 0, offset
= 0; i
< pfc
->nr_ranges
; ++i
) {
67 const struct sh_pfc_pin_range
*range
= &pfc
->ranges
[i
];
69 if (pin
<= range
->end
)
70 return pin
>= range
->start
71 ? offset
+ pin
- range
->start
: -1;
73 offset
+= range
->end
- range
->start
+ 1;
79 static int sh_pfc_enum_in_range(u16 enum_id
, const struct pinmux_range
*r
)
81 if (enum_id
< r
->begin
)
90 u32
sh_pfc_read_raw_reg(void __iomem
*mapped_reg
, unsigned int reg_width
)
94 return readb(mapped_reg
);
96 return readw(mapped_reg
);
98 return readl(mapped_reg
);
105 void sh_pfc_write_raw_reg(void __iomem
*mapped_reg
, unsigned int reg_width
,
110 writeb(data
, mapped_reg
);
113 writew(data
, mapped_reg
);
116 writel(data
, mapped_reg
);
123 u32
sh_pfc_read_reg(struct sh_pfc
*pfc
, u32 reg
, unsigned int width
)
125 return sh_pfc_read_raw_reg(pfc
->regs
+ reg
, width
);
128 void sh_pfc_write_reg(struct sh_pfc
*pfc
, u32 reg
, unsigned int width
, u32 data
)
130 void __iomem
*unlock_reg
=
131 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
133 if (pfc
->info
->unlock_reg
)
134 sh_pfc_write_raw_reg(unlock_reg
, 32, ~data
);
136 sh_pfc_write_raw_reg(pfc
->regs
+ reg
, width
, data
);
139 static void sh_pfc_config_reg_helper(struct sh_pfc
*pfc
,
140 const struct pinmux_cfg_reg
*crp
,
142 void __iomem
**mapped_regp
, u32
*maskp
,
147 *mapped_regp
= (void __iomem
*)(uintptr_t)crp
->reg
;
149 if (crp
->field_width
) {
150 *maskp
= (1 << crp
->field_width
) - 1;
151 *posp
= crp
->reg_width
- ((in_pos
+ 1) * crp
->field_width
);
153 *maskp
= (1 << crp
->var_field_width
[in_pos
]) - 1;
154 *posp
= crp
->reg_width
;
155 for (k
= 0; k
<= in_pos
; k
++)
156 *posp
-= crp
->var_field_width
[k
];
160 static void sh_pfc_write_config_reg(struct sh_pfc
*pfc
,
161 const struct pinmux_cfg_reg
*crp
,
162 unsigned int field
, u32 value
)
164 void __iomem
*mapped_reg
;
165 void __iomem
*unlock_reg
=
166 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
170 sh_pfc_config_reg_helper(pfc
, crp
, field
, &mapped_reg
, &mask
, &pos
);
172 dev_dbg(pfc
->dev
, "write_reg addr = %x, value = 0x%x, field = %u, "
173 "r_width = %u, f_width = %u\n",
174 crp
->reg
, value
, field
, crp
->reg_width
, crp
->field_width
);
176 mask
= ~(mask
<< pos
);
177 value
= value
<< pos
;
179 data
= sh_pfc_read_raw_reg(mapped_reg
, crp
->reg_width
);
183 if (pfc
->info
->unlock_reg
)
184 sh_pfc_write_raw_reg(unlock_reg
, 32, ~data
);
186 sh_pfc_write_raw_reg(mapped_reg
, crp
->reg_width
, data
);
189 static int sh_pfc_get_config_reg(struct sh_pfc
*pfc
, u16 enum_id
,
190 const struct pinmux_cfg_reg
**crp
,
191 unsigned int *fieldp
, u32
*valuep
)
196 const struct pinmux_cfg_reg
*config_reg
=
197 pfc
->info
->cfg_regs
+ k
;
198 unsigned int r_width
= config_reg
->reg_width
;
199 unsigned int f_width
= config_reg
->field_width
;
200 unsigned int curr_width
;
201 unsigned int bit_pos
;
202 unsigned int pos
= 0;
208 for (bit_pos
= 0; bit_pos
< r_width
; bit_pos
+= curr_width
) {
213 curr_width
= f_width
;
215 curr_width
= config_reg
->var_field_width
[m
];
217 ncomb
= 1 << curr_width
;
218 for (n
= 0; n
< ncomb
; n
++) {
219 if (config_reg
->enum_ids
[pos
+ n
] == enum_id
) {
235 static int sh_pfc_mark_to_enum(struct sh_pfc
*pfc
, u16 mark
, int pos
,
238 const u16
*data
= pfc
->info
->pinmux_data
;
242 *enum_idp
= data
[pos
+ 1];
246 for (k
= 0; k
< pfc
->info
->pinmux_data_size
; k
++) {
247 if (data
[k
] == mark
) {
248 *enum_idp
= data
[k
+ 1];
253 dev_err(pfc
->dev
, "cannot locate data/mark enum_id for mark %d\n",
258 int sh_pfc_config_mux(struct sh_pfc
*pfc
, unsigned mark
, int pinmux_type
)
260 const struct pinmux_range
*range
;
263 switch (pinmux_type
) {
264 case PINMUX_TYPE_GPIO
:
265 case PINMUX_TYPE_FUNCTION
:
269 case PINMUX_TYPE_OUTPUT
:
270 range
= &pfc
->info
->output
;
273 case PINMUX_TYPE_INPUT
:
274 range
= &pfc
->info
->input
;
281 /* Iterate over all the configuration fields we need to update. */
283 const struct pinmux_cfg_reg
*cr
;
290 pos
= sh_pfc_mark_to_enum(pfc
, mark
, pos
, &enum_id
);
297 /* Check if the configuration field selects a function. If it
298 * doesn't, skip the field if it's not applicable to the
299 * requested pinmux type.
301 in_range
= sh_pfc_enum_in_range(enum_id
, &pfc
->info
->function
);
303 if (pinmux_type
== PINMUX_TYPE_FUNCTION
) {
304 /* Functions are allowed to modify all
308 } else if (pinmux_type
!= PINMUX_TYPE_GPIO
) {
309 /* Input/output types can only modify fields
310 * that correspond to their respective ranges.
312 in_range
= sh_pfc_enum_in_range(enum_id
, range
);
315 * special case pass through for fixed
316 * input-only or output-only pins without
317 * function enum register association.
319 if (in_range
&& enum_id
== range
->force
)
322 /* GPIOs are only allowed to modify function fields. */
328 ret
= sh_pfc_get_config_reg(pfc
, enum_id
, &cr
, &field
, &value
);
332 sh_pfc_write_config_reg(pfc
, cr
, field
, value
);
338 const struct sh_pfc_bias_info
*
339 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info
*info
,
340 unsigned int num
, unsigned int pin
)
344 for (i
= 0; i
< num
; i
++)
345 if (info
[i
].pin
== pin
)
348 printf("Pin %u is not in bias info list\n", pin
);
353 static int sh_pfc_init_ranges(struct sh_pfc
*pfc
)
355 struct sh_pfc_pin_range
*range
;
356 unsigned int nr_ranges
;
359 if (pfc
->info
->pins
[0].pin
== (u16
)-1) {
360 /* Pin number -1 denotes that the SoC doesn't report pin numbers
361 * in its pin arrays yet. Consider the pin numbers range as
362 * continuous and allocate a single range.
365 pfc
->ranges
= kzalloc(sizeof(*pfc
->ranges
), GFP_KERNEL
);
366 if (pfc
->ranges
== NULL
)
369 pfc
->ranges
->start
= 0;
370 pfc
->ranges
->end
= pfc
->info
->nr_pins
- 1;
371 pfc
->nr_gpio_pins
= pfc
->info
->nr_pins
;
376 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
377 * be sorted by pin numbers, and pins without a GPIO port must come
380 for (i
= 1, nr_ranges
= 1; i
< pfc
->info
->nr_pins
; ++i
) {
381 if (pfc
->info
->pins
[i
-1].pin
!= pfc
->info
->pins
[i
].pin
- 1)
385 pfc
->nr_ranges
= nr_ranges
;
386 pfc
->ranges
= kzalloc(sizeof(*pfc
->ranges
) * nr_ranges
, GFP_KERNEL
);
387 if (pfc
->ranges
== NULL
)
391 range
->start
= pfc
->info
->pins
[0].pin
;
393 for (i
= 1; i
< pfc
->info
->nr_pins
; ++i
) {
394 if (pfc
->info
->pins
[i
-1].pin
== pfc
->info
->pins
[i
].pin
- 1)
397 range
->end
= pfc
->info
->pins
[i
-1].pin
;
398 if (!(pfc
->info
->pins
[i
-1].configs
& SH_PFC_PIN_CFG_NO_GPIO
))
399 pfc
->nr_gpio_pins
= range
->end
+ 1;
402 range
->start
= pfc
->info
->pins
[i
].pin
;
405 range
->end
= pfc
->info
->pins
[i
-1].pin
;
406 if (!(pfc
->info
->pins
[i
-1].configs
& SH_PFC_PIN_CFG_NO_GPIO
))
407 pfc
->nr_gpio_pins
= range
->end
+ 1;
412 static int sh_pfc_pinctrl_get_pins_count(struct udevice
*dev
)
414 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
416 return priv
->pfc
.info
->nr_pins
;
419 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice
*dev
,
422 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
424 return priv
->pfc
.info
->pins
[selector
].name
;
427 static int sh_pfc_pinctrl_get_groups_count(struct udevice
*dev
)
429 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
431 return priv
->pfc
.info
->nr_groups
;
434 static const char *sh_pfc_pinctrl_get_group_name(struct udevice
*dev
,
437 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
439 return priv
->pfc
.info
->groups
[selector
].name
;
442 static int sh_pfc_pinctrl_get_functions_count(struct udevice
*dev
)
444 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
446 return priv
->pfc
.info
->nr_functions
;
449 static const char *sh_pfc_pinctrl_get_function_name(struct udevice
*dev
,
452 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
454 return priv
->pfc
.info
->functions
[selector
].name
;
457 int sh_pfc_config_mux_for_gpio(struct udevice
*dev
, unsigned pin_selector
)
459 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
460 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
461 struct sh_pfc
*pfc
= &priv
->pfc
;
462 struct sh_pfc_pin_config
*cfg
;
463 const struct sh_pfc_pin
*pin
= NULL
;
466 for (i
= 1; i
< pfc
->info
->nr_pins
; i
++) {
467 if (priv
->pfc
.info
->pins
[i
].pin
!= pin_selector
)
470 pin
= &priv
->pfc
.info
->pins
[i
];
477 idx
= sh_pfc_get_pin_index(pfc
, pin
->pin
);
478 cfg
= &pmx
->configs
[idx
];
480 if (cfg
->type
!= PINMUX_TYPE_NONE
)
483 return sh_pfc_config_mux(pfc
, pin
->enum_id
, PINMUX_TYPE_GPIO
);
486 static int sh_pfc_pinctrl_pin_set(struct udevice
*dev
, unsigned pin_selector
,
487 unsigned func_selector
)
489 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
490 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
491 struct sh_pfc
*pfc
= &priv
->pfc
;
492 const struct sh_pfc_pin
*pin
= &priv
->pfc
.info
->pins
[pin_selector
];
493 int idx
= sh_pfc_get_pin_index(pfc
, pin
->pin
);
494 struct sh_pfc_pin_config
*cfg
= &pmx
->configs
[idx
];
496 if (cfg
->type
!= PINMUX_TYPE_NONE
)
499 return sh_pfc_config_mux(pfc
, pin
->enum_id
, PINMUX_TYPE_FUNCTION
);
502 static int sh_pfc_pinctrl_group_set(struct udevice
*dev
, unsigned group_selector
,
503 unsigned func_selector
)
505 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
506 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
507 struct sh_pfc
*pfc
= &priv
->pfc
;
508 const struct sh_pfc_pin_group
*grp
= &priv
->pfc
.info
->groups
[group_selector
];
512 for (i
= 0; i
< grp
->nr_pins
; ++i
) {
513 int idx
= sh_pfc_get_pin_index(pfc
, grp
->pins
[i
]);
514 struct sh_pfc_pin_config
*cfg
= &pmx
->configs
[idx
];
516 if (cfg
->type
!= PINMUX_TYPE_NONE
) {
522 for (i
= 0; i
< grp
->nr_pins
; ++i
) {
523 ret
= sh_pfc_config_mux(pfc
, grp
->mux
[i
], PINMUX_TYPE_FUNCTION
);
531 #if CONFIG_IS_ENABLED(PINCONF)
532 static const struct pinconf_param sh_pfc_pinconf_params
[] = {
533 { "bias-disable", PIN_CONFIG_BIAS_DISABLE
, 0 },
534 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP
, 1 },
535 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN
, 1 },
536 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH
, 0 },
537 { "power-source", PIN_CONFIG_POWER_SOURCE
, 3300 },
540 static void __iomem
*
541 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc
*pfc
, unsigned int pin
,
542 unsigned int *offset
, unsigned int *size
)
544 const struct pinmux_drive_reg_field
*field
;
545 const struct pinmux_drive_reg
*reg
;
548 for (reg
= pfc
->info
->drive_regs
; reg
->reg
; ++reg
) {
549 for (i
= 0; i
< ARRAY_SIZE(reg
->fields
); ++i
) {
550 field
= ®
->fields
[i
];
552 if (field
->size
&& field
->pin
== pin
) {
553 *offset
= field
->offset
;
556 return (void __iomem
*)(uintptr_t)reg
->reg
;
564 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc
*pfc
,
565 unsigned int pin
, u16 strength
)
571 void __iomem
*unlock_reg
=
572 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
575 reg
= sh_pfc_pinconf_find_drive_strength_reg(pfc
, pin
, &offset
, &size
);
579 step
= size
== 2 ? 6 : 3;
581 if (strength
< step
|| strength
> 24)
584 /* Convert the value from mA based on a full drive strength value of
585 * 24mA. We can make the full value configurable later if needed.
587 strength
= strength
/ step
- 1;
589 val
= sh_pfc_read_raw_reg(reg
, 32);
590 val
&= ~GENMASK(offset
+ size
- 1, offset
);
591 val
|= strength
<< offset
;
594 sh_pfc_write_raw_reg(unlock_reg
, 32, ~val
);
596 sh_pfc_write_raw_reg(reg
, 32, val
);
601 /* Check whether the requested parameter is supported for a pin. */
602 static bool sh_pfc_pinconf_validate(struct sh_pfc
*pfc
, unsigned int _pin
,
605 int idx
= sh_pfc_get_pin_index(pfc
, _pin
);
606 const struct sh_pfc_pin
*pin
= &pfc
->info
->pins
[idx
];
609 case PIN_CONFIG_BIAS_DISABLE
:
610 return pin
->configs
&
611 (SH_PFC_PIN_CFG_PULL_UP
| SH_PFC_PIN_CFG_PULL_DOWN
);
613 case PIN_CONFIG_BIAS_PULL_UP
:
614 return pin
->configs
& SH_PFC_PIN_CFG_PULL_UP
;
616 case PIN_CONFIG_BIAS_PULL_DOWN
:
617 return pin
->configs
& SH_PFC_PIN_CFG_PULL_DOWN
;
619 case PIN_CONFIG_DRIVE_STRENGTH
:
620 return pin
->configs
& SH_PFC_PIN_CFG_DRIVE_STRENGTH
;
622 case PIN_CONFIG_POWER_SOURCE
:
623 return pin
->configs
& SH_PFC_PIN_CFG_IO_VOLTAGE
;
630 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl
*pmx
, unsigned _pin
,
631 unsigned int param
, unsigned int arg
)
633 struct sh_pfc
*pfc
= pmx
->pfc
;
634 void __iomem
*pocctrl
;
635 void __iomem
*unlock_reg
=
636 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
640 if (!sh_pfc_pinconf_validate(pfc
, _pin
, param
))
644 case PIN_CONFIG_BIAS_PULL_UP
:
645 case PIN_CONFIG_BIAS_PULL_DOWN
:
646 case PIN_CONFIG_BIAS_DISABLE
:
647 if (!pfc
->info
->ops
|| !pfc
->info
->ops
->set_bias
)
650 pfc
->info
->ops
->set_bias(pfc
, _pin
, param
);
654 case PIN_CONFIG_DRIVE_STRENGTH
:
655 ret
= sh_pfc_pinconf_set_drive_strength(pfc
, _pin
, arg
);
661 case PIN_CONFIG_POWER_SOURCE
:
662 if (!pfc
->info
->ops
|| !pfc
->info
->ops
->pin_to_pocctrl
)
665 bit
= pfc
->info
->ops
->pin_to_pocctrl(pfc
, _pin
, &addr
);
667 printf("invalid pin %#x", _pin
);
671 if (arg
!= 1800 && arg
!= 3300)
674 pocctrl
= (void __iomem
*)(uintptr_t)addr
;
676 val
= sh_pfc_read_raw_reg(pocctrl
, 32);
683 sh_pfc_write_raw_reg(unlock_reg
, 32, ~val
);
685 sh_pfc_write_raw_reg(pocctrl
, 32, val
);
696 static int sh_pfc_pinconf_pin_set(struct udevice
*dev
,
697 unsigned int pin_selector
,
698 unsigned int param
, unsigned int arg
)
700 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
701 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
702 struct sh_pfc
*pfc
= &priv
->pfc
;
703 const struct sh_pfc_pin
*pin
= &pfc
->info
->pins
[pin_selector
];
705 sh_pfc_pinconf_set(pmx
, pin
->pin
, param
, arg
);
710 static int sh_pfc_pinconf_group_set(struct udevice
*dev
,
711 unsigned int group_selector
,
712 unsigned int param
, unsigned int arg
)
714 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
715 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
716 struct sh_pfc
*pfc
= &priv
->pfc
;
717 const struct sh_pfc_pin_group
*grp
= &pfc
->info
->groups
[group_selector
];
720 for (i
= 0; i
< grp
->nr_pins
; i
++)
721 sh_pfc_pinconf_set(pmx
, grp
->pins
[i
], param
, arg
);
727 static struct pinctrl_ops sh_pfc_pinctrl_ops
= {
728 .get_pins_count
= sh_pfc_pinctrl_get_pins_count
,
729 .get_pin_name
= sh_pfc_pinctrl_get_pin_name
,
730 .get_groups_count
= sh_pfc_pinctrl_get_groups_count
,
731 .get_group_name
= sh_pfc_pinctrl_get_group_name
,
732 .get_functions_count
= sh_pfc_pinctrl_get_functions_count
,
733 .get_function_name
= sh_pfc_pinctrl_get_function_name
,
735 #if CONFIG_IS_ENABLED(PINCONF)
736 .pinconf_num_params
= ARRAY_SIZE(sh_pfc_pinconf_params
),
737 .pinconf_params
= sh_pfc_pinconf_params
,
738 .pinconf_set
= sh_pfc_pinconf_pin_set
,
739 .pinconf_group_set
= sh_pfc_pinconf_group_set
,
741 .pinmux_set
= sh_pfc_pinctrl_pin_set
,
742 .pinmux_group_set
= sh_pfc_pinctrl_group_set
,
743 .set_state
= pinctrl_generic_set_state
,
746 static int sh_pfc_map_pins(struct sh_pfc
*pfc
, struct sh_pfc_pinctrl
*pmx
)
750 /* Allocate and initialize the pins and configs arrays. */
751 pmx
->configs
= kzalloc(sizeof(*pmx
->configs
) * pfc
->info
->nr_pins
,
753 if (unlikely(!pmx
->configs
))
756 for (i
= 0; i
< pfc
->info
->nr_pins
; ++i
) {
757 struct sh_pfc_pin_config
*cfg
= &pmx
->configs
[i
];
758 cfg
->type
= PINMUX_TYPE_NONE
;
765 static int sh_pfc_pinctrl_probe(struct udevice
*dev
)
767 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
768 enum sh_pfc_model model
= dev_get_driver_data(dev
);
771 base
= devfdt_get_addr(dev
);
772 if (base
== FDT_ADDR_T_NONE
)
775 priv
->pfc
.regs
= devm_ioremap(dev
, base
, SZ_2K
);
779 #ifdef CONFIG_PINCTRL_PFC_R8A7790
780 if (model
== SH_PFC_R8A7790
)
781 priv
->pfc
.info
= &r8a7790_pinmux_info
;
783 #ifdef CONFIG_PINCTRL_PFC_R8A7791
784 if (model
== SH_PFC_R8A7791
)
785 priv
->pfc
.info
= &r8a7791_pinmux_info
;
787 #ifdef CONFIG_PINCTRL_PFC_R8A7792
788 if (model
== SH_PFC_R8A7792
)
789 priv
->pfc
.info
= &r8a7792_pinmux_info
;
791 #ifdef CONFIG_PINCTRL_PFC_R8A7793
792 if (model
== SH_PFC_R8A7793
)
793 priv
->pfc
.info
= &r8a7793_pinmux_info
;
795 #ifdef CONFIG_PINCTRL_PFC_R8A7795
796 if (model
== SH_PFC_R8A7795
)
797 priv
->pfc
.info
= &r8a7795_pinmux_info
;
799 #ifdef CONFIG_PINCTRL_PFC_R8A7796
800 if (model
== SH_PFC_R8A7796
)
801 priv
->pfc
.info
= &r8a7796_pinmux_info
;
803 #ifdef CONFIG_PINCTRL_PFC_R8A77970
804 if (model
== SH_PFC_R8A77970
)
805 priv
->pfc
.info
= &r8a77970_pinmux_info
;
807 #ifdef CONFIG_PINCTRL_PFC_R8A77995
808 if (model
== SH_PFC_R8A77995
)
809 priv
->pfc
.info
= &r8a77995_pinmux_info
;
812 priv
->pmx
.pfc
= &priv
->pfc
;
813 sh_pfc_init_ranges(&priv
->pfc
);
814 sh_pfc_map_pins(&priv
->pfc
, &priv
->pmx
);
819 static const struct udevice_id sh_pfc_pinctrl_ids
[] = {
820 #ifdef CONFIG_PINCTRL_PFC_R8A7790
822 .compatible
= "renesas,pfc-r8a7790",
823 .data
= SH_PFC_R8A7790
,
826 #ifdef CONFIG_PINCTRL_PFC_R8A7791
828 .compatible
= "renesas,pfc-r8a7791",
829 .data
= SH_PFC_R8A7791
,
832 #ifdef CONFIG_PINCTRL_PFC_R8A7792
834 .compatible
= "renesas,pfc-r8a7792",
835 .data
= SH_PFC_R8A7792
,
838 #ifdef CONFIG_PINCTRL_PFC_R8A7793
840 .compatible
= "renesas,pfc-r8a7793",
841 .data
= SH_PFC_R8A7793
,
844 #ifdef CONFIG_PINCTRL_PFC_R8A7795
846 .compatible
= "renesas,pfc-r8a7795",
847 .data
= SH_PFC_R8A7795
,
850 #ifdef CONFIG_PINCTRL_PFC_R8A7796
852 .compatible
= "renesas,pfc-r8a7796",
853 .data
= SH_PFC_R8A7796
,
856 #ifdef CONFIG_PINCTRL_PFC_R8A77970
858 .compatible
= "renesas,pfc-r8a77970",
859 .data
= SH_PFC_R8A77970
,
862 #ifdef CONFIG_PINCTRL_PFC_R8A77995
864 .compatible
= "renesas,pfc-r8a77995",
865 .data
= SH_PFC_R8A77995
,
871 U_BOOT_DRIVER(pinctrl_sh_pfc
) = {
872 .name
= "sh_pfc_pinctrl",
873 .id
= UCLASS_PINCTRL
,
874 .of_match
= sh_pfc_pinctrl_ids
,
875 .priv_auto_alloc_size
= sizeof(struct sh_pfc_pinctrl_priv
),
876 .ops
= &sh_pfc_pinctrl_ops
,
877 .probe
= sh_pfc_pinctrl_probe
,