drivers/pinctrl/renesas/pfc.c

   1 /*
   2  * Pin Control driver for SuperH Pin Function Controller.
   3  *
   4  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   5  *
   6  * Copyright (C) 2008 Magnus Damm
   7  * Copyright (C) 2009 - 2012 Paul Mundt
   8  * Copyright (C) 2017 Marek Vasut
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0
  11  */
  12
  13 #define DRV_NAME "sh-pfc"
  14
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/io.h>
  20 #include <linux/sizes.h>
  21
  22 #include "sh_pfc.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 enum sh_pfc_model {
  27         SH_PFC_R8A7790 = 0,
  28         SH_PFC_R8A7791,
  29         SH_PFC_R8A7792,
  30         SH_PFC_R8A7793,
  31         SH_PFC_R8A7794,
  32         SH_PFC_R8A7795,
  33         SH_PFC_R8A7796,
  34         SH_PFC_R8A77970,
  35         SH_PFC_R8A77995,
  36 };
  37
  38 struct sh_pfc_pin_config {
  39         u32 type;
  40 };
  41
  42 struct sh_pfc_pinctrl {
  43         struct sh_pfc *pfc;
  44
  45         struct sh_pfc_pin_config *configs;
  46
  47         const char *func_prop_name;
  48         const char *groups_prop_name;
  49         const char *pins_prop_name;
  50 };
  51
  52 struct sh_pfc_pin_range {
  53         u16 start;
  54         u16 end;
  55 };
  56
  57 struct sh_pfc_pinctrl_priv {
  58         struct sh_pfc                   pfc;
  59         struct sh_pfc_pinctrl           pmx;
  60 };
  61
  62 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  63 {
  64         unsigned int offset;
  65         unsigned int i;
  66
  67         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  68                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  69
  70                 if (pin <= range->end)
  71                         return pin >= range->start
  72                              ? offset + pin - range->start : -1;
  73
  74                 offset += range->end - range->start + 1;
  75         }
  76
  77         return -EINVAL;
  78 }
  79
  80 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  81 {
  82         if (enum_id < r->begin)
  83                 return 0;
  84
  85         if (enum_id > r->end)
  86                 return 0;
  87
  88         return 1;
  89 }
  90
  91 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  92 {
  93         switch (reg_width) {
  94         case 8:
  95                 return readb(mapped_reg);
  96         case 16:
  97                 return readw(mapped_reg);
  98         case 32:
  99                 return readl(mapped_reg);
 100         }
 101
 102         BUG();
 103         return 0;
 104 }
 105
 106 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 107                           u32 data)
 108 {
 109         switch (reg_width) {
 110         case 8:
 111                 writeb(data, mapped_reg);
 112                 return;
 113         case 16:
 114                 writew(data, mapped_reg);
 115                 return;
 116         case 32:
 117                 writel(data, mapped_reg);
 118                 return;
 119         }
 120
 121         BUG();
 122 }
 123
 124 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
 125 {
 126         return sh_pfc_read_raw_reg(pfc->regs + reg, width);
 127 }
 128
 129 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
 130 {
 131         void __iomem *unlock_reg =
 132                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 133
 134         if (pfc->info->unlock_reg)
 135                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 136
 137         sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
 138 }
 139
 140 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 141                                      const struct pinmux_cfg_reg *crp,
 142                                      unsigned int in_pos,
 143                                      void __iomem **mapped_regp, u32 *maskp,
 144                                      unsigned int *posp)
 145 {
 146         unsigned int k;
 147
 148         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
 149
 150         if (crp->field_width) {
 151                 *maskp = (1 << crp->field_width) - 1;
 152                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 153         } else {
 154                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 155                 *posp = crp->reg_width;
 156                 for (k = 0; k <= in_pos; k++)
 157                         *posp -= crp->var_field_width[k];
 158         }
 159 }
 160
 161 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 162                                     const struct pinmux_cfg_reg *crp,
 163                                     unsigned int field, u32 value)
 164 {
 165         void __iomem *mapped_reg;
 166         void __iomem *unlock_reg =
 167                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 168         unsigned int pos;
 169         u32 mask, data;
 170
 171         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 172
 173         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 174                 "r_width = %u, f_width = %u\n",
 175                 crp->reg, value, field, crp->reg_width, crp->field_width);
 176
 177         mask = ~(mask << pos);
 178         value = value << pos;
 179
 180         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 181         data &= mask;
 182         data |= value;
 183
 184         if (pfc->info->unlock_reg)
 185                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 186
 187         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 188 }
 189
 190 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 191                                  const struct pinmux_cfg_reg **crp,
 192                                  unsigned int *fieldp, u32 *valuep)
 193 {
 194         unsigned int k = 0;
 195
 196         while (1) {
 197                 const struct pinmux_cfg_reg *config_reg =
 198                         pfc->info->cfg_regs + k;
 199                 unsigned int r_width = config_reg->reg_width;
 200                 unsigned int f_width = config_reg->field_width;
 201                 unsigned int curr_width;
 202                 unsigned int bit_pos;
 203                 unsigned int pos = 0;
 204                 unsigned int m = 0;
 205
 206                 if (!r_width)
 207                         break;
 208
 209                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 210                         u32 ncomb;
 211                         u32 n;
 212
 213                         if (f_width)
 214                                 curr_width = f_width;
 215                         else
 216                                 curr_width = config_reg->var_field_width[m];
 217
 218                         ncomb = 1 << curr_width;
 219                         for (n = 0; n < ncomb; n++) {
 220                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 221                                         *crp = config_reg;
 222                                         *fieldp = m;
 223                                         *valuep = n;
 224                                         return 0;
 225                                 }
 226                         }
 227                         pos += ncomb;
 228                         m++;
 229                 }
 230                 k++;
 231         }
 232
 233         return -EINVAL;
 234 }
 235
 236 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 237                               u16 *enum_idp)
 238 {
 239         const u16 *data = pfc->info->pinmux_data;
 240         unsigned int k;
 241
 242         if (pos) {
 243                 *enum_idp = data[pos + 1];
 244                 return pos + 1;
 245         }
 246
 247         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 248                 if (data[k] == mark) {
 249                         *enum_idp = data[k + 1];
 250                         return k + 1;
 251                 }
 252         }
 253
 254         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 255                 mark);
 256         return -EINVAL;
 257 }
 258
 259 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 260 {
 261         const struct pinmux_range *range;
 262         int pos = 0;
 263
 264         switch (pinmux_type) {
 265         case PINMUX_TYPE_GPIO:
 266         case PINMUX_TYPE_FUNCTION:
 267                 range = NULL;
 268                 break;
 269
 270         case PINMUX_TYPE_OUTPUT:
 271                 range = &pfc->info->output;
 272                 break;
 273
 274         case PINMUX_TYPE_INPUT:
 275                 range = &pfc->info->input;
 276                 break;
 277
 278         default:
 279                 return -EINVAL;
 280         }
 281
 282         /* Iterate over all the configuration fields we need to update. */
 283         while (1) {
 284                 const struct pinmux_cfg_reg *cr;
 285                 unsigned int field;
 286                 u16 enum_id;
 287                 u32 value;
 288                 int in_range;
 289                 int ret;
 290
 291                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 292                 if (pos < 0)
 293                         return pos;
 294
 295                 if (!enum_id)
 296                         break;
 297
 298                 /* Check if the configuration field selects a function. If it
 299                  * doesn't, skip the field if it's not applicable to the
 300                  * requested pinmux type.
 301                  */
 302                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 303                 if (!in_range) {
 304                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 305                                 /* Functions are allowed to modify all
 306                                  * fields.
 307                                  */
 308                                 in_range = 1;
 309                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 310                                 /* Input/output types can only modify fields
 311                                  * that correspond to their respective ranges.
 312                                  */
 313                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 314
 315                                 /*
 316                                  * special case pass through for fixed
 317                                  * input-only or output-only pins without
 318                                  * function enum register association.
 319                                  */
 320                                 if (in_range && enum_id == range->force)
 321                                         continue;
 322                         }
 323                         /* GPIOs are only allowed to modify function fields. */
 324                 }
 325
 326                 if (!in_range)
 327                         continue;
 328
 329                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 330                 if (ret < 0)
 331                         return ret;
 332
 333                 sh_pfc_write_config_reg(pfc, cr, field, value);
 334         }
 335
 336         return 0;
 337 }
 338
 339 const struct sh_pfc_bias_info *
 340 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
 341                         unsigned int num, unsigned int pin)
 342 {
 343         unsigned int i;
 344
 345         for (i = 0; i < num; i++)
 346                 if (info[i].pin == pin)
 347                         return &info[i];
 348
 349         printf("Pin %u is not in bias info list\n", pin);
 350
 351         return NULL;
 352 }
 353
 354 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 355 {
 356         struct sh_pfc_pin_range *range;
 357         unsigned int nr_ranges;
 358         unsigned int i;
 359
 360         if (pfc->info->pins[0].pin == (u16)-1) {
 361                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 362                  * in its pin arrays yet. Consider the pin numbers range as
 363                  * continuous and allocate a single range.
 364                  */
 365                 pfc->nr_ranges = 1;
 366                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
 367                 if (pfc->ranges == NULL)
 368                         return -ENOMEM;
 369
 370                 pfc->ranges->start = 0;
 371                 pfc->ranges->end = pfc->info->nr_pins - 1;
 372                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 373
 374                 return 0;
 375         }
 376
 377         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 378          * be sorted by pin numbers, and pins without a GPIO port must come
 379          * last.
 380          */
 381         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 382                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 383                         nr_ranges++;
 384         }
 385
 386         pfc->nr_ranges = nr_ranges;
 387         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
 388         if (pfc->ranges == NULL)
 389                 return -ENOMEM;
 390
 391         range = pfc->ranges;
 392         range->start = pfc->info->pins[0].pin;
 393
 394         for (i = 1; i < pfc->info->nr_pins; ++i) {
 395                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 396                         continue;
 397
 398                 range->end = pfc->info->pins[i-1].pin;
 399                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 400                         pfc->nr_gpio_pins = range->end + 1;
 401
 402                 range++;
 403                 range->start = pfc->info->pins[i].pin;
 404         }
 405
 406         range->end = pfc->info->pins[i-1].pin;
 407         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 408                 pfc->nr_gpio_pins = range->end + 1;
 409
 410         return 0;
 411 }
 412
 413 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
 414 {
 415         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 416
 417         return priv->pfc.info->nr_pins;
 418 }
 419
 420 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
 421                                                   unsigned selector)
 422 {
 423         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 424
 425         return priv->pfc.info->pins[selector].name;
 426 }
 427
 428 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
 429 {
 430         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 431
 432         return priv->pfc.info->nr_groups;
 433 }
 434
 435 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
 436                                                   unsigned selector)
 437 {
 438         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 439
 440         return priv->pfc.info->groups[selector].name;
 441 }
 442
 443 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
 444 {
 445         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 446
 447         return priv->pfc.info->nr_functions;
 448 }
 449
 450 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
 451                                                   unsigned selector)
 452 {
 453         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 454
 455         return priv->pfc.info->functions[selector].name;
 456 }
 457
 458 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
 459 {
 460         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 461         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 462         struct sh_pfc *pfc = &priv->pfc;
 463         struct sh_pfc_pin_config *cfg;
 464         const struct sh_pfc_pin *pin = NULL;
 465         int i, idx;
 466
 467         for (i = 1; i < pfc->info->nr_pins; i++) {
 468                 if (priv->pfc.info->pins[i].pin != pin_selector)
 469                         continue;
 470
 471                 pin = &priv->pfc.info->pins[i];
 472                 break;
 473         }
 474
 475         if (!pin)
 476                 return -EINVAL;
 477
 478         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 479         cfg = &pmx->configs[idx];
 480
 481         if (cfg->type != PINMUX_TYPE_NONE)
 482                 return -EBUSY;
 483
 484         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
 485 }
 486
 487 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
 488                                   unsigned func_selector)
 489 {
 490         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 491         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 492         struct sh_pfc *pfc = &priv->pfc;
 493         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
 494         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
 495         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 496
 497         if (cfg->type != PINMUX_TYPE_NONE)
 498                 return -EBUSY;
 499
 500         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
 501 }
 502
 503 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
 504                                      unsigned func_selector)
 505 {
 506         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 507         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 508         struct sh_pfc *pfc = &priv->pfc;
 509         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
 510         unsigned int i;
 511         int ret = 0;
 512
 513         for (i = 0; i < grp->nr_pins; ++i) {
 514                 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
 515                 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 516
 517                 if (cfg->type != PINMUX_TYPE_NONE) {
 518                         ret = -EBUSY;
 519                         goto done;
 520                 }
 521         }
 522
 523         for (i = 0; i < grp->nr_pins; ++i) {
 524                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
 525                 if (ret < 0)
 526                         break;
 527         }
 528
 529 done:
 530         return ret;
 531 }
 532 #if CONFIG_IS_ENABLED(PINCONF)
 533 static const struct pinconf_param sh_pfc_pinconf_params[] = {
 534         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
 535         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
 536         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
 537         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
 538         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
 539 };
 540
 541 static void __iomem *
 542 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
 543                                        unsigned int *offset, unsigned int *size)
 544 {
 545         const struct pinmux_drive_reg_field *field;
 546         const struct pinmux_drive_reg *reg;
 547         unsigned int i;
 548
 549         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
 550                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
 551                         field = &reg->fields[i];
 552
 553                         if (field->size && field->pin == pin) {
 554                                 *offset = field->offset;
 555                                 *size = field->size;
 556
 557                                 return (void __iomem *)(uintptr_t)reg->reg;
 558                         }
 559                 }
 560         }
 561
 562         return NULL;
 563 }
 564
 565 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 566                                              unsigned int pin, u16 strength)
 567 {
 568         unsigned int offset;
 569         unsigned int size;
 570         unsigned int step;
 571         void __iomem *reg;
 572         void __iomem *unlock_reg =
 573                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 574         u32 val;
 575
 576         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
 577         if (!reg)
 578                 return -EINVAL;
 579
 580         step = size == 2 ? 6 : 3;
 581
 582         if (strength < step || strength > 24)
 583                 return -EINVAL;
 584
 585         /* Convert the value from mA based on a full drive strength value of
 586          * 24mA. We can make the full value configurable later if needed.
 587          */
 588         strength = strength / step - 1;
 589
 590         val = sh_pfc_read_raw_reg(reg, 32);
 591         val &= ~GENMASK(offset + size - 1, offset);
 592         val |= strength << offset;
 593
 594         if (unlock_reg)
 595                 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 596
 597         sh_pfc_write_raw_reg(reg, 32, val);
 598
 599         return 0;
 600 }
 601
 602 /* Check whether the requested parameter is supported for a pin. */
 603 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
 604                                     unsigned int param)
 605 {
 606         int idx = sh_pfc_get_pin_index(pfc, _pin);
 607         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 608
 609         switch (param) {
 610         case PIN_CONFIG_BIAS_DISABLE:
 611                 return pin->configs &
 612                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
 613
 614         case PIN_CONFIG_BIAS_PULL_UP:
 615                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 616
 617         case PIN_CONFIG_BIAS_PULL_DOWN:
 618                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 619
 620         case PIN_CONFIG_DRIVE_STRENGTH:
 621                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 622
 623         case PIN_CONFIG_POWER_SOURCE:
 624                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
 625
 626         default:
 627                 return false;
 628         }
 629 }
 630
 631 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 632                               unsigned int param, unsigned int arg)
 633 {
 634         struct sh_pfc *pfc = pmx->pfc;
 635         void __iomem *pocctrl;
 636         void __iomem *unlock_reg =
 637                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 638         u32 addr, val;
 639         int bit, ret;
 640
 641         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
 642                 return -ENOTSUPP;
 643
 644         switch (param) {
 645         case PIN_CONFIG_BIAS_PULL_UP:
 646         case PIN_CONFIG_BIAS_PULL_DOWN:
 647         case PIN_CONFIG_BIAS_DISABLE:
 648                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
 649                         return -ENOTSUPP;
 650
 651                 pfc->info->ops->set_bias(pfc, _pin, param);
 652
 653                 break;
 654
 655         case PIN_CONFIG_DRIVE_STRENGTH:
 656                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
 657                 if (ret < 0)
 658                         return ret;
 659
 660                 break;
 661
 662         case PIN_CONFIG_POWER_SOURCE:
 663                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 664                         return -ENOTSUPP;
 665
 666                 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
 667                 if (bit < 0) {
 668                         printf("invalid pin %#x", _pin);
 669                         return bit;
 670                 }
 671
 672                 if (arg != 1800 && arg != 3300)
 673                         return -EINVAL;
 674
 675                 pocctrl = (void __iomem *)(uintptr_t)addr;
 676
 677                 val = sh_pfc_read_raw_reg(pocctrl, 32);
 678                 if (arg == 3300)
 679                         val |= BIT(bit);
 680                 else
 681                         val &= ~BIT(bit);
 682
 683                 if (unlock_reg)
 684                         sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 685
 686                 sh_pfc_write_raw_reg(pocctrl, 32, val);
 687
 688                 break;
 689
 690         default:
 691                 return -ENOTSUPP;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
 698                                   unsigned int pin_selector,
 699                                   unsigned int param, unsigned int arg)
 700 {
 701         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 702         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 703         struct sh_pfc *pfc = &priv->pfc;
 704         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
 705
 706         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
 707
 708         return 0;
 709 }
 710
 711 static int sh_pfc_pinconf_group_set(struct udevice *dev,
 712                                       unsigned int group_selector,
 713                                       unsigned int param, unsigned int arg)
 714 {
 715         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 716         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 717         struct sh_pfc *pfc = &priv->pfc;
 718         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
 719         unsigned int i;
 720
 721         for (i = 0; i < grp->nr_pins; i++)
 722                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
 723
 724         return 0;
 725 }
 726 #endif
 727
 728 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 729         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
 730         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
 731         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
 732         .get_group_name         = sh_pfc_pinctrl_get_group_name,
 733         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
 734         .get_function_name      = sh_pfc_pinctrl_get_function_name,
 735
 736 #if CONFIG_IS_ENABLED(PINCONF)
 737         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
 738         .pinconf_params         = sh_pfc_pinconf_params,
 739         .pinconf_set            = sh_pfc_pinconf_pin_set,
 740         .pinconf_group_set      = sh_pfc_pinconf_group_set,
 741 #endif
 742         .pinmux_set             = sh_pfc_pinctrl_pin_set,
 743         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
 744         .set_state              = pinctrl_generic_set_state,
 745 };
 746
 747 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 748 {
 749         unsigned int i;
 750
 751         /* Allocate and initialize the pins and configs arrays. */
 752         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
 753                                     GFP_KERNEL);
 754         if (unlikely(!pmx->configs))
 755                 return -ENOMEM;
 756
 757         for (i = 0; i < pfc->info->nr_pins; ++i) {
 758                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
 759                 cfg->type = PINMUX_TYPE_NONE;
 760         }
 761
 762         return 0;
 763 }
 764
 765
 766 static int sh_pfc_pinctrl_probe(struct udevice *dev)
 767 {
 768         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 769         enum sh_pfc_model model = dev_get_driver_data(dev);
 770         fdt_addr_t base;
 771
 772         base = devfdt_get_addr(dev);
 773         if (base == FDT_ADDR_T_NONE)
 774                 return -EINVAL;
 775
 776         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
 777         if (!priv->pfc.regs)
 778                 return -ENOMEM;
 779
 780 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 781         if (model == SH_PFC_R8A7790)
 782                 priv->pfc.info = &r8a7790_pinmux_info;
 783 #endif
 784 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 785         if (model == SH_PFC_R8A7791)
 786                 priv->pfc.info = &r8a7791_pinmux_info;
 787 #endif
 788 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 789         if (model == SH_PFC_R8A7792)
 790                 priv->pfc.info = &r8a7792_pinmux_info;
 791 #endif
 792 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 793         if (model == SH_PFC_R8A7793)
 794                 priv->pfc.info = &r8a7793_pinmux_info;
 795 #endif
 796 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 797         if (model == SH_PFC_R8A7794)
 798                 priv->pfc.info = &r8a7794_pinmux_info;
 799 #endif
 800 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 801         if (model == SH_PFC_R8A7795)
 802                 priv->pfc.info = &r8a7795_pinmux_info;
 803 #endif
 804 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 805         if (model == SH_PFC_R8A7796)
 806                 priv->pfc.info = &r8a7796_pinmux_info;
 807 #endif
 808 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 809         if (model == SH_PFC_R8A77970)
 810                 priv->pfc.info = &r8a77970_pinmux_info;
 811 #endif
 812 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 813         if (model == SH_PFC_R8A77995)
 814                 priv->pfc.info = &r8a77995_pinmux_info;
 815 #endif
 816
 817         priv->pmx.pfc = &priv->pfc;
 818         sh_pfc_init_ranges(&priv->pfc);
 819         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
 820
 821         return 0;
 822 }
 823
 824 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
 825 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 826         {
 827                 .compatible = "renesas,pfc-r8a7790",
 828                 .data = SH_PFC_R8A7790,
 829         },
 830 #endif
 831 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 832         {
 833                 .compatible = "renesas,pfc-r8a7791",
 834                 .data = SH_PFC_R8A7791,
 835         },
 836 #endif
 837 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 838         {
 839                 .compatible = "renesas,pfc-r8a7792",
 840                 .data = SH_PFC_R8A7792,
 841         },
 842 #endif
 843 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 844         {
 845                 .compatible = "renesas,pfc-r8a7793",
 846                 .data = SH_PFC_R8A7793,
 847         },
 848 #endif
 849 #ifdef CONFIG_PINCTRL_PFC_R8A7794
 850         {
 851                 .compatible = "renesas,pfc-r8a7794",
 852                 .data = SH_PFC_R8A7794,
 853         },
 854 #endif
 855 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 856         {
 857                 .compatible = "renesas,pfc-r8a7795",
 858                 .data = SH_PFC_R8A7795,
 859         },
 860 #endif
 861 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 862         {
 863                 .compatible = "renesas,pfc-r8a7796",
 864                 .data = SH_PFC_R8A7796,
 865         },
 866 #endif
 867 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 868         {
 869                 .compatible = "renesas,pfc-r8a77970",
 870                 .data = SH_PFC_R8A77970,
 871         },
 872 #endif
 873 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 874         {
 875                 .compatible = "renesas,pfc-r8a77995",
 876                 .data = SH_PFC_R8A77995,
 877         },
 878 #endif
 879         { },
 880 };
 881
 882 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
 883         .name           = "sh_pfc_pinctrl",
 884         .id             = UCLASS_PINCTRL,
 885         .of_match       = sh_pfc_pinctrl_ids,
 886         .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
 887         .ops            = &sh_pfc_pinctrl_ops,
 888         .probe          = sh_pfc_pinctrl_probe,
 889 };