2 * Pin Control driver for SuperH Pin Function Controller.
4 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 * Copyright (C) 2008 Magnus Damm
7 * Copyright (C) 2009 - 2012 Paul Mundt
8 * Copyright (C) 2017 Marek Vasut
10 * SPDX-License-Identifier: GPL-2.0
13 #define DRV_NAME "sh-pfc"
18 #include <dm/pinctrl.h>
20 #include <linux/sizes.h>
24 DECLARE_GLOBAL_DATA_PTR
;
36 struct sh_pfc_pin_config
{
40 struct sh_pfc_pinctrl
{
43 struct sh_pfc_pin_config
*configs
;
45 const char *func_prop_name
;
46 const char *groups_prop_name
;
47 const char *pins_prop_name
;
50 struct sh_pfc_pin_range
{
55 struct sh_pfc_pinctrl_priv
{
57 struct sh_pfc_pinctrl pmx
;
60 int sh_pfc_get_pin_index(struct sh_pfc
*pfc
, unsigned int pin
)
65 for (i
= 0, offset
= 0; i
< pfc
->nr_ranges
; ++i
) {
66 const struct sh_pfc_pin_range
*range
= &pfc
->ranges
[i
];
68 if (pin
<= range
->end
)
69 return pin
>= range
->start
70 ? offset
+ pin
- range
->start
: -1;
72 offset
+= range
->end
- range
->start
+ 1;
78 static int sh_pfc_enum_in_range(u16 enum_id
, const struct pinmux_range
*r
)
80 if (enum_id
< r
->begin
)
89 u32
sh_pfc_read_raw_reg(void __iomem
*mapped_reg
, unsigned int reg_width
)
93 return readb(mapped_reg
);
95 return readw(mapped_reg
);
97 return readl(mapped_reg
);
104 void sh_pfc_write_raw_reg(void __iomem
*mapped_reg
, unsigned int reg_width
,
109 writeb(data
, mapped_reg
);
112 writew(data
, mapped_reg
);
115 writel(data
, mapped_reg
);
122 u32
sh_pfc_read_reg(struct sh_pfc
*pfc
, u32 reg
, unsigned int width
)
124 return sh_pfc_read_raw_reg(pfc
->regs
+ reg
, width
);
127 void sh_pfc_write_reg(struct sh_pfc
*pfc
, u32 reg
, unsigned int width
, u32 data
)
129 void __iomem
*unlock_reg
=
130 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
132 if (pfc
->info
->unlock_reg
)
133 sh_pfc_write_raw_reg(unlock_reg
, 32, ~data
);
135 sh_pfc_write_raw_reg(pfc
->regs
+ reg
, width
, data
);
138 static void sh_pfc_config_reg_helper(struct sh_pfc
*pfc
,
139 const struct pinmux_cfg_reg
*crp
,
141 void __iomem
**mapped_regp
, u32
*maskp
,
146 *mapped_regp
= (void __iomem
*)(uintptr_t)crp
->reg
;
148 if (crp
->field_width
) {
149 *maskp
= (1 << crp
->field_width
) - 1;
150 *posp
= crp
->reg_width
- ((in_pos
+ 1) * crp
->field_width
);
152 *maskp
= (1 << crp
->var_field_width
[in_pos
]) - 1;
153 *posp
= crp
->reg_width
;
154 for (k
= 0; k
<= in_pos
; k
++)
155 *posp
-= crp
->var_field_width
[k
];
159 static void sh_pfc_write_config_reg(struct sh_pfc
*pfc
,
160 const struct pinmux_cfg_reg
*crp
,
161 unsigned int field
, u32 value
)
163 void __iomem
*mapped_reg
;
164 void __iomem
*unlock_reg
=
165 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
169 sh_pfc_config_reg_helper(pfc
, crp
, field
, &mapped_reg
, &mask
, &pos
);
171 dev_dbg(pfc
->dev
, "write_reg addr = %x, value = 0x%x, field = %u, "
172 "r_width = %u, f_width = %u\n",
173 crp
->reg
, value
, field
, crp
->reg_width
, crp
->field_width
);
175 mask
= ~(mask
<< pos
);
176 value
= value
<< pos
;
178 data
= sh_pfc_read_raw_reg(mapped_reg
, crp
->reg_width
);
182 if (pfc
->info
->unlock_reg
)
183 sh_pfc_write_raw_reg(unlock_reg
, 32, ~data
);
185 sh_pfc_write_raw_reg(mapped_reg
, crp
->reg_width
, data
);
188 static int sh_pfc_get_config_reg(struct sh_pfc
*pfc
, u16 enum_id
,
189 const struct pinmux_cfg_reg
**crp
,
190 unsigned int *fieldp
, u32
*valuep
)
195 const struct pinmux_cfg_reg
*config_reg
=
196 pfc
->info
->cfg_regs
+ k
;
197 unsigned int r_width
= config_reg
->reg_width
;
198 unsigned int f_width
= config_reg
->field_width
;
199 unsigned int curr_width
;
200 unsigned int bit_pos
;
201 unsigned int pos
= 0;
207 for (bit_pos
= 0; bit_pos
< r_width
; bit_pos
+= curr_width
) {
212 curr_width
= f_width
;
214 curr_width
= config_reg
->var_field_width
[m
];
216 ncomb
= 1 << curr_width
;
217 for (n
= 0; n
< ncomb
; n
++) {
218 if (config_reg
->enum_ids
[pos
+ n
] == enum_id
) {
234 static int sh_pfc_mark_to_enum(struct sh_pfc
*pfc
, u16 mark
, int pos
,
237 const u16
*data
= pfc
->info
->pinmux_data
;
241 *enum_idp
= data
[pos
+ 1];
245 for (k
= 0; k
< pfc
->info
->pinmux_data_size
; k
++) {
246 if (data
[k
] == mark
) {
247 *enum_idp
= data
[k
+ 1];
252 dev_err(pfc
->dev
, "cannot locate data/mark enum_id for mark %d\n",
257 int sh_pfc_config_mux(struct sh_pfc
*pfc
, unsigned mark
, int pinmux_type
)
259 const struct pinmux_range
*range
;
262 switch (pinmux_type
) {
263 case PINMUX_TYPE_GPIO
:
264 case PINMUX_TYPE_FUNCTION
:
268 case PINMUX_TYPE_OUTPUT
:
269 range
= &pfc
->info
->output
;
272 case PINMUX_TYPE_INPUT
:
273 range
= &pfc
->info
->input
;
280 /* Iterate over all the configuration fields we need to update. */
282 const struct pinmux_cfg_reg
*cr
;
289 pos
= sh_pfc_mark_to_enum(pfc
, mark
, pos
, &enum_id
);
296 /* Check if the configuration field selects a function. If it
297 * doesn't, skip the field if it's not applicable to the
298 * requested pinmux type.
300 in_range
= sh_pfc_enum_in_range(enum_id
, &pfc
->info
->function
);
302 if (pinmux_type
== PINMUX_TYPE_FUNCTION
) {
303 /* Functions are allowed to modify all
307 } else if (pinmux_type
!= PINMUX_TYPE_GPIO
) {
308 /* Input/output types can only modify fields
309 * that correspond to their respective ranges.
311 in_range
= sh_pfc_enum_in_range(enum_id
, range
);
314 * special case pass through for fixed
315 * input-only or output-only pins without
316 * function enum register association.
318 if (in_range
&& enum_id
== range
->force
)
321 /* GPIOs are only allowed to modify function fields. */
327 ret
= sh_pfc_get_config_reg(pfc
, enum_id
, &cr
, &field
, &value
);
331 sh_pfc_write_config_reg(pfc
, cr
, field
, value
);
337 const struct sh_pfc_bias_info
*
338 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info
*info
,
339 unsigned int num
, unsigned int pin
)
343 for (i
= 0; i
< num
; i
++)
344 if (info
[i
].pin
== pin
)
347 printf("Pin %u is not in bias info list\n", pin
);
352 static int sh_pfc_init_ranges(struct sh_pfc
*pfc
)
354 struct sh_pfc_pin_range
*range
;
355 unsigned int nr_ranges
;
358 if (pfc
->info
->pins
[0].pin
== (u16
)-1) {
359 /* Pin number -1 denotes that the SoC doesn't report pin numbers
360 * in its pin arrays yet. Consider the pin numbers range as
361 * continuous and allocate a single range.
364 pfc
->ranges
= kzalloc(sizeof(*pfc
->ranges
), GFP_KERNEL
);
365 if (pfc
->ranges
== NULL
)
368 pfc
->ranges
->start
= 0;
369 pfc
->ranges
->end
= pfc
->info
->nr_pins
- 1;
370 pfc
->nr_gpio_pins
= pfc
->info
->nr_pins
;
375 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
376 * be sorted by pin numbers, and pins without a GPIO port must come
379 for (i
= 1, nr_ranges
= 1; i
< pfc
->info
->nr_pins
; ++i
) {
380 if (pfc
->info
->pins
[i
-1].pin
!= pfc
->info
->pins
[i
].pin
- 1)
384 pfc
->nr_ranges
= nr_ranges
;
385 pfc
->ranges
= kzalloc(sizeof(*pfc
->ranges
) * nr_ranges
, GFP_KERNEL
);
386 if (pfc
->ranges
== NULL
)
390 range
->start
= pfc
->info
->pins
[0].pin
;
392 for (i
= 1; i
< pfc
->info
->nr_pins
; ++i
) {
393 if (pfc
->info
->pins
[i
-1].pin
== pfc
->info
->pins
[i
].pin
- 1)
396 range
->end
= pfc
->info
->pins
[i
-1].pin
;
397 if (!(pfc
->info
->pins
[i
-1].configs
& SH_PFC_PIN_CFG_NO_GPIO
))
398 pfc
->nr_gpio_pins
= range
->end
+ 1;
401 range
->start
= pfc
->info
->pins
[i
].pin
;
404 range
->end
= pfc
->info
->pins
[i
-1].pin
;
405 if (!(pfc
->info
->pins
[i
-1].configs
& SH_PFC_PIN_CFG_NO_GPIO
))
406 pfc
->nr_gpio_pins
= range
->end
+ 1;
411 static int sh_pfc_pinctrl_get_pins_count(struct udevice
*dev
)
413 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
415 return priv
->pfc
.info
->nr_pins
;
418 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice
*dev
,
421 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
423 return priv
->pfc
.info
->pins
[selector
].name
;
426 static int sh_pfc_pinctrl_get_groups_count(struct udevice
*dev
)
428 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
430 return priv
->pfc
.info
->nr_groups
;
433 static const char *sh_pfc_pinctrl_get_group_name(struct udevice
*dev
,
436 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
438 return priv
->pfc
.info
->groups
[selector
].name
;
441 static int sh_pfc_pinctrl_get_functions_count(struct udevice
*dev
)
443 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
445 return priv
->pfc
.info
->nr_functions
;
448 static const char *sh_pfc_pinctrl_get_function_name(struct udevice
*dev
,
451 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
453 return priv
->pfc
.info
->functions
[selector
].name
;
456 int sh_pfc_config_mux_for_gpio(struct udevice
*dev
, unsigned pin_selector
)
458 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
459 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
460 struct sh_pfc
*pfc
= &priv
->pfc
;
461 struct sh_pfc_pin_config
*cfg
;
462 const struct sh_pfc_pin
*pin
= NULL
;
465 for (i
= 1; i
< pfc
->info
->nr_pins
; i
++) {
466 if (priv
->pfc
.info
->pins
[i
].pin
!= pin_selector
)
469 pin
= &priv
->pfc
.info
->pins
[i
];
476 idx
= sh_pfc_get_pin_index(pfc
, pin
->pin
);
477 cfg
= &pmx
->configs
[idx
];
479 if (cfg
->type
!= PINMUX_TYPE_NONE
)
482 return sh_pfc_config_mux(pfc
, pin
->enum_id
, PINMUX_TYPE_GPIO
);
485 static int sh_pfc_pinctrl_pin_set(struct udevice
*dev
, unsigned pin_selector
,
486 unsigned func_selector
)
488 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
489 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
490 struct sh_pfc
*pfc
= &priv
->pfc
;
491 const struct sh_pfc_pin
*pin
= &priv
->pfc
.info
->pins
[pin_selector
];
492 int idx
= sh_pfc_get_pin_index(pfc
, pin
->pin
);
493 struct sh_pfc_pin_config
*cfg
= &pmx
->configs
[idx
];
495 if (cfg
->type
!= PINMUX_TYPE_NONE
)
498 return sh_pfc_config_mux(pfc
, pin
->enum_id
, PINMUX_TYPE_FUNCTION
);
501 static int sh_pfc_pinctrl_group_set(struct udevice
*dev
, unsigned group_selector
,
502 unsigned func_selector
)
504 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
505 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
506 struct sh_pfc
*pfc
= &priv
->pfc
;
507 const struct sh_pfc_pin_group
*grp
= &priv
->pfc
.info
->groups
[group_selector
];
511 for (i
= 0; i
< grp
->nr_pins
; ++i
) {
512 int idx
= sh_pfc_get_pin_index(pfc
, grp
->pins
[i
]);
513 struct sh_pfc_pin_config
*cfg
= &pmx
->configs
[idx
];
515 if (cfg
->type
!= PINMUX_TYPE_NONE
) {
521 for (i
= 0; i
< grp
->nr_pins
; ++i
) {
522 ret
= sh_pfc_config_mux(pfc
, grp
->mux
[i
], PINMUX_TYPE_FUNCTION
);
530 #if CONFIG_IS_ENABLED(PINCONF)
531 static const struct pinconf_param sh_pfc_pinconf_params
[] = {
532 { "bias-disable", PIN_CONFIG_BIAS_DISABLE
, 0 },
533 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP
, 1 },
534 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN
, 1 },
535 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH
, 0 },
536 { "power-source", PIN_CONFIG_POWER_SOURCE
, 3300 },
539 static void __iomem
*
540 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc
*pfc
, unsigned int pin
,
541 unsigned int *offset
, unsigned int *size
)
543 const struct pinmux_drive_reg_field
*field
;
544 const struct pinmux_drive_reg
*reg
;
547 for (reg
= pfc
->info
->drive_regs
; reg
->reg
; ++reg
) {
548 for (i
= 0; i
< ARRAY_SIZE(reg
->fields
); ++i
) {
549 field
= ®
->fields
[i
];
551 if (field
->size
&& field
->pin
== pin
) {
552 *offset
= field
->offset
;
555 return (void __iomem
*)(uintptr_t)reg
->reg
;
563 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc
*pfc
,
564 unsigned int pin
, u16 strength
)
570 void __iomem
*unlock_reg
=
571 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
574 reg
= sh_pfc_pinconf_find_drive_strength_reg(pfc
, pin
, &offset
, &size
);
578 step
= size
== 2 ? 6 : 3;
580 if (strength
< step
|| strength
> 24)
583 /* Convert the value from mA based on a full drive strength value of
584 * 24mA. We can make the full value configurable later if needed.
586 strength
= strength
/ step
- 1;
588 val
= sh_pfc_read_raw_reg(reg
, 32);
589 val
&= ~GENMASK(offset
+ size
- 1, offset
);
590 val
|= strength
<< offset
;
593 sh_pfc_write_raw_reg(unlock_reg
, 32, ~val
);
595 sh_pfc_write_raw_reg(reg
, 32, val
);
600 /* Check whether the requested parameter is supported for a pin. */
601 static bool sh_pfc_pinconf_validate(struct sh_pfc
*pfc
, unsigned int _pin
,
604 int idx
= sh_pfc_get_pin_index(pfc
, _pin
);
605 const struct sh_pfc_pin
*pin
= &pfc
->info
->pins
[idx
];
608 case PIN_CONFIG_BIAS_DISABLE
:
609 return pin
->configs
&
610 (SH_PFC_PIN_CFG_PULL_UP
| SH_PFC_PIN_CFG_PULL_DOWN
);
612 case PIN_CONFIG_BIAS_PULL_UP
:
613 return pin
->configs
& SH_PFC_PIN_CFG_PULL_UP
;
615 case PIN_CONFIG_BIAS_PULL_DOWN
:
616 return pin
->configs
& SH_PFC_PIN_CFG_PULL_DOWN
;
618 case PIN_CONFIG_DRIVE_STRENGTH
:
619 return pin
->configs
& SH_PFC_PIN_CFG_DRIVE_STRENGTH
;
621 case PIN_CONFIG_POWER_SOURCE
:
622 return pin
->configs
& SH_PFC_PIN_CFG_IO_VOLTAGE
;
629 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl
*pmx
, unsigned _pin
,
630 unsigned int param
, unsigned int arg
)
632 struct sh_pfc
*pfc
= pmx
->pfc
;
633 void __iomem
*pocctrl
;
634 void __iomem
*unlock_reg
=
635 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
639 if (!sh_pfc_pinconf_validate(pfc
, _pin
, param
))
643 case PIN_CONFIG_BIAS_PULL_UP
:
644 case PIN_CONFIG_BIAS_PULL_DOWN
:
645 case PIN_CONFIG_BIAS_DISABLE
:
646 if (!pfc
->info
->ops
|| !pfc
->info
->ops
->set_bias
)
649 pfc
->info
->ops
->set_bias(pfc
, _pin
, param
);
653 case PIN_CONFIG_DRIVE_STRENGTH
:
654 ret
= sh_pfc_pinconf_set_drive_strength(pfc
, _pin
, arg
);
660 case PIN_CONFIG_POWER_SOURCE
:
661 if (!pfc
->info
->ops
|| !pfc
->info
->ops
->pin_to_pocctrl
)
664 bit
= pfc
->info
->ops
->pin_to_pocctrl(pfc
, _pin
, &addr
);
666 printf("invalid pin %#x", _pin
);
670 if (arg
!= 1800 && arg
!= 3300)
673 pocctrl
= (void __iomem
*)(uintptr_t)addr
;
675 val
= sh_pfc_read_raw_reg(pocctrl
, 32);
682 sh_pfc_write_raw_reg(unlock_reg
, 32, ~val
);
684 sh_pfc_write_raw_reg(pocctrl
, 32, val
);
695 static int sh_pfc_pinconf_pin_set(struct udevice
*dev
,
696 unsigned int pin_selector
,
697 unsigned int param
, unsigned int arg
)
699 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
700 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
701 struct sh_pfc
*pfc
= &priv
->pfc
;
702 const struct sh_pfc_pin
*pin
= &pfc
->info
->pins
[pin_selector
];
704 sh_pfc_pinconf_set(pmx
, pin
->pin
, param
, arg
);
709 static int sh_pfc_pinconf_group_set(struct udevice
*dev
,
710 unsigned int group_selector
,
711 unsigned int param
, unsigned int arg
)
713 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
714 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
715 struct sh_pfc
*pfc
= &priv
->pfc
;
716 const struct sh_pfc_pin_group
*grp
= &pfc
->info
->groups
[group_selector
];
719 for (i
= 0; i
< grp
->nr_pins
; i
++)
720 sh_pfc_pinconf_set(pmx
, grp
->pins
[i
], param
, arg
);
726 static struct pinctrl_ops sh_pfc_pinctrl_ops
= {
727 .get_pins_count
= sh_pfc_pinctrl_get_pins_count
,
728 .get_pin_name
= sh_pfc_pinctrl_get_pin_name
,
729 .get_groups_count
= sh_pfc_pinctrl_get_groups_count
,
730 .get_group_name
= sh_pfc_pinctrl_get_group_name
,
731 .get_functions_count
= sh_pfc_pinctrl_get_functions_count
,
732 .get_function_name
= sh_pfc_pinctrl_get_function_name
,
734 #if CONFIG_IS_ENABLED(PINCONF)
735 .pinconf_num_params
= ARRAY_SIZE(sh_pfc_pinconf_params
),
736 .pinconf_params
= sh_pfc_pinconf_params
,
737 .pinconf_set
= sh_pfc_pinconf_pin_set
,
738 .pinconf_group_set
= sh_pfc_pinconf_group_set
,
740 .pinmux_set
= sh_pfc_pinctrl_pin_set
,
741 .pinmux_group_set
= sh_pfc_pinctrl_group_set
,
742 .set_state
= pinctrl_generic_set_state
,
745 static int sh_pfc_map_pins(struct sh_pfc
*pfc
, struct sh_pfc_pinctrl
*pmx
)
749 /* Allocate and initialize the pins and configs arrays. */
750 pmx
->configs
= kzalloc(sizeof(*pmx
->configs
) * pfc
->info
->nr_pins
,
752 if (unlikely(!pmx
->configs
))
755 for (i
= 0; i
< pfc
->info
->nr_pins
; ++i
) {
756 struct sh_pfc_pin_config
*cfg
= &pmx
->configs
[i
];
757 cfg
->type
= PINMUX_TYPE_NONE
;
764 static int sh_pfc_pinctrl_probe(struct udevice
*dev
)
766 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
767 enum sh_pfc_model model
= dev_get_driver_data(dev
);
770 base
= devfdt_get_addr(dev
);
771 if (base
== FDT_ADDR_T_NONE
)
774 priv
->pfc
.regs
= devm_ioremap(dev
, base
, SZ_2K
);
778 #ifdef CONFIG_PINCTRL_PFC_R8A7790
779 if (model
== SH_PFC_R8A7790
)
780 priv
->pfc
.info
= &r8a7790_pinmux_info
;
782 #ifdef CONFIG_PINCTRL_PFC_R8A7791
783 if (model
== SH_PFC_R8A7791
)
784 priv
->pfc
.info
= &r8a7791_pinmux_info
;
786 #ifdef CONFIG_PINCTRL_PFC_R8A7793
787 if (model
== SH_PFC_R8A7793
)
788 priv
->pfc
.info
= &r8a7793_pinmux_info
;
790 #ifdef CONFIG_PINCTRL_PFC_R8A7795
791 if (model
== SH_PFC_R8A7795
)
792 priv
->pfc
.info
= &r8a7795_pinmux_info
;
794 #ifdef CONFIG_PINCTRL_PFC_R8A7796
795 if (model
== SH_PFC_R8A7796
)
796 priv
->pfc
.info
= &r8a7796_pinmux_info
;
798 #ifdef CONFIG_PINCTRL_PFC_R8A77970
799 if (model
== SH_PFC_R8A77970
)
800 priv
->pfc
.info
= &r8a77970_pinmux_info
;
802 #ifdef CONFIG_PINCTRL_PFC_R8A77995
803 if (model
== SH_PFC_R8A77995
)
804 priv
->pfc
.info
= &r8a77995_pinmux_info
;
807 priv
->pmx
.pfc
= &priv
->pfc
;
808 sh_pfc_init_ranges(&priv
->pfc
);
809 sh_pfc_map_pins(&priv
->pfc
, &priv
->pmx
);
814 static const struct udevice_id sh_pfc_pinctrl_ids
[] = {
815 #ifdef CONFIG_PINCTRL_PFC_R8A7790
817 .compatible
= "renesas,pfc-r8a7790",
818 .data
= SH_PFC_R8A7790
,
821 #ifdef CONFIG_PINCTRL_PFC_R8A7791
823 .compatible
= "renesas,pfc-r8a7791",
824 .data
= SH_PFC_R8A7791
,
827 #ifdef CONFIG_PINCTRL_PFC_R8A7793
829 .compatible
= "renesas,pfc-r8a7793",
830 .data
= SH_PFC_R8A7793
,
833 #ifdef CONFIG_PINCTRL_PFC_R8A7795
835 .compatible
= "renesas,pfc-r8a7795",
836 .data
= SH_PFC_R8A7795
,
839 #ifdef CONFIG_PINCTRL_PFC_R8A7796
841 .compatible
= "renesas,pfc-r8a7796",
842 .data
= SH_PFC_R8A7796
,
845 #ifdef CONFIG_PINCTRL_PFC_R8A77970
847 .compatible
= "renesas,pfc-r8a77970",
848 .data
= SH_PFC_R8A77970
,
851 #ifdef CONFIG_PINCTRL_PFC_R8A77995
853 .compatible
= "renesas,pfc-r8a77995",
854 .data
= SH_PFC_R8A77995
,
860 U_BOOT_DRIVER(pinctrl_sh_pfc
) = {
861 .name
= "sh_pfc_pinctrl",
862 .id
= UCLASS_PINCTRL
,
863 .of_match
= sh_pfc_pinctrl_ids
,
864 .priv_auto_alloc_size
= sizeof(struct sh_pfc_pinctrl_priv
),
865 .ops
= &sh_pfc_pinctrl_ops
,
866 .probe
= sh_pfc_pinctrl_probe
,