2 * Pinctrl driver for Rockchip 3128 SoCs
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/grf_rk3128.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/periph.h>
17 #include <dm/pinctrl.h>
19 DECLARE_GLOBAL_DATA_PTR
;
21 struct rk3128_pinctrl_priv
{
22 struct rk3128_grf
*grf
;
25 static void pinctrl_rk3128_i2c_config(struct rk3128_grf
*grf
, int i2c_id
)
29 rk_clrsetreg(&grf
->gpio0a_iomux
,
30 GPIO0A1_MASK
| GPIO0A0_MASK
,
31 GPIO0A1_I2C0_SDA
<< GPIO0A1_SHIFT
|
32 GPIO0A0_I2C0_SCL
<< GPIO0A0_SHIFT
);
36 rk_clrsetreg(&grf
->gpio0a_iomux
,
37 GPIO0A3_MASK
| GPIO0A2_MASK
,
38 GPIO0A3_I2C1_SDA
<< GPIO0A3_SHIFT
|
39 GPIO0A2_I2C1_SCL
<< GPIO0A2_SHIFT
);
42 rk_clrsetreg(&grf
->gpio2c_iomux2
,
43 GPIO2C5_MASK
| GPIO2C4_MASK
,
44 GPIO2C5_I2C2_SCL
<< GPIO2C5_SHIFT
|
45 GPIO2C4_I2C2_SDA
<< GPIO2C4_SHIFT
);
48 rk_clrsetreg(&grf
->gpio0a_iomux
,
49 GPIO0A7_MASK
| GPIO0A6_MASK
,
50 GPIO0A7_I2C3_SDA
<< GPIO0A7_SHIFT
|
51 GPIO0A6_I2C3_SCL
<< GPIO0A6_SHIFT
);
57 static void pinctrl_rk3128_sdmmc_config(struct rk3128_grf
*grf
, int mmc_id
)
61 rk_clrsetreg(&grf
->gpio1d_iomux
, 0xffff,
62 GPIO1D7_EMMC_D7
<< GPIO1D7_SHIFT
|
63 GPIO1D6_EMMC_D6
<< GPIO1D6_SHIFT
|
64 GPIO1D5_EMMC_D5
<< GPIO1D5_SHIFT
|
65 GPIO1D4_EMMC_D4
<< GPIO1D4_SHIFT
|
66 GPIO1D3_EMMC_D3
<< GPIO1D3_SHIFT
|
67 GPIO1D2_EMMC_D2
<< GPIO1D2_SHIFT
|
68 GPIO1D1_EMMC_D1
<< GPIO1D1_SHIFT
|
69 GPIO1D0_EMMC_D0
<< GPIO1D0_SHIFT
);
70 rk_clrsetreg(&grf
->gpio2a_iomux
,
71 GPIO2A5_MASK
| GPIO2A7_MASK
,
72 GPIO2A5_EMMC_PWREN
<< GPIO2A5_SHIFT
|
73 GPIO2A7_EMMC_CLKOUT
<< GPIO2A7_SHIFT
);
75 case PERIPH_ID_SDCARD
:
76 rk_clrsetreg(&grf
->gpio1c_iomux
, 0x0fff,
77 GPIO1C5_MMC0_D3
<< GPIO1C5_SHIFT
|
78 GPIO1C4_MMC0_D2
<< GPIO1C4_SHIFT
|
79 GPIO1C3_MMC0_D1
<< GPIO1C3_SHIFT
|
80 GPIO1C2_MMC0_D0
<< GPIO1C2_SHIFT
|
81 GPIO1C1_MMC0_DETN
<< GPIO1C1_SHIFT
|
82 GPIO1C0_MMC0_CLKOUT
<< GPIO1C0_SHIFT
);
87 static int rk3128_pinctrl_request(struct udevice
*dev
, int func
, int flags
)
89 struct rk3128_pinctrl_priv
*priv
= dev_get_priv(dev
);
91 debug("%s: func=%x, flags=%x\n", __func__
, func
, flags
);
97 pinctrl_rk3128_i2c_config(priv
->grf
, func
);
99 case PERIPH_ID_SDMMC0
:
100 case PERIPH_ID_SDMMC1
:
101 pinctrl_rk3128_sdmmc_config(priv
->grf
, func
);
110 static int rk3128_pinctrl_get_periph_id(struct udevice
*dev
,
111 struct udevice
*periph
)
116 ret
= fdtdec_get_int_array(gd
->fdt_blob
, dev_of_offset(periph
),
117 "interrupts", cell
, ARRAY_SIZE(cell
));
123 return PERIPH_ID_SDCARD
;
125 return PERIPH_ID_EMMC
;
127 return PERIPH_ID_UART0
;
129 return PERIPH_ID_UART1
;
131 return PERIPH_ID_UART2
;
133 return PERIPH_ID_SPI0
;
135 return PERIPH_ID_I2C0
;
137 return PERIPH_ID_I2C1
;
139 return PERIPH_ID_I2C2
;
141 return PERIPH_ID_I2C3
;
143 return PERIPH_ID_PWM0
;
148 static int rk3128_pinctrl_set_state_simple(struct udevice
*dev
,
149 struct udevice
*periph
)
153 func
= rk3128_pinctrl_get_periph_id(dev
, periph
);
156 return rk3128_pinctrl_request(dev
, func
, 0);
159 static struct pinctrl_ops rk3128_pinctrl_ops
= {
160 .set_state_simple
= rk3128_pinctrl_set_state_simple
,
161 .request
= rk3128_pinctrl_request
,
162 .get_periph_id
= rk3128_pinctrl_get_periph_id
,
165 static int rk3128_pinctrl_probe(struct udevice
*dev
)
167 struct rk3128_pinctrl_priv
*priv
= dev_get_priv(dev
);
169 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
170 debug("%s: grf=%p\n", __func__
, priv
->grf
);
174 static const struct udevice_id rk3128_pinctrl_ids
[] = {
175 { .compatible
= "rockchip,rk3128-pinctrl" },
179 U_BOOT_DRIVER(pinctrl_rk3128
) = {
180 .name
= "pinctrl_rk3128",
181 .id
= UCLASS_PINCTRL
,
182 .of_match
= rk3128_pinctrl_ids
,
183 .priv_auto_alloc_size
= sizeof(struct rk3128_pinctrl_priv
),
184 .ops
= &rk3128_pinctrl_ops
,
185 .bind
= dm_scan_fdt_dev
,
186 .probe
= rk3128_pinctrl_probe
,