2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/grf_rk322x.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/periph.h>
16 #include <dm/pinctrl.h>
18 DECLARE_GLOBAL_DATA_PTR
;
20 struct rk322x_pinctrl_priv
{
21 struct rk322x_grf
*grf
;
24 static void pinctrl_rk322x_pwm_config(struct rk322x_grf
*grf
, int pwm_id
)
26 u32 mux_con
= readl(&grf
->con_iomux
);
30 if (mux_con
& CON_IOMUX_PWM0SEL_MASK
)
31 rk_clrsetreg(&grf
->gpio3c_iomux
, GPIO3C5_MASK
,
32 GPIO3C5_PWM10
<< GPIO3C5_SHIFT
);
34 rk_clrsetreg(&grf
->gpio0d_iomux
, GPIO0D2_MASK
,
35 GPIO0D2_PWM0
<< GPIO0D2_SHIFT
);
38 if (mux_con
& CON_IOMUX_PWM1SEL_MASK
)
39 rk_clrsetreg(&grf
->gpio0d_iomux
, GPIO0D6_MASK
,
40 GPIO0D6_PWM11
<< GPIO0D6_SHIFT
);
42 rk_clrsetreg(&grf
->gpio0d_iomux
, GPIO0D3_MASK
,
43 GPIO0D3_PWM1
<< GPIO0D3_SHIFT
);
46 if (mux_con
& CON_IOMUX_PWM2SEL_MASK
)
47 rk_clrsetreg(&grf
->gpio1b_iomux
, GPIO1B4_MASK
,
48 GPIO1B4_PWM12
<< GPIO1B4_SHIFT
);
50 rk_clrsetreg(&grf
->gpio0d_iomux
, GPIO0D4_MASK
,
51 GPIO0D4_PWM2
<< GPIO0D4_SHIFT
);
54 if (mux_con
& CON_IOMUX_PWM3SEL_MASK
)
55 rk_clrsetreg(&grf
->gpio1b_iomux
, GPIO1B3_MASK
,
56 GPIO1B3_PWM13
<< GPIO1B3_SHIFT
);
58 rk_clrsetreg(&grf
->gpio3d_iomux
, GPIO3D2_MASK
,
59 GPIO3D2_PWM3
<< GPIO3D2_SHIFT
);
62 debug("pwm id = %d iomux error!\n", pwm_id
);
67 static void pinctrl_rk322x_i2c_config(struct rk322x_grf
*grf
, int i2c_id
)
71 rk_clrsetreg(&grf
->gpio0a_iomux
,
72 GPIO0A1_MASK
| GPIO0A0_MASK
,
73 GPIO0A1_I2C0_SDA
<< GPIO0A1_SHIFT
|
74 GPIO0A0_I2C0_SCL
<< GPIO0A0_SHIFT
);
78 rk_clrsetreg(&grf
->gpio0a_iomux
,
79 GPIO0A3_MASK
| GPIO0A2_MASK
,
80 GPIO0A3_I2C1_SDA
<< GPIO0A3_SHIFT
|
81 GPIO0A2_I2C1_SCL
<< GPIO0A2_SHIFT
);
84 rk_clrsetreg(&grf
->gpio2c_iomux
,
85 GPIO2C5_MASK
| GPIO2C4_MASK
,
86 GPIO2C5_I2C2_SCL
<< GPIO2C5_SHIFT
|
87 GPIO2C4_I2C2_SDA
<< GPIO2C4_SHIFT
);
90 rk_clrsetreg(&grf
->gpio0a_iomux
,
91 GPIO0A7_MASK
| GPIO0A6_MASK
,
92 GPIO0A7_I2C3_SDA
<< GPIO0A7_SHIFT
|
93 GPIO0A6_I2C3_SCL
<< GPIO0A6_SHIFT
);
99 static void pinctrl_rk322x_spi_config(struct rk322x_grf
*grf
, int cs
)
103 rk_clrsetreg(&grf
->gpio0b_iomux
, GPIO0B6_MASK
,
104 GPIO0B6_SPI_CSN0
<< GPIO0B6_SHIFT
);
107 rk_clrsetreg(&grf
->gpio1b_iomux
, GPIO1B4_MASK
,
108 GPIO1B4_SPI_CSN1
<< GPIO1B4_SHIFT
);
111 rk_clrsetreg(&grf
->gpio0b_iomux
,
112 GPIO0B1_MASK
| GPIO0B3_MASK
| GPIO0B5_MASK
,
113 GPIO0B5_SPI_RXD
<< GPIO0B5_SHIFT
|
114 GPIO0B3_SPI_TXD
<< GPIO0B3_SHIFT
|
115 GPIO0B1_SPI_CLK
<< GPIO0B1_SHIFT
);
118 static void pinctrl_rk322x_uart_config(struct rk322x_grf
*grf
, int uart_id
)
120 u32 mux_con
= readl(&grf
->con_iomux
);
123 case PERIPH_ID_UART1
:
124 if (!(mux_con
& CON_IOMUX_UART1SEL_MASK
))
125 rk_clrsetreg(&grf
->gpio1b_iomux
,
126 GPIO1B1_MASK
| GPIO1B2_MASK
,
127 GPIO1B1_UART1_SOUT
<< GPIO1B1_SHIFT
|
128 GPIO1B2_UART1_SIN
<< GPIO1B2_SHIFT
);
130 case PERIPH_ID_UART2
:
131 if (mux_con
& CON_IOMUX_UART2SEL_MASK
)
132 rk_clrsetreg(&grf
->gpio1b_iomux
,
133 GPIO1B1_MASK
| GPIO1B2_MASK
,
134 GPIO1B1_UART21_SOUT
<< GPIO1B1_SHIFT
|
135 GPIO1B2_UART21_SIN
<< GPIO1B2_SHIFT
);
137 rk_clrsetreg(&grf
->gpio1c_iomux
,
138 GPIO1C3_MASK
| GPIO1C2_MASK
,
139 GPIO1C3_UART2_SIN
<< GPIO1C3_SHIFT
|
140 GPIO1C2_UART2_SOUT
<< GPIO1C2_SHIFT
);
145 static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf
*grf
, int mmc_id
)
149 rk_clrsetreg(&grf
->gpio1d_iomux
, 0xffff,
150 GPIO1D7_EMMC_D7
<< GPIO1D7_SHIFT
|
151 GPIO1D6_EMMC_D6
<< GPIO1D6_SHIFT
|
152 GPIO1D5_EMMC_D5
<< GPIO1D5_SHIFT
|
153 GPIO1D4_EMMC_D4
<< GPIO1D4_SHIFT
|
154 GPIO1D3_EMMC_D3
<< GPIO1D3_SHIFT
|
155 GPIO1D2_EMMC_D2
<< GPIO1D2_SHIFT
|
156 GPIO1D1_EMMC_D1
<< GPIO1D1_SHIFT
|
157 GPIO1D0_EMMC_D0
<< GPIO1D0_SHIFT
);
158 rk_clrsetreg(&grf
->gpio2a_iomux
,
159 GPIO2A5_MASK
| GPIO2A7_MASK
,
160 GPIO2A5_EMMC_PWREN
<< GPIO2A5_SHIFT
|
161 GPIO2A7_EMMC_CLKOUT
<< GPIO2A7_SHIFT
);
162 rk_clrsetreg(&grf
->gpio1c_iomux
,
163 GPIO1C6_MASK
| GPIO1C7_MASK
,
164 GPIO1C6_EMMC_CMD
<< GPIO1C6_SHIFT
|
165 GPIO1C7_EMMC_RSTNOUT
<< GPIO1C6_SHIFT
);
167 case PERIPH_ID_SDCARD
:
168 rk_clrsetreg(&grf
->gpio1b_iomux
,
169 GPIO1B6_MASK
| GPIO1B7_MASK
,
170 GPIO1B6_SDMMC_PWREN
<< GPIO1B6_SHIFT
|
171 GPIO1B7_SDMMC_CMD
<< GPIO1B6_SHIFT
);
172 rk_clrsetreg(&grf
->gpio1c_iomux
, 0xfff,
173 GPIO1C5_SDMMC_D3
<< GPIO1C5_SHIFT
|
174 GPIO1C4_SDMMC_D2
<< GPIO1C4_SHIFT
|
175 GPIO1C3_SDMMC_D1
<< GPIO1C3_SHIFT
|
176 GPIO1C2_SDMMC_D0
<< GPIO1C2_SHIFT
|
177 GPIO1C1_SDMMC_DETN
<< GPIO1C1_SHIFT
|
178 GPIO1C0_SDMMC_CLKOUT
<< GPIO1C0_SHIFT
);
183 static int rk322x_pinctrl_request(struct udevice
*dev
, int func
, int flags
)
185 struct rk322x_pinctrl_priv
*priv
= dev_get_priv(dev
);
187 debug("%s: func=%x, flags=%x\n", __func__
, func
, flags
);
193 pinctrl_rk322x_pwm_config(priv
->grf
, func
);
198 pinctrl_rk322x_i2c_config(priv
->grf
, func
);
201 pinctrl_rk322x_spi_config(priv
->grf
, flags
);
203 case PERIPH_ID_UART0
:
204 case PERIPH_ID_UART1
:
205 case PERIPH_ID_UART2
:
206 pinctrl_rk322x_uart_config(priv
->grf
, func
);
208 case PERIPH_ID_SDMMC0
:
209 case PERIPH_ID_SDMMC1
:
210 pinctrl_rk322x_sdmmc_config(priv
->grf
, func
);
219 static int rk322x_pinctrl_get_periph_id(struct udevice
*dev
,
220 struct udevice
*periph
)
225 ret
= fdtdec_get_int_array(gd
->fdt_blob
, dev_of_offset(periph
),
226 "interrupts", cell
, ARRAY_SIZE(cell
));
232 return PERIPH_ID_SDCARD
;
234 return PERIPH_ID_EMMC
;
236 return PERIPH_ID_I2C0
;
238 return PERIPH_ID_I2C1
;
240 return PERIPH_ID_I2C2
;
242 return PERIPH_ID_SPI0
;
244 return PERIPH_ID_PWM0
;
246 return PERIPH_ID_UART0
;
248 return PERIPH_ID_UART1
;
250 return PERIPH_ID_UART2
;
255 static int rk322x_pinctrl_set_state_simple(struct udevice
*dev
,
256 struct udevice
*periph
)
260 func
= rk322x_pinctrl_get_periph_id(dev
, periph
);
263 return rk322x_pinctrl_request(dev
, func
, 0);
266 static struct pinctrl_ops rk322x_pinctrl_ops
= {
267 .set_state_simple
= rk322x_pinctrl_set_state_simple
,
268 .request
= rk322x_pinctrl_request
,
269 .get_periph_id
= rk322x_pinctrl_get_periph_id
,
272 static int rk322x_pinctrl_probe(struct udevice
*dev
)
274 struct rk322x_pinctrl_priv
*priv
= dev_get_priv(dev
);
276 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
277 debug("%s: grf=%p\n", __func__
, priv
->grf
);
281 static const struct udevice_id rk322x_pinctrl_ids
[] = {
282 { .compatible
= "rockchip,rk3228-pinctrl" },
286 U_BOOT_DRIVER(pinctrl_rk3228
) = {
287 .name
= "pinctrl_rk3228",
288 .id
= UCLASS_PINCTRL
,
289 .of_match
= rk322x_pinctrl_ids
,
290 .priv_auto_alloc_size
= sizeof(struct rk322x_pinctrl_priv
),
291 .ops
= &rk322x_pinctrl_ops
,
292 .bind
= dm_scan_fdt_dev
,
293 .probe
= rk322x_pinctrl_probe
,