drivers/pinctrl/rockchip/pinctrl_rk322x.c

   1 /*
   2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <syscon.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/grf_rk322x.h>
  14 #include <asm/arch/hardware.h>
  15 #include <asm/arch/periph.h>
  16 #include <dm/pinctrl.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 /* GRF_GPIO0A_IOMUX */
  21 enum {
  22         GPIO0A7_SHIFT           = 14,
  23         GPIO0A7_MASK            = 3 << GPIO0A7_SHIFT,
  24         GPIO0A7_GPIO            = 0,
  25         GPIO0A7_I2C3_SDA,
  26         GPIO0A7_HDMI_DDCSDA,
  27
  28         GPIO0A6_SHIFT           = 12,
  29         GPIO0A6_MASK            = 3 << GPIO0A6_SHIFT,
  30         GPIO0A6_GPIO            = 0,
  31         GPIO0A6_I2C3_SCL,
  32         GPIO0A6_HDMI_DDCSCL,
  33
  34         GPIO0A3_SHIFT           = 6,
  35         GPIO0A3_MASK            = 3 << GPIO0A3_SHIFT,
  36         GPIO0A3_GPIO            = 0,
  37         GPIO0A3_I2C1_SDA,
  38         GPIO0A3_SDIO_CMD,
  39
  40         GPIO0A2_SHIFT           = 4,
  41         GPIO0A2_MASK            = 3 << GPIO0A2_SHIFT,
  42         GPIO0A2_GPIO            = 0,
  43         GPIO0A2_I2C1_SCL,
  44
  45         GPIO0A1_SHIFT           = 2,
  46         GPIO0A1_MASK            = 3 << GPIO0A1_SHIFT,
  47         GPIO0A1_GPIO            = 0,
  48         GPIO0A1_I2C0_SDA,
  49
  50         GPIO0A0_SHIFT           = 0,
  51         GPIO0A0_MASK            = 3 << GPIO0A0_SHIFT,
  52         GPIO0A0_GPIO            = 0,
  53         GPIO0A0_I2C0_SCL,
  54 };
  55
  56 /* GRF_GPIO0B_IOMUX */
  57 enum {
  58         GPIO0B7_SHIFT           = 14,
  59         GPIO0B7_MASK            = 3 << GPIO0B7_SHIFT,
  60         GPIO0B7_GPIO            = 0,
  61         GPIO0B7_HDMI_HDP,
  62
  63         GPIO0B6_SHIFT           = 12,
  64         GPIO0B6_MASK            = 3 << GPIO0B6_SHIFT,
  65         GPIO0B6_GPIO            = 0,
  66         GPIO0B6_I2S_SDI,
  67         GPIO0B6_SPI_CSN0,
  68
  69         GPIO0B5_SHIFT           = 10,
  70         GPIO0B5_MASK            = 3 << GPIO0B5_SHIFT,
  71         GPIO0B5_GPIO            = 0,
  72         GPIO0B5_I2S_SDO,
  73         GPIO0B5_SPI_RXD,
  74
  75         GPIO0B3_SHIFT           = 6,
  76         GPIO0B3_MASK            = 3 << GPIO0B3_SHIFT,
  77         GPIO0B3_GPIO            = 0,
  78         GPIO0B3_I2S1_LRCKRX,
  79         GPIO0B3_SPI_TXD,
  80
  81         GPIO0B1_SHIFT           = 2,
  82         GPIO0B1_MASK            = 3 << GPIO0B1_SHIFT,
  83         GPIO0B1_GPIO            = 0,
  84         GPIO0B1_I2S_SCLK,
  85         GPIO0B1_SPI_CLK,
  86
  87         GPIO0B0_SHIFT           = 0,
  88         GPIO0B0_MASK            = 3,
  89         GPIO0B0_GPIO            = 0,
  90         GPIO0B0_I2S_MCLK,
  91 };
  92
  93 /* GRF_GPIO0C_IOMUX */
  94 enum {
  95         GPIO0C4_SHIFT           = 8,
  96         GPIO0C4_MASK            = 3 << GPIO0C4_SHIFT,
  97         GPIO0C4_GPIO            = 0,
  98         GPIO0C4_HDMI_CECSDA,
  99
 100         GPIO0C1_SHIFT           = 2,
 101         GPIO0C1_MASK            = 3 << GPIO0C1_SHIFT,
 102         GPIO0C1_GPIO            = 0,
 103         GPIO0C1_UART0_RSTN,
 104         GPIO0C1_CLK_OUT1,
 105 };
 106
 107 /* GRF_GPIO0D_IOMUX */
 108 enum {
 109         GPIO0D6_SHIFT           = 12,
 110         GPIO0D6_MASK            = 3 << GPIO0D6_SHIFT,
 111         GPIO0D6_GPIO            = 0,
 112         GPIO0D6_SDIO_PWREN,
 113         GPIO0D6_PWM11,
 114
 115         GPIO0D4_SHIFT           = 8,
 116         GPIO0D4_MASK            = 3 << GPIO0D4_SHIFT,
 117         GPIO0D4_GPIO            = 0,
 118         GPIO0D4_PWM2,
 119
 120         GPIO0D3_SHIFT           = 6,
 121         GPIO0D3_MASK            = 3 << GPIO0D3_SHIFT,
 122         GPIO0D3_GPIO            = 0,
 123         GPIO0D3_PWM1,
 124
 125         GPIO0D2_SHIFT           = 4,
 126         GPIO0D2_MASK            = 3 << GPIO0D2_SHIFT,
 127         GPIO0D2_GPIO            = 0,
 128         GPIO0D2_PWM0,
 129 };
 130
 131 /* GRF_GPIO1A_IOMUX */
 132 enum {
 133         GPIO1A7_SHIFT           = 14,
 134         GPIO1A7_MASK            = 1,
 135         GPIO1A7_GPIO            = 0,
 136         GPIO1A7_SDMMC_WRPRT,
 137 };
 138
 139 /* GRF_GPIO1B_IOMUX */
 140 enum {
 141         GPIO1B7_SHIFT           = 14,
 142         GPIO1B7_MASK            = 3 << GPIO1B7_SHIFT,
 143         GPIO1B7_GPIO            = 0,
 144         GPIO1B7_SDMMC_CMD,
 145
 146         GPIO1B6_SHIFT           = 12,
 147         GPIO1B6_MASK            = 3 << GPIO1B6_SHIFT,
 148         GPIO1B6_GPIO            = 0,
 149         GPIO1B6_SDMMC_PWREN,
 150
 151         GPIO1B4_SHIFT           = 8,
 152         GPIO1B4_MASK            = 3 << GPIO1B4_SHIFT,
 153         GPIO1B4_GPIO            = 0,
 154         GPIO1B4_SPI_CSN1,
 155         GPIO1B4_PWM12,
 156
 157         GPIO1B3_SHIFT           = 6,
 158         GPIO1B3_MASK            = 3 << GPIO1B3_SHIFT,
 159         GPIO1B3_GPIO            = 0,
 160         GPIO1B3_UART1_RSTN,
 161         GPIO1B3_PWM13,
 162
 163         GPIO1B2_SHIFT           = 4,
 164         GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
 165         GPIO1B2_GPIO            = 0,
 166         GPIO1B2_UART1_SIN,
 167         GPIO1B2_UART21_SIN,
 168
 169         GPIO1B1_SHIFT           = 2,
 170         GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
 171         GPIO1B1_GPIO            = 0,
 172         GPIO1B1_UART1_SOUT,
 173         GPIO1B1_UART21_SOUT,
 174 };
 175
 176 /* GRF_GPIO1C_IOMUX */
 177 enum {
 178         GPIO1C7_SHIFT           = 14,
 179         GPIO1C7_MASK            = 3 << GPIO1C7_SHIFT,
 180         GPIO1C7_GPIO            = 0,
 181         GPIO1C7_NAND_CS3,
 182         GPIO1C7_EMMC_RSTNOUT,
 183
 184         GPIO1C6_SHIFT           = 12,
 185         GPIO1C6_MASK            = 3 << GPIO1C6_SHIFT,
 186         GPIO1C6_GPIO            = 0,
 187         GPIO1C6_NAND_CS2,
 188         GPIO1C6_EMMC_CMD,
 189
 190         GPIO1C5_SHIFT           = 10,
 191         GPIO1C5_MASK            = 3 << GPIO1C5_SHIFT,
 192         GPIO1C5_GPIO            = 0,
 193         GPIO1C5_SDMMC_D3,
 194         GPIO1C5_JTAG_TMS,
 195
 196         GPIO1C4_SHIFT           = 8,
 197         GPIO1C4_MASK            = 3 << GPIO1C4_SHIFT,
 198         GPIO1C4_GPIO            = 0,
 199         GPIO1C4_SDMMC_D2,
 200         GPIO1C4_JTAG_TCK,
 201
 202         GPIO1C3_SHIFT           = 6,
 203         GPIO1C3_MASK            = 3 << GPIO1C3_SHIFT,
 204         GPIO1C3_GPIO            = 0,
 205         GPIO1C3_SDMMC_D1,
 206         GPIO1C3_UART2_SIN,
 207
 208         GPIO1C2_SHIFT           = 4,
 209         GPIO1C2_MASK            = 3 << GPIO1C2_SHIFT,
 210         GPIO1C2_GPIO            = 0,
 211         GPIO1C2_SDMMC_D0,
 212         GPIO1C2_UART2_SOUT,
 213
 214         GPIO1C1_SHIFT           = 2,
 215         GPIO1C1_MASK            = 3 << GPIO1C1_SHIFT,
 216         GPIO1C1_GPIO            = 0,
 217         GPIO1C1_SDMMC_DETN,
 218
 219         GPIO1C0_SHIFT           = 0,
 220         GPIO1C0_MASK            = 3 << GPIO1C0_SHIFT,
 221         GPIO1C0_GPIO            = 0,
 222         GPIO1C0_SDMMC_CLKOUT,
 223 };
 224
 225 /* GRF_GPIO1D_IOMUX */
 226 enum {
 227         GPIO1D7_SHIFT           = 14,
 228         GPIO1D7_MASK            = 3 << GPIO1D7_SHIFT,
 229         GPIO1D7_GPIO            = 0,
 230         GPIO1D7_NAND_D7,
 231         GPIO1D7_EMMC_D7,
 232
 233         GPIO1D6_SHIFT           = 12,
 234         GPIO1D6_MASK            = 3 << GPIO1D6_SHIFT,
 235         GPIO1D6_GPIO            = 0,
 236         GPIO1D6_NAND_D6,
 237         GPIO1D6_EMMC_D6,
 238
 239         GPIO1D5_SHIFT           = 10,
 240         GPIO1D5_MASK            = 3 << GPIO1D5_SHIFT,
 241         GPIO1D5_GPIO            = 0,
 242         GPIO1D5_NAND_D5,
 243         GPIO1D5_EMMC_D5,
 244
 245         GPIO1D4_SHIFT           = 8,
 246         GPIO1D4_MASK            = 3 << GPIO1D4_SHIFT,
 247         GPIO1D4_GPIO            = 0,
 248         GPIO1D4_NAND_D4,
 249         GPIO1D4_EMMC_D4,
 250
 251         GPIO1D3_SHIFT           = 6,
 252         GPIO1D3_MASK            = 3 << GPIO1D3_SHIFT,
 253         GPIO1D3_GPIO            = 0,
 254         GPIO1D3_NAND_D3,
 255         GPIO1D3_EMMC_D3,
 256
 257         GPIO1D2_SHIFT           = 4,
 258         GPIO1D2_MASK            = 3 << GPIO1D2_SHIFT,
 259         GPIO1D2_GPIO            = 0,
 260         GPIO1D2_NAND_D2,
 261         GPIO1D2_EMMC_D2,
 262
 263         GPIO1D1_SHIFT           = 2,
 264         GPIO1D1_MASK            = 3 << GPIO1D1_SHIFT,
 265         GPIO1D1_GPIO            = 0,
 266         GPIO1D1_NAND_D1,
 267         GPIO1D1_EMMC_D1,
 268
 269         GPIO1D0_SHIFT           = 0,
 270         GPIO1D0_MASK            = 3 << GPIO1D0_SHIFT,
 271         GPIO1D0_GPIO            = 0,
 272         GPIO1D0_NAND_D0,
 273         GPIO1D0_EMMC_D0,
 274 };
 275
 276 /* GRF_GPIO2A_IOMUX */
 277 enum {
 278         GPIO2A7_SHIFT           = 14,
 279         GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
 280         GPIO2A7_GPIO            = 0,
 281         GPIO2A7_NAND_DQS,
 282         GPIO2A7_EMMC_CLKOUT,
 283
 284         GPIO2A5_SHIFT           = 10,
 285         GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
 286         GPIO2A5_GPIO            = 0,
 287         GPIO2A5_NAND_WP,
 288         GPIO2A5_EMMC_PWREN,
 289
 290         GPIO2A4_SHIFT           = 8,
 291         GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
 292         GPIO2A4_GPIO            = 0,
 293         GPIO2A4_NAND_RDY,
 294         GPIO2A4_EMMC_CMD,
 295
 296         GPIO2A3_SHIFT           = 6,
 297         GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
 298         GPIO2A3_GPIO            = 0,
 299         GPIO2A3_NAND_RDN,
 300         GPIO2A4_SPI1_CSN1,
 301
 302         GPIO2A2_SHIFT           = 4,
 303         GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
 304         GPIO2A2_GPIO            = 0,
 305         GPIO2A2_NAND_WRN,
 306         GPIO2A4_SPI1_CSN0,
 307
 308         GPIO2A1_SHIFT           = 2,
 309         GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
 310         GPIO2A1_GPIO            = 0,
 311         GPIO2A1_NAND_CLE,
 312         GPIO2A1_SPI1_TXD,
 313
 314         GPIO2A0_SHIFT           = 0,
 315         GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
 316         GPIO2A0_GPIO            = 0,
 317         GPIO2A0_NAND_ALE,
 318         GPIO2A0_SPI1_RXD,
 319 };
 320
 321 /* GRF_GPIO2B_IOMUX */
 322 enum {
 323         GPIO2B7_SHIFT           = 14,
 324         GPIO2B7_MASK            = 3 << GPIO2B7_SHIFT,
 325         GPIO2B7_GPIO            = 0,
 326         GPIO2B7_GMAC_RXER,
 327
 328         GPIO2B6_SHIFT           = 12,
 329         GPIO2B6_MASK            = 3 << GPIO2B6_SHIFT,
 330         GPIO2B6_GPIO            = 0,
 331         GPIO2B6_GMAC_CLK,
 332         GPIO2B6_MAC_LINK,
 333
 334         GPIO2B5_SHIFT           = 10,
 335         GPIO2B5_MASK            = 3 << GPIO2B5_SHIFT,
 336         GPIO2B5_GPIO            = 0,
 337         GPIO2B5_GMAC_TXEN,
 338
 339         GPIO2B4_SHIFT           = 8,
 340         GPIO2B4_MASK            = 3 << GPIO2B4_SHIFT,
 341         GPIO2B4_GPIO            = 0,
 342         GPIO2B4_GMAC_MDIO,
 343
 344         GPIO2B3_SHIFT           = 6,
 345         GPIO2B3_MASK            = 3 << GPIO2B3_SHIFT,
 346         GPIO2B3_GPIO            = 0,
 347         GPIO2B3_GMAC_RXCLK,
 348
 349         GPIO2B2_SHIFT           = 4,
 350         GPIO2B2_MASK            = 3 << GPIO2B2_SHIFT,
 351         GPIO2B2_GPIO            = 0,
 352         GPIO2B2_GMAC_CRS,
 353
 354         GPIO2B1_SHIFT           = 2,
 355         GPIO2B1_MASK            = 3 << GPIO2B1_SHIFT,
 356         GPIO2B1_GPIO            = 0,
 357         GPIO2B1_GMAC_TXCLK,
 358
 359         GPIO2B0_SHIFT           = 0,
 360         GPIO2B0_MASK            = 3 << GPIO2B0_SHIFT,
 361         GPIO2B0_GPIO            = 0,
 362         GPIO2B0_GMAC_RXDV,
 363         GPIO2B0_MAC_SPEED_IOUT,
 364 };
 365
 366 /* GRF_GPIO2C_IOMUX */
 367 enum {
 368         GPIO2C7_SHIFT           = 14,
 369         GPIO2C7_MASK            = 3 << GPIO2C7_SHIFT,
 370         GPIO2C7_GPIO            = 0,
 371         GPIO2C7_GMAC_TXD3,
 372
 373         GPIO2C6_SHIFT           = 12,
 374         GPIO2C6_MASK            = 3 << GPIO2C6_SHIFT,
 375         GPIO2C6_GPIO            = 0,
 376         GPIO2C6_GMAC_TXD2,
 377
 378         GPIO2C5_SHIFT           = 10,
 379         GPIO2C5_MASK            = 3 << GPIO2C5_SHIFT,
 380         GPIO2C5_GPIO            = 0,
 381         GPIO2C5_I2C2_SCL,
 382         GPIO2C5_GMAC_RXD2,
 383
 384         GPIO2C4_SHIFT           = 8,
 385         GPIO2C4_MASK            = 3 << GPIO2C4_SHIFT,
 386         GPIO2C4_GPIO            = 0,
 387         GPIO2C4_I2C2_SDA,
 388         GPIO2C4_GMAC_RXD3,
 389
 390         GPIO2C3_SHIFT           = 6,
 391         GPIO2C3_MASK            = 3 << GPIO2C3_SHIFT,
 392         GPIO2C3_GPIO            = 0,
 393         GPIO2C3_GMAC_TXD0,
 394
 395         GPIO2C2_SHIFT           = 4,
 396         GPIO2C2_MASK            = 3 << GPIO2C2_SHIFT,
 397         GPIO2C2_GPIO            = 0,
 398         GPIO2C2_GMAC_TXD1,
 399
 400         GPIO2C1_SHIFT           = 2,
 401         GPIO2C1_MASK            = 3 << GPIO2C1_SHIFT,
 402         GPIO2C1_GPIO            = 0,
 403         GPIO2C1_GMAC_RXD0,
 404
 405         GPIO2C0_SHIFT           = 0,
 406         GPIO2C0_MASK            = 3 << GPIO2C0_SHIFT,
 407         GPIO2C0_GPIO            = 0,
 408         GPIO2C0_GMAC_RXD1,
 409 };
 410
 411 /* GRF_GPIO2D_IOMUX */
 412 enum {
 413         GPIO2D1_SHIFT           = 2,
 414         GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
 415         GPIO2D1_GPIO            = 0,
 416         GPIO2D1_GMAC_MDC,
 417
 418         GPIO2D0_SHIFT           = 0,
 419         GPIO2D0_MASK            = 3,
 420         GPIO2D0_GPIO            = 0,
 421         GPIO2D0_GMAC_COL,
 422 };
 423
 424 /* GRF_GPIO3C_IOMUX */
 425 enum {
 426         GPIO3C6_SHIFT           = 12,
 427         GPIO3C6_MASK            = 3 << GPIO3C6_SHIFT,
 428         GPIO3C6_GPIO            = 0,
 429         GPIO3C6_DRV_VBUS1,
 430
 431         GPIO3C5_SHIFT           = 10,
 432         GPIO3C5_MASK            = 3 << GPIO3C5_SHIFT,
 433         GPIO3C5_GPIO            = 0,
 434         GPIO3C5_PWM10,
 435
 436         GPIO3C1_SHIFT           = 2,
 437         GPIO3C1_MASK            = 3 << GPIO3C1_SHIFT,
 438         GPIO3C1_GPIO            = 0,
 439         GPIO3C1_DRV_VBUS,
 440 };
 441
 442 /* GRF_GPIO3D_IOMUX */
 443 enum {
 444         GPIO3D2_SHIFT   = 4,
 445         GPIO3D2_MASK    = 3 << GPIO3D2_SHIFT,
 446         GPIO3D2_GPIO    = 0,
 447         GPIO3D2_PWM3,
 448 };
 449
 450 /* GRF_CON_IOMUX */
 451 enum {
 452         CON_IOMUX_GMACSEL_SHIFT = 15,
 453         CON_IOMUX_GMACSEL_MASK  = 1 << CON_IOMUX_GMACSEL_SHIFT,
 454         CON_IOMUX_GMACSEL_1     = 1,
 455         CON_IOMUX_UART1SEL_SHIFT        = 11,
 456         CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
 457         CON_IOMUX_UART2SEL_SHIFT        = 8,
 458         CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
 459         CON_IOMUX_UART2SEL_2    = 0,
 460         CON_IOMUX_UART2SEL_21,
 461         CON_IOMUX_EMMCSEL_SHIFT = 7,
 462         CON_IOMUX_EMMCSEL_MASK  = 1 << CON_IOMUX_EMMCSEL_SHIFT,
 463         CON_IOMUX_PWM3SEL_SHIFT = 3,
 464         CON_IOMUX_PWM3SEL_MASK  = 1 << CON_IOMUX_PWM3SEL_SHIFT,
 465         CON_IOMUX_PWM2SEL_SHIFT = 2,
 466         CON_IOMUX_PWM2SEL_MASK  = 1 << CON_IOMUX_PWM2SEL_SHIFT,
 467         CON_IOMUX_PWM1SEL_SHIFT = 1,
 468         CON_IOMUX_PWM1SEL_MASK  = 1 << CON_IOMUX_PWM1SEL_SHIFT,
 469         CON_IOMUX_PWM0SEL_SHIFT = 0,
 470         CON_IOMUX_PWM0SEL_MASK  = 1 << CON_IOMUX_PWM0SEL_SHIFT,
 471 };
 472
 473 struct rk322x_pinctrl_priv {
 474         struct rk322x_grf *grf;
 475 };
 476
 477 static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
 478 {
 479         u32 mux_con = readl(&grf->con_iomux);
 480
 481         switch (pwm_id) {
 482         case PERIPH_ID_PWM0:
 483                 if (mux_con & CON_IOMUX_PWM0SEL_MASK)
 484                         rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
 485                                      GPIO3C5_PWM10 << GPIO3C5_SHIFT);
 486                 else
 487                         rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
 488                                      GPIO0D2_PWM0 << GPIO0D2_SHIFT);
 489                 break;
 490         case PERIPH_ID_PWM1:
 491                 if (mux_con & CON_IOMUX_PWM1SEL_MASK)
 492                         rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
 493                                      GPIO0D6_PWM11 << GPIO0D6_SHIFT);
 494                 else
 495                         rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
 496                                      GPIO0D3_PWM1 << GPIO0D3_SHIFT);
 497                 break;
 498         case PERIPH_ID_PWM2:
 499                 if (mux_con & CON_IOMUX_PWM2SEL_MASK)
 500                         rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
 501                                      GPIO1B4_PWM12 << GPIO1B4_SHIFT);
 502                 else
 503                         rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
 504                                      GPIO0D4_PWM2 << GPIO0D4_SHIFT);
 505                 break;
 506         case PERIPH_ID_PWM3:
 507                 if (mux_con & CON_IOMUX_PWM3SEL_MASK)
 508                         rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
 509                                      GPIO1B3_PWM13 << GPIO1B3_SHIFT);
 510                 else
 511                         rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
 512                                      GPIO3D2_PWM3 << GPIO3D2_SHIFT);
 513                 break;
 514         default:
 515                 debug("pwm id = %d iomux error!\n", pwm_id);
 516                 break;
 517         }
 518 }
 519
 520 static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
 521 {
 522         switch (i2c_id) {
 523         case PERIPH_ID_I2C0:
 524                 rk_clrsetreg(&grf->gpio0a_iomux,
 525                              GPIO0A1_MASK | GPIO0A0_MASK,
 526                              GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
 527                              GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
 528
 529                 break;
 530         case PERIPH_ID_I2C1:
 531                 rk_clrsetreg(&grf->gpio0a_iomux,
 532                              GPIO0A3_MASK | GPIO0A2_MASK,
 533                              GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
 534                              GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
 535                 break;
 536         case PERIPH_ID_I2C2:
 537                 rk_clrsetreg(&grf->gpio2c_iomux,
 538                              GPIO2C5_MASK | GPIO2C4_MASK,
 539                              GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
 540                              GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
 541                 break;
 542         case PERIPH_ID_I2C3:
 543                 rk_clrsetreg(&grf->gpio0a_iomux,
 544                              GPIO0A7_MASK | GPIO0A6_MASK,
 545                              GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
 546                              GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
 547
 548                 break;
 549         }
 550 }
 551
 552 static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
 553 {
 554         switch (cs) {
 555         case 0:
 556                 rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
 557                              GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
 558                 break;
 559         case 1:
 560                 rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
 561                              GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
 562                 break;
 563         }
 564         rk_clrsetreg(&grf->gpio0b_iomux,
 565                      GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
 566                      GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
 567                      GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
 568                      GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
 569 }
 570
 571 static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
 572 {
 573         u32 mux_con = readl(&grf->con_iomux);
 574
 575         switch (uart_id) {
 576         case PERIPH_ID_UART1:
 577                 if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
 578                         rk_clrsetreg(&grf->gpio1b_iomux,
 579                                      GPIO1B1_MASK | GPIO1B2_MASK,
 580                                      GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
 581                                      GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
 582                 break;
 583         case PERIPH_ID_UART2:
 584                 if (mux_con & CON_IOMUX_UART2SEL_MASK)
 585                         rk_clrsetreg(&grf->gpio1b_iomux,
 586                                      GPIO1B1_MASK | GPIO1B2_MASK,
 587                                      GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
 588                                      GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
 589                 else
 590                         rk_clrsetreg(&grf->gpio1c_iomux,
 591                                      GPIO1C3_MASK | GPIO1C2_MASK,
 592                                      GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
 593                                      GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
 594                 break;
 595         }
 596 }
 597
 598 static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
 599 {
 600         switch (mmc_id) {
 601         case PERIPH_ID_EMMC:
 602                 rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
 603                              GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
 604                              GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
 605                              GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
 606                              GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
 607                              GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
 608                              GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
 609                              GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
 610                              GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
 611                 rk_clrsetreg(&grf->gpio2a_iomux,
 612                              GPIO2A5_MASK | GPIO2A7_MASK,
 613                              GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
 614                              GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
 615                 rk_clrsetreg(&grf->gpio1c_iomux,
 616                              GPIO1C6_MASK | GPIO1C7_MASK,
 617                              GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
 618                              GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
 619                 break;
 620         case PERIPH_ID_SDCARD:
 621                 rk_clrsetreg(&grf->gpio1b_iomux,
 622                              GPIO1B6_MASK | GPIO1B7_MASK,
 623                              GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
 624                              GPIO1B7_SDMMC_CMD << GPIO1B7_SHIFT);
 625                 rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
 626                              GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
 627                              GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
 628                              GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
 629                              GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
 630                              GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
 631                              GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
 632                 break;
 633         }
 634 }
 635
 636 static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
 637 {
 638         struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
 639
 640         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 641         switch (func) {
 642         case PERIPH_ID_PWM0:
 643         case PERIPH_ID_PWM1:
 644         case PERIPH_ID_PWM2:
 645         case PERIPH_ID_PWM3:
 646                 pinctrl_rk322x_pwm_config(priv->grf, func);
 647                 break;
 648         case PERIPH_ID_I2C0:
 649         case PERIPH_ID_I2C1:
 650         case PERIPH_ID_I2C2:
 651                 pinctrl_rk322x_i2c_config(priv->grf, func);
 652                 break;
 653         case PERIPH_ID_SPI0:
 654                 pinctrl_rk322x_spi_config(priv->grf, flags);
 655                 break;
 656         case PERIPH_ID_UART0:
 657         case PERIPH_ID_UART1:
 658         case PERIPH_ID_UART2:
 659                 pinctrl_rk322x_uart_config(priv->grf, func);
 660                 break;
 661         case PERIPH_ID_SDMMC0:
 662         case PERIPH_ID_SDMMC1:
 663                 pinctrl_rk322x_sdmmc_config(priv->grf, func);
 664                 break;
 665         default:
 666                 return -EINVAL;
 667         }
 668
 669         return 0;
 670 }
 671
 672 static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
 673                                         struct udevice *periph)
 674 {
 675         u32 cell[3];
 676         int ret;
 677
 678         ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
 679                                    "interrupts", cell, ARRAY_SIZE(cell));
 680         if (ret < 0)
 681                 return -EINVAL;
 682
 683         switch (cell[1]) {
 684         case 12:
 685                 return PERIPH_ID_SDCARD;
 686         case 14:
 687                 return PERIPH_ID_EMMC;
 688         case 36:
 689                 return PERIPH_ID_I2C0;
 690         case 37:
 691                 return PERIPH_ID_I2C1;
 692         case 38:
 693                 return PERIPH_ID_I2C2;
 694         case 49:
 695                 return PERIPH_ID_SPI0;
 696         case 50:
 697                 return PERIPH_ID_PWM0;
 698         case 55:
 699                 return PERIPH_ID_UART0;
 700         case 56:
 701                 return PERIPH_ID_UART1;
 702         case 57:
 703                 return PERIPH_ID_UART2;
 704         }
 705         return -ENOENT;
 706 }
 707
 708 static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
 709                                            struct udevice *periph)
 710 {
 711         int func;
 712
 713         func = rk322x_pinctrl_get_periph_id(dev, periph);
 714         if (func < 0)
 715                 return func;
 716         return rk322x_pinctrl_request(dev, func, 0);
 717 }
 718
 719 static struct pinctrl_ops rk322x_pinctrl_ops = {
 720         .set_state_simple       = rk322x_pinctrl_set_state_simple,
 721         .request        = rk322x_pinctrl_request,
 722         .get_periph_id  = rk322x_pinctrl_get_periph_id,
 723 };
 724
 725 static int rk322x_pinctrl_probe(struct udevice *dev)
 726 {
 727         struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
 728
 729         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 730         debug("%s: grf=%p\n", __func__, priv->grf);
 731         return 0;
 732 }
 733
 734 static const struct udevice_id rk322x_pinctrl_ids[] = {
 735         { .compatible = "rockchip,rk3228-pinctrl" },
 736         { }
 737 };
 738
 739 U_BOOT_DRIVER(pinctrl_rk3228) = {
 740         .name           = "pinctrl_rk3228",
 741         .id             = UCLASS_PINCTRL,
 742         .of_match       = rk322x_pinctrl_ids,
 743         .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
 744         .ops            = &rk322x_pinctrl_ops,
 745         .bind           = dm_scan_fdt_dev,
 746         .probe          = rk322x_pinctrl_probe,
 747 };