drivers/pinctrl/rockchip/pinctrl_rk3399.c

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <syscon.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/grf_rk3399.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/periph.h>
  15 #include <asm/arch/clock.h>
  16 #include <dm/pinctrl.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 struct rk3399_pinctrl_priv {
  21         struct rk3399_grf_regs *grf;
  22         struct rk3399_pmugrf_regs *pmugrf;
  23 };
  24
  25 enum {
  26         /* GRF_GPIO2B_IOMUX */
  27         GRF_GPIO2B1_SEL_SHIFT   = 0,
  28         GRF_GPIO2B1_SEL_MASK    = 3 << GRF_GPIO2B1_SEL_SHIFT,
  29         GRF_SPI2TPM_RXD         = 1,
  30         GRF_GPIO2B2_SEL_SHIFT   = 2,
  31         GRF_GPIO2B2_SEL_MASK    = 3 << GRF_GPIO2B2_SEL_SHIFT,
  32         GRF_SPI2TPM_TXD         = 1,
  33         GRF_GPIO2B3_SEL_SHIFT   = 6,
  34         GRF_GPIO2B3_SEL_MASK    = 3 << GRF_GPIO2B3_SEL_SHIFT,
  35         GRF_SPI2TPM_CLK         = 1,
  36         GRF_GPIO2B4_SEL_SHIFT   = 8,
  37         GRF_GPIO2B4_SEL_MASK    = 3 << GRF_GPIO2B4_SEL_SHIFT,
  38         GRF_SPI2TPM_CSN0        = 1,
  39
  40         /* GRF_GPIO3A_IOMUX */
  41         GRF_GPIO3A4_SEL_SHIFT   = 8,
  42         GRF_GPIO3A4_SEL_MASK    = 3 << GRF_GPIO3A4_SEL_SHIFT,
  43         GRF_SPI0NORCODEC_RXD    = 2,
  44         GRF_GPIO3A5_SEL_SHIFT   = 10,
  45         GRF_GPIO3A5_SEL_MASK    = 3 << GRF_GPIO3A5_SEL_SHIFT,
  46         GRF_SPI0NORCODEC_TXD    = 2,
  47         GRF_GPIO3A6_SEL_SHIFT   = 12,
  48         GRF_GPIO3A6_SEL_MASK    = 3 << GRF_GPIO3A6_SEL_SHIFT,
  49         GRF_SPI0NORCODEC_CLK    = 2,
  50         GRF_GPIO3A7_SEL_SHIFT   = 14,
  51         GRF_GPIO3A7_SEL_MASK    = 3 << GRF_GPIO3A7_SEL_SHIFT,
  52         GRF_SPI0NORCODEC_CSN0   = 2,
  53
  54         /* GRF_GPIO3B_IOMUX */
  55         GRF_GPIO3B0_SEL_SHIFT   = 0,
  56         GRF_GPIO3B0_SEL_MASK    = 3 << GRF_GPIO3B0_SEL_SHIFT,
  57         GRF_SPI0NORCODEC_CSN1   = 2,
  58
  59         /* GRF_GPIO4B_IOMUX */
  60         GRF_GPIO4B0_SEL_SHIFT   = 0,
  61         GRF_GPIO4B0_SEL_MASK    = 3 << GRF_GPIO4B0_SEL_SHIFT,
  62         GRF_SDMMC_DATA0         = 1,
  63         GRF_UART2DBGA_SIN       = 2,
  64         GRF_GPIO4B1_SEL_SHIFT   = 2,
  65         GRF_GPIO4B1_SEL_MASK    = 3 << GRF_GPIO4B1_SEL_SHIFT,
  66         GRF_SDMMC_DATA1         = 1,
  67         GRF_UART2DBGA_SOUT      = 2,
  68         GRF_GPIO4B2_SEL_SHIFT   = 4,
  69         GRF_GPIO4B2_SEL_MASK    = 3 << GRF_GPIO4B2_SEL_SHIFT,
  70         GRF_SDMMC_DATA2         = 1,
  71         GRF_GPIO4B3_SEL_SHIFT   = 6,
  72         GRF_GPIO4B3_SEL_MASK    = 3 << GRF_GPIO4B3_SEL_SHIFT,
  73         GRF_SDMMC_DATA3         = 1,
  74         GRF_GPIO4B4_SEL_SHIFT   = 8,
  75         GRF_GPIO4B4_SEL_MASK    = 3 << GRF_GPIO4B4_SEL_SHIFT,
  76         GRF_SDMMC_CLKOUT        = 1,
  77         GRF_GPIO4B5_SEL_SHIFT   = 10,
  78         GRF_GPIO4B5_SEL_MASK    = 3 << GRF_GPIO4B5_SEL_SHIFT,
  79         GRF_SDMMC_CMD           = 1,
  80
  81         /* GRF_GPIO4C_IOMUX */
  82         GRF_GPIO4C2_SEL_SHIFT   = 4,
  83         GRF_GPIO4C2_SEL_MASK    = 3 << GRF_GPIO4C2_SEL_SHIFT,
  84         GRF_PWM_0               = 1,
  85         GRF_GPIO4C3_SEL_SHIFT   = 6,
  86         GRF_GPIO4C3_SEL_MASK    = 3 << GRF_GPIO4C3_SEL_SHIFT,
  87         GRF_UART2DGBC_SIN       = 1,
  88         GRF_GPIO4C4_SEL_SHIFT   = 8,
  89         GRF_GPIO4C4_SEL_MASK    = 3 << GRF_GPIO4C4_SEL_SHIFT,
  90         GRF_UART2DBGC_SOUT      = 1,
  91         GRF_GPIO4C6_SEL_SHIFT   = 12,
  92         GRF_GPIO4C6_SEL_MASK    = 3 << GRF_GPIO4C6_SEL_SHIFT,
  93         GRF_PWM_1               = 1,
  94
  95         /* PMUGRF_GPIO0A_IOMUX */
  96         PMUGRF_GPIO0A6_SEL_SHIFT        = 12,
  97         PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
  98         PMUGRF_PWM_3A           = 1,
  99
 100         /* PMUGRF_GPIO1A_IOMUX */
 101         PMUGRF_GPIO1A7_SEL_SHIFT        = 14,
 102         PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
 103         PMUGRF_SPI1EC_RXD       = 2,
 104
 105         /* PMUGRF_GPIO1B_IOMUX */
 106         PMUGRF_GPIO1B0_SEL_SHIFT        = 0,
 107         PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
 108         PMUGRF_SPI1EC_TXD       = 2,
 109         PMUGRF_GPIO1B1_SEL_SHIFT        = 2,
 110         PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
 111         PMUGRF_SPI1EC_CLK       = 2,
 112         PMUGRF_GPIO1B2_SEL_SHIFT        = 4,
 113         PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
 114         PMUGRF_SPI1EC_CSN0      = 2,
 115         PMUGRF_GPIO1B6_SEL_SHIFT        = 12,
 116         PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
 117         PMUGRF_PWM_3B           = 1,
 118         PMUGRF_GPIO1B7_SEL_SHIFT        = 14,
 119         PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
 120         PMUGRF_I2C0PMU_SDA      = 2,
 121
 122         /* PMUGRF_GPIO1C_IOMUX */
 123         PMUGRF_GPIO1C0_SEL_SHIFT        = 0,
 124         PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
 125         PMUGRF_I2C0PMU_SCL      = 2,
 126         PMUGRF_GPIO1C3_SEL_SHIFT        = 6,
 127         PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
 128         PMUGRF_PWM_2            = 1,
 129
 130 };
 131 static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
 132                 struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
 133 {
 134         switch (pwm_id) {
 135         case PERIPH_ID_PWM0:
 136                 rk_clrsetreg(&grf->gpio4c_iomux,
 137                              GRF_GPIO4C2_SEL_MASK,
 138                              GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
 139                 break;
 140         case PERIPH_ID_PWM1:
 141                 rk_clrsetreg(&grf->gpio4c_iomux,
 142                              GRF_GPIO4C6_SEL_MASK,
 143                              GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
 144                 break;
 145         case PERIPH_ID_PWM2:
 146                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
 147                              PMUGRF_GPIO1C3_SEL_MASK,
 148                              PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
 149                 break;
 150         case PERIPH_ID_PWM3:
 151                 if (readl(&pmugrf->soc_con0) & (1 << 5))
 152                         rk_clrsetreg(&pmugrf->gpio1b_iomux,
 153                                      PMUGRF_GPIO1B6_SEL_MASK,
 154                                      PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
 155                 else
 156                         rk_clrsetreg(&pmugrf->gpio0a_iomux,
 157                                      PMUGRF_GPIO0A6_SEL_MASK,
 158                                      PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
 159                 break;
 160         default:
 161                 debug("pwm id = %d iomux error!\n", pwm_id);
 162                 break;
 163         }
 164 }
 165
 166 static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
 167                                       struct rk3399_pmugrf_regs *pmugrf,
 168                                       int i2c_id)
 169 {
 170         switch (i2c_id) {
 171         case PERIPH_ID_I2C0:
 172                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 173                              PMUGRF_GPIO1B7_SEL_MASK,
 174                              PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
 175                 rk_clrsetreg(&pmugrf->gpio1c_iomux,
 176                              PMUGRF_GPIO1C0_SEL_MASK,
 177                              PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
 178                 break;
 179         case PERIPH_ID_I2C1:
 180         case PERIPH_ID_I2C2:
 181         case PERIPH_ID_I2C3:
 182         case PERIPH_ID_I2C4:
 183         case PERIPH_ID_I2C5:
 184         default:
 185                 debug("i2c id = %d iomux error!\n", i2c_id);
 186                 break;
 187         }
 188 }
 189
 190 static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
 191 {
 192         switch (lcd_id) {
 193         case PERIPH_ID_LCDC0:
 194                 break;
 195         default:
 196                 debug("lcdc id = %d iomux error!\n", lcd_id);
 197                 break;
 198         }
 199 }
 200
 201 static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
 202                                      struct rk3399_pmugrf_regs *pmugrf,
 203                                      enum periph_id spi_id, int cs)
 204 {
 205         switch (spi_id) {
 206         case PERIPH_ID_SPI0:
 207                 switch (cs) {
 208                 case 0:
 209                         rk_clrsetreg(&grf->gpio3a_iomux,
 210                                      GRF_GPIO3A7_SEL_MASK,
 211                                      GRF_SPI0NORCODEC_CSN0
 212                                      << GRF_GPIO3A7_SEL_SHIFT);
 213                         break;
 214                 case 1:
 215                         rk_clrsetreg(&grf->gpio3b_iomux,
 216                                      GRF_GPIO3B0_SEL_MASK,
 217                                      GRF_SPI0NORCODEC_CSN1
 218                                      << GRF_GPIO3B0_SEL_SHIFT);
 219                         break;
 220                 default:
 221                         goto err;
 222                 }
 223                 rk_clrsetreg(&grf->gpio3a_iomux,
 224                              GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
 225                              | GRF_GPIO3A6_SEL_SHIFT,
 226                              GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
 227                              | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
 228                              | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
 229                 break;
 230         case PERIPH_ID_SPI1:
 231                 if (cs != 0)
 232                         goto err;
 233                 rk_clrsetreg(&pmugrf->gpio1a_iomux,
 234                              PMUGRF_GPIO1A7_SEL_MASK,
 235                              PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
 236                 rk_clrsetreg(&pmugrf->gpio1b_iomux,
 237                              PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
 238                              | PMUGRF_GPIO1B2_SEL_MASK,
 239                              PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
 240                              | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
 241                              | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
 242                 break;
 243         case PERIPH_ID_SPI2:
 244                 if (cs != 0)
 245                         goto err;
 246                 rk_clrsetreg(&grf->gpio2b_iomux,
 247                              GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
 248                              | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
 249                              GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
 250                              | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
 251                              | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
 252                              | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
 253                 break;
 254         default:
 255                 goto err;
 256         }
 257
 258         return 0;
 259 err:
 260         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 261         return -ENOENT;
 262 }
 263
 264 static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
 265                                        struct rk3399_pmugrf_regs *pmugrf,
 266                                        int uart_id)
 267 {
 268         switch (uart_id) {
 269         case PERIPH_ID_UART2:
 270                 /* Using channel-C by default */
 271                 rk_clrsetreg(&grf->gpio4c_iomux,
 272                              GRF_GPIO4C3_SEL_MASK,
 273                              GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
 274                 rk_clrsetreg(&grf->gpio4c_iomux,
 275                              GRF_GPIO4C4_SEL_MASK,
 276                              GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
 277                 break;
 278         case PERIPH_ID_UART0:
 279         case PERIPH_ID_UART1:
 280         case PERIPH_ID_UART3:
 281         case PERIPH_ID_UART4:
 282         default:
 283                 debug("uart id = %d iomux error!\n", uart_id);
 284                 break;
 285         }
 286 }
 287
 288 static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
 289 {
 290         switch (mmc_id) {
 291         case PERIPH_ID_EMMC:
 292                 break;
 293         case PERIPH_ID_SDCARD:
 294                 rk_clrsetreg(&grf->gpio4b_iomux,
 295                              GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
 296                              | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
 297                              | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
 298                              GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
 299                              | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
 300                              | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
 301                              | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
 302                              | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
 303                              | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
 304                 break;
 305         default:
 306                 debug("mmc id = %d iomux error!\n", mmc_id);
 307                 break;
 308         }
 309 }
 310
 311 static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
 312 {
 313         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 314
 315         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 316         switch (func) {
 317         case PERIPH_ID_PWM0:
 318         case PERIPH_ID_PWM1:
 319         case PERIPH_ID_PWM2:
 320         case PERIPH_ID_PWM3:
 321         case PERIPH_ID_PWM4:
 322                 pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
 323                 break;
 324         case PERIPH_ID_I2C0:
 325         case PERIPH_ID_I2C1:
 326         case PERIPH_ID_I2C2:
 327         case PERIPH_ID_I2C3:
 328         case PERIPH_ID_I2C4:
 329         case PERIPH_ID_I2C5:
 330                 pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
 331                 break;
 332         case PERIPH_ID_SPI0:
 333         case PERIPH_ID_SPI1:
 334         case PERIPH_ID_SPI2:
 335                 pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
 336                 break;
 337         case PERIPH_ID_UART0:
 338         case PERIPH_ID_UART1:
 339         case PERIPH_ID_UART2:
 340         case PERIPH_ID_UART3:
 341         case PERIPH_ID_UART4:
 342                 pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
 343                 break;
 344         case PERIPH_ID_LCDC0:
 345         case PERIPH_ID_LCDC1:
 346                 pinctrl_rk3399_lcdc_config(priv->grf, func);
 347                 break;
 348         case PERIPH_ID_SDMMC0:
 349         case PERIPH_ID_SDMMC1:
 350                 pinctrl_rk3399_sdmmc_config(priv->grf, func);
 351                 break;
 352         default:
 353                 return -EINVAL;
 354         }
 355
 356         return 0;
 357 }
 358
 359 static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
 360                                         struct udevice *periph)
 361 {
 362         u32 cell[3];
 363         int ret;
 364
 365         ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
 366                                    "interrupts", cell, ARRAY_SIZE(cell));
 367         if (ret < 0)
 368                 return -EINVAL;
 369
 370         switch (cell[1]) {
 371         case 68:
 372                 return PERIPH_ID_SPI0;
 373         case 53:
 374                 return PERIPH_ID_SPI1;
 375         case 52:
 376                 return PERIPH_ID_SPI2;
 377         case 57:
 378                 return PERIPH_ID_I2C0;
 379         case 59: /* Note strange order */
 380                 return PERIPH_ID_I2C1;
 381         case 35:
 382                 return PERIPH_ID_I2C2;
 383         case 34:
 384                 return PERIPH_ID_I2C3;
 385         case 56:
 386                 return PERIPH_ID_I2C4;
 387         case 38:
 388                 return PERIPH_ID_I2C5;
 389         case 65:
 390                 return PERIPH_ID_SDMMC1;
 391         }
 392
 393         return -ENOENT;
 394 }
 395
 396 static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
 397                                            struct udevice *periph)
 398 {
 399         int func;
 400
 401         func = rk3399_pinctrl_get_periph_id(dev, periph);
 402         if (func < 0)
 403                 return func;
 404
 405         return rk3399_pinctrl_request(dev, func, 0);
 406 }
 407
 408 static struct pinctrl_ops rk3399_pinctrl_ops = {
 409         .set_state_simple       = rk3399_pinctrl_set_state_simple,
 410         .request        = rk3399_pinctrl_request,
 411         .get_periph_id  = rk3399_pinctrl_get_periph_id,
 412 };
 413
 414 static int rk3399_pinctrl_probe(struct udevice *dev)
 415 {
 416         struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
 417         int ret = 0;
 418
 419         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 420         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 421         debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
 422
 423         return ret;
 424 }
 425
 426 static const struct udevice_id rk3399_pinctrl_ids[] = {
 427         { .compatible = "rockchip,rk3399-pinctrl" },
 428         { }
 429 };
 430
 431 U_BOOT_DRIVER(pinctrl_rk3399) = {
 432         .name           = "rockchip_rk3399_pinctrl",
 433         .id             = UCLASS_PINCTRL,
 434         .of_match       = rk3399_pinctrl_ids,
 435         .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
 436         .ops            = &rk3399_pinctrl_ops,
 437         .bind           = dm_scan_fdt_dev,
 438         .probe          = rk3399_pinctrl_probe,
 439 };