2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/grf_rv1108.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/periph.h>
15 #include <dm/pinctrl.h>
17 DECLARE_GLOBAL_DATA_PTR
;
19 struct rv1108_pinctrl_priv
{
20 struct rv1108_grf
*grf
;
23 /* GRF_GPIO1B_IOMUX */
26 GPIO1B7_MASK
= 3 << GPIO1B7_SHIFT
,
33 GPIO1B6_MASK
= 3 << GPIO1B6_SHIFT
,
36 GPIO1B6_I2S_LRCLKTX_M0
,
40 GPIO1B5_MASK
= 3 << GPIO1B5_SHIFT
,
47 GPIO1B4_MASK
= 3 << GPIO1B4_SHIFT
,
54 GPIO1B3_MASK
= 3 << GPIO1B3_SHIFT
,
61 GPIO1B2_MASK
= 3 << GPIO1B2_SHIFT
,
68 GPIO1B1_MASK
= 3 << GPIO1B1_SHIFT
,
80 /* GRF_GPIO1C_IOMUX */
83 GPIO1C7_MASK
= 3 << GPIO1C7_SHIFT
,
89 GPIO1C6_MASK
= 3 << GPIO1C6_SHIFT
,
92 GPIO1C6_I2S_LRCLKTX_M1
,
95 GPIO1C5_MASK
= 3 << GPIO1C5_SHIFT
,
101 GPIO1C4_MASK
= 3 << GPIO1C4_SHIFT
,
107 GPIO1C3_MASK
= 3 << GPIO1C3_SHIFT
,
113 GPIO1C2_MASK
= 3 << GPIO1C2_SHIFT
,
116 GPIO1C2_I2S_SDIO3_M0
,
120 GPIO1C1_MASK
= 3 << GPIO1C1_SHIFT
,
130 GPIO1C0_I2S_LRCLKRX_M0
,
133 /* GRF_GPIO1D_OIMUX */
136 GPIO1D7_MASK
= 3 << GPIO1D7_SHIFT
,
142 GPIO1D6_MASK
= 1 << GPIO1D6_SHIFT
,
147 GPIO1D5_MASK
= 3 << GPIO1D5_SHIFT
,
153 GPIO1D4_MASK
= 3 << GPIO1D4_SHIFT
,
159 GPIO1D3_MASK
= 3 << GPIO1D3_SHIFT
,
165 GPIO1D2_MASK
= 3 << GPIO1D2_SHIFT
,
172 GPIO1D1_MASK
= 3 << GPIO1D1_SHIFT
,
186 /* GRF_GPIO2A_IOMUX */
189 GPIO2A7_MASK
= 3 << GPIO2A7_SHIFT
,
195 GPIO2A6_MASK
= 3 << GPIO2A6_SHIFT
,
201 GPIO2A5_MASK
= 3 << GPIO2A5_SHIFT
,
207 GPIO2A4_MASK
= 3 << GPIO2A4_SHIFT
,
213 GPIO2A3_MASK
= 3 << GPIO2A3_SHIFT
,
217 GPIO2A3_SFC_HOLD_IO3
,
220 GPIO2A2_MASK
= 3 << GPIO2A2_SHIFT
,
227 GPIO2A1_MASK
= 3 << GPIO2A1_SHIFT
,
234 GPIO2A0_MASK
= 3 << GPIO2A0_SHIFT
,
241 /* GRF_GPIO2D_IOMUX */
244 GPIO2B7_MASK
= 3 << GPIO2B7_SHIFT
,
250 GPIO2B6_MASK
= 1 << GPIO2B6_SHIFT
,
255 GPIO2B5_MASK
= 1 << GPIO2B5_SHIFT
,
260 GPIO2B4_MASK
= 3 << GPIO2B4_SHIFT
,
267 GPIO2B3_MASK
= 1 << GPIO2B3_SHIFT
,
272 GPIO2B2_MASK
= 1 << GPIO2B2_SHIFT
,
277 GPIO2B1_MASK
= 1 << GPIO2B1_SHIFT
,
282 GPIO2B0_MASK
= 1 << GPIO2B0_SHIFT
,
287 /* GRF_GPIO2D_IOMUX */
290 GPIO2D7_MASK
= 1 << GPIO2D7_SHIFT
,
295 GPIO2D6_MASK
= 1 << GPIO2D6_SHIFT
,
300 GPIO2D5_MASK
= 1 << GPIO2D5_SHIFT
,
305 GPIO2D4_MASK
= 1 << GPIO2D4_SHIFT
,
310 GPIO2D3_MASK
= 1 << GPIO2D3_SHIFT
,
315 GPIO2D2_MASK
= 3 << GPIO2D2_SHIFT
,
317 GPIO2D2_UART2_SOUT_M0
,
321 GPIO2D1_MASK
= 3 << GPIO2D1_SHIFT
,
323 GPIO2D1_UART2_SIN_M0
,
335 /* GRF_GPIO3A_IOMUX */
338 GPIO3A7_MASK
= 1 << GPIO3A7_SHIFT
,
342 GPIO3A6_MASK
= 1 << GPIO3A6_SHIFT
,
347 GPIO3A5_MASK
= 1 << GPIO3A5_SHIFT
,
352 GPIO3A4_MASK
= 1 << GPIO3A4_SHIFT
,
357 GPIO3A3_MASK
= 1 << GPIO3A3_SHIFT
,
362 GPIO3A2_MASK
= 1 << GPIO3A2_SHIFT
,
367 GPIO3A1_MASK
= 1 << GPIO3A1_SHIFT
,
377 /* GRF_GPIO3C_IOMUX */
380 GPIO3C7_MASK
= 1 << GPIO3C7_SHIFT
,
385 GPIO3C6_MASK
= 1 << GPIO3C6_SHIFT
,
390 GPIO3C5_MASK
= 1 << GPIO3C5_SHIFT
,
395 GPIO3C4_MASK
= 1 << GPIO3C4_SHIFT
,
400 GPIO3C3_MASK
= 3 << GPIO3C3_SHIFT
,
403 GPIO3C3_UART2_SOUT_M1
,
406 GPIO3C2_MASK
= 3 << GPIO3C2_SHIFT
,
409 GPIO3C2_UART2_SIN_M1
,
412 GPIOC1_MASK
= 1 << GPIOC1_SHIFT
,
422 static void pinctrl_rv1108_uart_config(struct rv1108_grf
*grf
, int uart_id
)
425 case PERIPH_ID_UART0
:
426 rk_clrsetreg(&grf
->gpio3a_iomux
,
427 GPIO3A6_MASK
| GPIO3A5_MASK
,
428 GPIO3A6_UART1_SOUT
<< GPIO3A6_SHIFT
|
429 GPIO3A5_UART1_SIN
<< GPIO3A5_SHIFT
);
431 case PERIPH_ID_UART1
:
432 rk_clrsetreg(&grf
->gpio1d_iomux
,
433 GPIO1D3_MASK
| GPIO1D2_MASK
| GPIO1D1_MASK
|
435 GPIO1D3_UART0_SOUT
<< GPIO1D3_SHIFT
|
436 GPIO1D2_UART0_SIN
<< GPIO1D2_SHIFT
|
437 GPIO1D1_UART0_RTSN
<< GPIO1D1_SHIFT
|
438 GPIO1D0_UART0_CTSN
<< GPIO1D0_SHIFT
);
440 case PERIPH_ID_UART2
:
441 rk_clrsetreg(&grf
->gpio2d_iomux
,
442 GPIO2D2_MASK
| GPIO2D1_MASK
,
443 GPIO2D2_UART2_SOUT_M0
<< GPIO2D2_SHIFT
|
444 GPIO2D1_UART2_SIN_M0
<< GPIO2D1_SHIFT
);
449 static void pinctrl_rv1108_gmac_config(struct rv1108_grf
*grf
, int func
)
451 rk_clrsetreg(&grf
->gpio1b_iomux
,
452 GPIO1B7_MASK
| GPIO1B6_MASK
| GPIO1B5_MASK
|
453 GPIO1B4_MASK
| GPIO1B3_MASK
| GPIO1B2_MASK
,
454 GPIO1B7_GMAC_RXDV
<< GPIO1B7_SHIFT
|
455 GPIO1B6_GMAC_RXD1
<< GPIO1B6_SHIFT
|
456 GPIO1B5_GMAC_RXD0
<< GPIO1B5_SHIFT
|
457 GPIO1B4_GMAC_TXEN
<< GPIO1B4_SHIFT
|
458 GPIO1B3_GMAC_TXD1
<< GPIO1B3_SHIFT
|
459 GPIO1B2_GMAC_TXD0
<< GPIO1B2_SHIFT
);
460 rk_clrsetreg(&grf
->gpio1c_iomux
,
461 GPIO1C5_MASK
| GPIO1C4_MASK
|
462 GPIO1C3_MASK
| GPIO1C2_MASK
,
463 GPIO1C5_GMAC_CLK
<< GPIO1C5_SHIFT
|
464 GPIO1C4_GMAC_MDC
<< GPIO1C4_SHIFT
|
465 GPIO1C3_GMAC_MDIO
<< GPIO1C3_SHIFT
|
466 GPIO1C2_GMAC_RXER
<< GPIO1C2_SHIFT
);
467 writel(0xffff57f5, &grf
->gpio1b_drv
);
470 static void pinctrl_rv1108_sfc_config(struct rv1108_grf
*grf
)
472 rk_clrsetreg(&grf
->gpio2a_iomux
, GPIO2A3_MASK
| GPIO2A2_MASK
|
473 GPIO2A1_MASK
| GPIO2A0_MASK
,
474 GPIO2A3_SFC_HOLD_IO3
<< GPIO2A3_SHIFT
|
475 GPIO2A2_SFC_WP_IO2
<< GPIO2A2_SHIFT
|
476 GPIO2A1_SFC_SO_IO1
<< GPIO2A1_SHIFT
|
477 GPIO2A0_SFC_SI_IO0
<< GPIO2A0_SHIFT
);
478 rk_clrsetreg(&grf
->gpio2b_iomux
, GPIO2B7_MASK
| GPIO2B4_MASK
,
479 GPIO2B7_SFC_CLK
<< GPIO2B7_SHIFT
|
480 GPIO2B4_SFC_CSN0
<< GPIO2B4_SHIFT
);
483 static int rv1108_pinctrl_request(struct udevice
*dev
, int func
, int flags
)
485 struct rv1108_pinctrl_priv
*priv
= dev_get_priv(dev
);
488 case PERIPH_ID_UART0
:
489 case PERIPH_ID_UART1
:
490 case PERIPH_ID_UART2
:
491 pinctrl_rv1108_uart_config(priv
->grf
, func
);
494 pinctrl_rv1108_gmac_config(priv
->grf
, func
);
496 pinctrl_rv1108_sfc_config(priv
->grf
);
504 static int rv1108_pinctrl_get_periph_id(struct udevice
*dev
,
505 struct udevice
*periph
)
510 ret
= dev_read_u32_array(periph
, "interrupts", cell
, ARRAY_SIZE(cell
));
516 return PERIPH_ID_SDCARD
;
518 return PERIPH_ID_EMMC
;
520 return PERIPH_ID_GMAC
;
522 return PERIPH_ID_I2C0
;
524 return PERIPH_ID_I2C1
;
526 return PERIPH_ID_I2C2
;
528 return PERIPH_ID_PWM0
;
530 return PERIPH_ID_UART0
;
532 return PERIPH_ID_UART1
;
534 return PERIPH_ID_UART2
;
536 return PERIPH_ID_SFC
;
542 static int rv1108_pinctrl_set_state_simple(struct udevice
*dev
,
543 struct udevice
*periph
)
547 func
= rv1108_pinctrl_get_periph_id(dev
, periph
);
551 return rv1108_pinctrl_request(dev
, func
, 0);
554 static struct pinctrl_ops rv1108_pinctrl_ops
= {
555 .set_state_simple
= rv1108_pinctrl_set_state_simple
,
556 .request
= rv1108_pinctrl_request
,
557 .get_periph_id
= rv1108_pinctrl_get_periph_id
,
560 static int rv1108_pinctrl_probe(struct udevice
*dev
)
562 struct rv1108_pinctrl_priv
*priv
= dev_get_priv(dev
);
564 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
569 static const struct udevice_id rv1108_pinctrl_ids
[] = {
570 {.compatible
= "rockchip,rv1108-pinctrl" },
574 U_BOOT_DRIVER(pinctrl_rv1108
) = {
575 .name
= "pinctrl_rv1108",
576 .id
= UCLASS_PINCTRL
,
577 .of_match
= rv1108_pinctrl_ids
,
578 .priv_auto_alloc_size
= sizeof(struct rv1108_pinctrl_priv
),
579 .ops
= &rv1108_pinctrl_ops
,
580 .bind
= dm_scan_fdt_dev
,
581 .probe
= rv1108_pinctrl_probe
,