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[people/ms/u-boot.git] / drivers / ram / rockchip / dmc-rk3368.c
1 /*
2 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <dt-bindings/memory/rk3368-dmc.h>
11 #include <dt-structs.h>
12 #include <ram.h>
13 #include <regmap.h>
14 #include <syscon.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cru_rk3368.h>
18 #include <asm/arch/grf_rk3368.h>
19 #include <asm/arch/ddr_rk3368.h>
20 #include <asm/arch/sdram.h>
21 #include <asm/arch/sdram_common.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 struct dram_info {
26 struct ram_info info;
27 struct clk ddr_clk;
28 struct rk3368_cru *cru;
29 struct rk3368_grf *grf;
30 struct rk3368_ddr_pctl *pctl;
31 struct rk3368_ddrphy *phy;
32 struct rk3368_pmu_grf *pmugrf;
33 struct rk3368_msch *msch;
34 };
35
36 struct rk3368_sdram_params {
37 #if CONFIG_IS_ENABLED(OF_PLATDATA)
38 struct dtd_rockchip_rk3368_dmc of_plat;
39 #endif
40 struct rk3288_sdram_pctl_timing pctl_timing;
41 u32 trefi_mem_ddr3;
42 struct rk3288_sdram_channel chan;
43 struct regmap *map;
44 u32 ddr_freq;
45 u32 memory_schedule;
46 u32 ddr_speed_bin;
47 u32 tfaw_mult;
48 };
49
50 /* PTCL bits */
51 enum {
52 /* PCTL_DFISTCFG0 */
53 DFI_INIT_START = BIT(0),
54 DFI_DATA_BYTE_DISABLE_EN = BIT(2),
55
56 /* PCTL_DFISTCFG1 */
57 DFI_DRAM_CLK_SR_EN = BIT(0),
58 DFI_DRAM_CLK_DPD_EN = BIT(1),
59 ODT_LEN_BL8_W_SHIFT = 16,
60
61 /* PCTL_DFISTCFG2 */
62 DFI_PARITY_INTR_EN = BIT(0),
63 DFI_PARITY_EN = BIT(1),
64
65 /* PCTL_DFILPCFG0 */
66 TLP_RESP_TIME_SHIFT = 16,
67 LP_SR_EN = BIT(8),
68 LP_PD_EN = BIT(0),
69
70 /* PCTL_DFIODTCFG */
71 RANK0_ODT_WRITE_SEL = BIT(3),
72 RANK1_ODT_WRITE_SEL = BIT(11),
73
74 /* PCTL_SCFG */
75 HW_LOW_POWER_EN = BIT(0),
76
77 /* PCTL_MCMD */
78 START_CMD = BIT(31),
79 MCMD_RANK0 = BIT(20),
80 MCMD_RANK1 = BIT(21),
81 DESELECT_CMD = 0,
82 PREA_CMD,
83 REF_CMD,
84 MRS_CMD,
85 ZQCS_CMD,
86 ZQCL_CMD,
87 RSTL_CMD,
88 MRR_CMD = 8,
89 DPDE_CMD,
90
91 /* PCTL_POWCTL */
92 POWER_UP_START = BIT(0),
93
94 /* PCTL_POWSTAT */
95 POWER_UP_DONE = BIT(0),
96
97 /* PCTL_SCTL */
98 INIT_STATE = 0,
99 CFG_STATE,
100 GO_STATE,
101 SLEEP_STATE,
102 WAKEUP_STATE,
103
104 /* PCTL_STAT */
105 LP_TRIG_SHIFT = 4,
106 LP_TRIG_MASK = 7,
107 PCTL_STAT_MSK = 7,
108 INIT_MEM = 0,
109 CONFIG,
110 CONFIG_REQ,
111 ACCESS,
112 ACCESS_REQ,
113 LOW_POWER,
114 LOW_POWER_ENTRY_REQ,
115 LOW_POWER_EXIT_REQ,
116
117 /* PCTL_MCFG */
118 DDR2_DDR3_BL_8 = BIT(0),
119 DDR3_EN = BIT(5),
120 TFAW_TRRD_MULT4 = (0 << 18),
121 TFAW_TRRD_MULT5 = (1 << 18),
122 TFAW_TRRD_MULT6 = (2 << 18),
123 };
124
125 #define DDR3_MR0_WR(n) \
126 ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
127 #define DDR3_MR0_CL(n) \
128 ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
129 #define DDR3_MR0_BL8 \
130 (0 << 0)
131 #define DDR3_MR0_DLL_RESET \
132 (1 << 8)
133 #define DDR3_MR1_RTT120OHM \
134 ((0 << 9) | (1 << 6) | (0 << 2))
135 #define DDR3_MR2_TWL(n) \
136 (((n - 5) & 0x7) << 3)
137
138
139 #ifdef CONFIG_TPL_BUILD
140
141 static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
142 {
143 if (enable)
144 rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
145 else
146 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
147 }
148
149 static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
150 {
151 if (ddr3_mode)
152 rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
153 else
154 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
155 }
156
157 static void ddrphy_config(struct rk3368_ddrphy *phy,
158 u32 tcl, u32 tal, u32 tcwl)
159 {
160 int i;
161
162 /* Set to DDR3 mode */
163 clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
164
165 /* DDRPHY_REGB: CL, AL */
166 clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
167 /* DDRPHY_REGC: CWL */
168 clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
169
170 /* Update drive-strength */
171 writel(0xcc, &phy->reg[0x11]);
172 writel(0xaa, &phy->reg[0x16]);
173 /*
174 * Update NRCOMP/PRCOMP for all 4 channels (for details of all
175 * affected registers refer to the documentation of DDRPHY_REG20
176 * and DDRPHY_REG21 in the RK3368 TRM.
177 */
178 for (i = 0; i < 4; ++i) {
179 writel(0xcc, &phy->reg[0x20 + i * 0x10]);
180 writel(0x44, &phy->reg[0x21 + i * 0x10]);
181 }
182
183 /* Enable write-leveling calibration bypass */
184 setbits_le32(&phy->reg[2], BIT(3));
185 }
186
187 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
188 {
189 int i;
190
191 for (i = 0; i < n / sizeof(u32); i++)
192 writel(*src++, dest++);
193 }
194
195 static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
196 {
197 u32 mcmd = START_CMD | cmd | rank;
198
199 debug("%s: writing %x to MCMD\n", __func__, mcmd);
200 writel(mcmd, &pctl->mcmd);
201 while (readl(&pctl->mcmd) & START_CMD)
202 /* spin */;
203 }
204
205 static void send_mrs(struct rk3368_ddr_pctl *pctl,
206 u32 rank, u32 mr_num, u32 mr_data)
207 {
208 u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
209
210 debug("%s: writing %x to MCMD\n", __func__, mcmd);
211 writel(mcmd, &pctl->mcmd);
212 while (readl(&pctl->mcmd) & START_CMD)
213 /* spin */;
214 }
215
216 static int memory_init(struct rk3368_ddr_pctl *pctl,
217 struct rk3368_sdram_params *params)
218 {
219 u32 mr[4];
220 const ulong timeout_ms = 500;
221 ulong tmp;
222
223 /*
224 * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
225 * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
226 * of PCTL.
227 */
228 writel(POWER_UP_START, &pctl->powctl);
229
230 tmp = get_timer(0);
231 do {
232 if (get_timer(tmp) > timeout_ms) {
233 error("%s: POWER_UP_START did not complete in %ld ms\n",
234 __func__, timeout_ms);
235 return -ETIME;
236 }
237 } while (!(readl(&pctl->powstat) & POWER_UP_DONE));
238
239 /* Configure MR0 through MR3 */
240 mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
241 DDR3_MR0_CL(params->pctl_timing.tcl) |
242 DDR3_MR0_DLL_RESET;
243 mr[1] = DDR3_MR1_RTT120OHM;
244 mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
245 mr[3] = 0;
246
247 /*
248 * Also see RK3368 Technical Reference Manual:
249 * "16.6.2 Initialization (DDR3 Initialization Sequence)"
250 */
251 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
252 udelay(1);
253 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
254 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
255 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
256 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
257 send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
258 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
259
260 return 0;
261 }
262
263 static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
264 {
265 /*
266 * Also see RK3368 Technical Reference Manual:
267 * "16.6.1 State transition of PCTL (Moving to Config State)"
268 */
269 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
270
271 switch (state) {
272 case LOW_POWER:
273 writel(WAKEUP_STATE, &pctl->sctl);
274 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
275 /* spin */;
276
277 /* fall-through */
278 case ACCESS:
279 case INIT_MEM:
280 writel(CFG_STATE, &pctl->sctl);
281 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
282 /* spin */;
283 break;
284
285 case CONFIG:
286 return;
287
288 default:
289 break;
290 }
291 }
292
293 static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
294 {
295 /*
296 * Also see RK3368 Technical Reference Manual:
297 * "16.6.1 State transition of PCTL (Moving to Access State)"
298 */
299 u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
300
301 switch (state) {
302 case LOW_POWER:
303 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
304 LP_TRIG_MASK) == 1)
305 return;
306
307 writel(WAKEUP_STATE, &pctl->sctl);
308 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
309 /* spin */;
310
311 /* fall-through */
312 case INIT_MEM:
313 writel(CFG_STATE, &pctl->sctl);
314 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
315 /* spin */;
316
317 /* fall-through */
318 case CONFIG:
319 writel(GO_STATE, &pctl->sctl);
320 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
321 /* spin */;
322 break;
323
324 case ACCESS:
325 return;
326
327 default:
328 break;
329 }
330 }
331
332 static void ddrctl_reset(struct rk3368_cru *cru)
333 {
334 const u32 ctl_reset = BIT(3) | BIT(2);
335 const u32 phy_reset = BIT(1) | BIT(0);
336
337 /*
338 * The PHY reset should be released before the PCTL reset.
339 *
340 * Note that the following sequence (including the number of
341 * us to delay between releasing the PHY and PCTL reset) has
342 * been adapted per feedback received from Rockchips, so do
343 * not try to optimise.
344 */
345 rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
346 udelay(1);
347 rk_clrreg(&cru->softrst_con[10], phy_reset);
348 udelay(5);
349 rk_clrreg(&cru->softrst_con[10], ctl_reset);
350 }
351
352 static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
353 {
354 /*
355 * The analog part of the PHY should be release at least 1000
356 * DRAM cycles before the digital part of the PHY (waiting for
357 * 5us will ensure this for a DRAM clock as low as 200MHz).
358 */
359 clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
360 udelay(1);
361 setbits_le32(&ddrphy->reg[0], BIT(2));
362 udelay(5);
363 setbits_le32(&ddrphy->reg[0], BIT(3));
364 }
365
366 static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
367 {
368 u32 dqs_dll_delay;
369
370 setbits_le32(&ddrphy->reg[0x13], BIT(4));
371 clrbits_le32(&ddrphy->reg[0x14], BIT(3));
372
373 setbits_le32(&ddrphy->reg[0x26], BIT(4));
374 clrbits_le32(&ddrphy->reg[0x27], BIT(3));
375
376 setbits_le32(&ddrphy->reg[0x36], BIT(4));
377 clrbits_le32(&ddrphy->reg[0x37], BIT(3));
378
379 setbits_le32(&ddrphy->reg[0x46], BIT(4));
380 clrbits_le32(&ddrphy->reg[0x47], BIT(3));
381
382 setbits_le32(&ddrphy->reg[0x56], BIT(4));
383 clrbits_le32(&ddrphy->reg[0x57], BIT(3));
384
385 if (freq <= 400000000)
386 setbits_le32(&ddrphy->reg[0xa4], 0x1f);
387 else
388 clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
389
390 if (freq < 681000000)
391 dqs_dll_delay = 3; /* 67.5 degree delay */
392 else
393 dqs_dll_delay = 2; /* 45 degree delay */
394
395 writel(dqs_dll_delay, &ddrphy->reg[0x28]);
396 writel(dqs_dll_delay, &ddrphy->reg[0x38]);
397 writel(dqs_dll_delay, &ddrphy->reg[0x48]);
398 writel(dqs_dll_delay, &ddrphy->reg[0x58]);
399 }
400
401 static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
402 {
403 const ulong timeout_ms = 200;
404 ulong tmp;
405
406 writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
407
408 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
409 &pctl->dfistcfg1);
410 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
411 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
412 &pctl->dfilpcfg0);
413
414 writel(1, &pctl->dfitphyupdtype0);
415
416 writel(0x1f, &pctl->dfitphyrdlat);
417 writel(0, &pctl->dfitphywrdata);
418 writel(0, &pctl->dfiupdcfg); /* phyupd and ctrlupd disabled */
419
420 setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
421
422 tmp = get_timer(0);
423 do {
424 if (get_timer(tmp) > timeout_ms) {
425 error("%s: DFI init did not complete within %ld ms\n",
426 __func__, timeout_ms);
427 return -ETIME;
428 }
429 } while ((readl(&pctl->dfiststat0) & 1) == 0);
430
431 return 0;
432 }
433
434 static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
435 {
436 const ulong MHz = 1000000;
437 return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
438 }
439
440 static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
441 {
442 return ps_to_tCK(ns * 1000, freq);
443 }
444
445 static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
446 {
447 const ulong MHz = 1000000;
448 return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
449 }
450
451 static int pctl_calc_timings(struct rk3368_sdram_params *params,
452 ulong freq)
453 {
454 struct rk3288_sdram_pctl_timing *pctl_timing = &params->pctl_timing;
455 const ulong MHz = 1000000;
456 u32 tccd;
457 u32 tfaw_as_ps;
458
459 if (params->ddr_speed_bin != DDR3_1600K) {
460 error("%s: unimplemented DDR3 speed bin %d\n",
461 __func__, params->ddr_speed_bin);
462 return -1;
463 }
464
465 /* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
466 pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
467 pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
468
469 pctl_timing->tinit = 200; /* 200 usec */
470 pctl_timing->trsth = 500; /* 500 usec */
471 pctl_timing->trefi = 78; /* 7.8usec = 78 * 100ns */
472 params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
473
474 if (freq <= (400 * MHz)) {
475 pctl_timing->tcl = 6;
476 pctl_timing->tcwl = 10;
477 } else if (freq <= (533 * MHz)) {
478 pctl_timing->tcl = 8;
479 pctl_timing->tcwl = 6;
480 } else if (freq <= (666 * MHz)) {
481 pctl_timing->tcl = 10;
482 pctl_timing->tcwl = 7;
483 } else {
484 pctl_timing->tcl = 11;
485 pctl_timing->tcwl = 8;
486 }
487
488 pctl_timing->tmrd = 4; /* 4 tCK (all speed bins) */
489 pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
490 pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
491 /*
492 * JESD-79:
493 * READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
494 */
495 tccd = 4;
496 pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
497 pctl_timing->tal = 0;
498 pctl_timing->tras = ps_to_tCK(35000, freq);
499 pctl_timing->trc = ps_to_tCK(48750, freq);
500 pctl_timing->trcd = ps_to_tCK(13750, freq);
501 pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
502 pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
503 pctl_timing->twr = ps_to_tCK(15000, freq);
504 /* The DDR3 mode-register does only support even values for tWR > 8. */
505 if (pctl_timing->twr > 8)
506 pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
507 pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
508 pctl_timing->texsr = 512; /* tEXSR(max) is tDLLLK */
509 pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
510 pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
511 pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
512 pctl_timing->tzqcsi = 10000; /* as used by Rockchip */
513 pctl_timing->tdqs = 1; /* fixed for DDR3 */
514 pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
515 pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
516 pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
517 pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
518 pctl_timing->trstl = ns_to_tCK(100, freq);
519 pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq)); /* tZQoper */
520 pctl_timing->tmrr = 0;
521 pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */
522 pctl_timing->tdpd = 0; /* RK3368 TRM: "allowed values for DDR3: 0" */
523
524
525 /*
526 * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
527 * We want to use the smallest multiplier that satisfies the tFAW
528 * requirements of the given speed-bin. If necessary, we stretch out
529 * tRRD to allow us to operate on a 6x multiplier for tFAW.
530 */
531 tfaw_as_ps = 40000; /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
532 if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
533 /* If tFAW is > 6 x tRRD, we need to stretch tRRD */
534 pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
535 params->tfaw_mult = TFAW_TRRD_MULT6;
536 } else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
537 params->tfaw_mult = TFAW_TRRD_MULT6;
538 } else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
539 params->tfaw_mult = TFAW_TRRD_MULT5;
540 } else {
541 params->tfaw_mult = TFAW_TRRD_MULT4;
542 }
543
544 return 0;
545 }
546
547 static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
548 struct rk3368_sdram_params *params,
549 struct rk3368_grf *grf)
550 {
551 /* Configure PCTL timing registers */
552 params->pctl_timing.trefi |= BIT(31); /* see PCTL_TREFI */
553 copy_to_reg(&pctl->togcnt1u, &params->pctl_timing.togcnt1u,
554 sizeof(params->pctl_timing));
555 writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
556
557 /* Set up ODT write selector and ODT write length */
558 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
559 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
560
561 /* Set up the CL/CWL-dependent timings of DFI */
562 writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
563 writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
564
565 /* DDR3 */
566 writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
567 writel(0x001c0004, &grf->ddrc0_con0);
568
569 setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
570 }
571
572 static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
573 struct rk3368_ddrphy *ddrphy)
574 {
575 const u32 trefi = readl(&pctl->trefi);
576 const ulong timeout_ms = 500;
577 ulong tmp;
578
579 /* disable auto-refresh */
580 writel(0 | BIT(31), &pctl->trefi);
581
582 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
583 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
584
585 tmp = get_timer(0);
586 do {
587 if (get_timer(tmp) > timeout_ms) {
588 error("%s: did not complete within %ld ms\n",
589 __func__, timeout_ms);
590 return -ETIME;
591 }
592 } while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
593
594 send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
595 clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
596 /* resume auto-refresh */
597 writel(trefi | BIT(31), &pctl->trefi);
598
599 return 0;
600 }
601
602 static int sdram_col_row_detect(struct udevice *dev)
603 {
604 struct dram_info *priv = dev_get_priv(dev);
605 struct rk3368_sdram_params *params = dev_get_platdata(dev);
606 struct rk3368_ddr_pctl *pctl = priv->pctl;
607 struct rk3368_msch *msch = priv->msch;
608 const u32 test_pattern = 0x5aa5f00f;
609 int row, col;
610 uintptr_t addr;
611
612 move_to_config_state(pctl);
613 writel(6, &msch->ddrconf);
614 move_to_access_state(pctl);
615
616 /* Detect col */
617 for (col = 11; col >= 9; col--) {
618 writel(0, CONFIG_SYS_SDRAM_BASE);
619 addr = CONFIG_SYS_SDRAM_BASE +
620 (1 << (col + params->chan.bw - 1));
621 writel(test_pattern, addr);
622 if ((readl(addr) == test_pattern) &&
623 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
624 break;
625 }
626
627 if (col == 8) {
628 error("%s: col detect error\n", __func__);
629 return -EINVAL;
630 }
631
632 move_to_config_state(pctl);
633 writel(15, &msch->ddrconf);
634 move_to_access_state(pctl);
635
636 /* Detect row*/
637 for (row = 16; row >= 12; row--) {
638 writel(0, CONFIG_SYS_SDRAM_BASE);
639 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
640 writel(test_pattern, addr);
641 if ((readl(addr) == test_pattern) &&
642 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
643 break;
644 }
645
646 if (row == 11) {
647 error("%s: row detect error\n", __func__);
648 return -EINVAL;
649 }
650
651 /* Record results */
652 debug("%s: col %d, row %d\n", __func__, col, row);
653 params->chan.col = col;
654 params->chan.cs0_row = row;
655 params->chan.cs1_row = row;
656 params->chan.row_3_4 = 0;
657
658 return 0;
659 }
660
661 static int msch_niu_config(struct rk3368_msch *msch,
662 struct rk3368_sdram_params *params)
663 {
664 int i;
665 const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
666 const u8 rows = params->chan.cs0_row;
667
668 /*
669 * The DDR address-translation table always assumes a 32bit
670 * bus and the comparison below takes care of adjusting for
671 * a 16bit bus (i.e. one column-address is consumed).
672 */
673 const struct {
674 u8 rows;
675 u8 columns;
676 u8 type;
677 } ddrconf_table[] = {
678 /*
679 * C-B-R-D patterns are first. For these we require an
680 * exact match for the columns and rows (as there's
681 * one entry per possible configuration).
682 */
683 [0] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
684 [1] = { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
685 [2] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
686 [3] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
687 [4] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
688 [5] = { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
689 [6] = { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
690 [7] = { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
691 [8] = { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
692 [9] = { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
693 [10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
694 /*
695 * 11 through 13 are C-R-B-D patterns. These are
696 * matched for an exact number of columns and to
697 * ensure that the hardware uses at least as many rows
698 * as the pattern requires (i.e. we make sure that
699 * there's no gaps up until we hit the device/chip-select;
700 * however, these patterns can accept up to 16 rows,
701 * as the row-address continues right after the CS
702 * switching)
703 */
704 [11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
705 [12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
706 [13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
707 /*
708 * 14 and 15 are catch-all variants using a C-B-D-R
709 * scheme (i.e. alternating the chip-select every time
710 * C-B overflows) and stuffing the remaining C-bits
711 * into the top. Matching needs to make sure that the
712 * number of columns is either an exact match (i.e. we
713 * can use less the the maximum number of rows) -or-
714 * that the columns exceed what is given in this table
715 * and the rows are an exact match (in which case the
716 * remaining C-bits will be stuffed onto the top after
717 * the device/chip-select switches).
718 */
719 [14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
720 [15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
721 };
722
723 /*
724 * For C-B-R-D, we need an exact match (i.e. both for the number of
725 * columns and rows), while for C-B-D-R, only the the number of
726 * columns needs to match.
727 */
728 for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
729 bool match = false;
730
731 /* If this entry if for a different matcher, then skip it */
732 if (ddrconf_table[i].type != params->memory_schedule)
733 continue;
734
735 /*
736 * Match according to the rules (exact/inexact/at-least)
737 * documented in the ddrconf_table above.
738 */
739 switch (params->memory_schedule) {
740 case DMC_MSCH_CBRD:
741 match = (ddrconf_table[i].columns == cols) &&
742 (ddrconf_table[i].rows == rows);
743 break;
744
745 case DMC_MSCH_CRBD:
746 match = (ddrconf_table[i].columns == cols) &&
747 (ddrconf_table[i].rows <= rows);
748 break;
749
750 case DMC_MSCH_CBDR:
751 match = (ddrconf_table[i].columns == cols) ||
752 ((ddrconf_table[i].columns <= cols) &&
753 (ddrconf_table[i].rows == rows));
754 break;
755
756 default:
757 break;
758 }
759
760 if (match) {
761 debug("%s: setting ddrconf 0x%x\n", __func__, i);
762 writel(i, &msch->ddrconf);
763 return 0;
764 }
765 }
766
767 error("%s: ddrconf (NIU config) not found\n", __func__);
768 return -EINVAL;
769 }
770
771 static void dram_all_config(struct udevice *dev)
772 {
773 struct dram_info *priv = dev_get_priv(dev);
774 struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
775 struct rk3368_sdram_params *params = dev_get_platdata(dev);
776 const struct rk3288_sdram_channel *info = &params->chan;
777 u32 sys_reg = 0;
778 const int chan = 0;
779
780 sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
781 sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
782
783 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
784 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
785 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
786 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
787 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
788 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
789 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
790 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
791 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
792
793 writel(sys_reg, &pmugrf->os_reg[2]);
794 }
795
796 static int setup_sdram(struct udevice *dev)
797 {
798 struct dram_info *priv = dev_get_priv(dev);
799 struct rk3368_sdram_params *params = dev_get_platdata(dev);
800
801 struct rk3368_ddr_pctl *pctl = priv->pctl;
802 struct rk3368_ddrphy *ddrphy = priv->phy;
803 struct rk3368_cru *cru = priv->cru;
804 struct rk3368_grf *grf = priv->grf;
805 struct rk3368_msch *msch = priv->msch;
806
807 int ret;
808
809 /* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
810 ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
811 if (ret < 0) {
812 debug("%s: could not set DDR clock: %d\n", __func__, ret);
813 return ret;
814 }
815
816 /* Update the read-latency for the RK3368 */
817 writel(0x32, &msch->readlatency);
818
819 /* Initialise the DDR PCTL and DDR PHY */
820 ddrctl_reset(cru);
821 ddrphy_reset(ddrphy);
822 ddrphy_config_delays(ddrphy, params->ddr_freq);
823 dfi_cfg(pctl);
824 /* Configure relative system information of grf_ddrc0_con0 register */
825 ddr_set_ddr3_mode(grf, true);
826 ddr_set_noc_spr_err_stall(grf, true);
827 /* Calculate timings */
828 pctl_calc_timings(params, params->ddr_freq);
829 /* Initialise the device timings in protocol controller */
830 pctl_cfg(pctl, params, grf);
831 /* Configure AL, CL ... information of PHY registers */
832 ddrphy_config(ddrphy,
833 params->pctl_timing.tcl,
834 params->pctl_timing.tal,
835 params->pctl_timing.tcwl);
836
837 /* Initialize DRAM and configure with mode-register values */
838 ret = memory_init(pctl, params);
839 if (ret)
840 goto error;
841
842 move_to_config_state(pctl);
843 /* Perform data-training */
844 ddrphy_data_training(pctl, ddrphy);
845 move_to_access_state(pctl);
846
847 /* TODO(prt): could detect rank in training... */
848 params->chan.rank = 2;
849 /* TODO(prt): bus width is not auto-detected (yet)... */
850 params->chan.bw = 2; /* 32bit wide bus */
851 params->chan.dbw = params->chan.dbw; /* 32bit wide bus */
852
853 /* DDR3 is always 8 bank */
854 params->chan.bk = 3;
855 /* Detect col and row number */
856 ret = sdram_col_row_detect(dev);
857 if (ret)
858 goto error;
859
860 /* Configure NIU DDR configuration */
861 ret = msch_niu_config(msch, params);
862 if (ret)
863 goto error;
864
865 /* set up OS_REG to communicate w/ next stage and OS */
866 dram_all_config(dev);
867
868 return 0;
869
870 error:
871 printf("DRAM init failed!\n");
872 hang();
873 }
874 #endif
875
876 static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
877 {
878 int ret = 0;
879
880 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
881 struct rk3368_sdram_params *plat = dev_get_platdata(dev);
882
883 ret = regmap_init_mem(dev, &plat->map);
884 if (ret)
885 return ret;
886 #endif
887
888 return ret;
889 }
890
891 #if CONFIG_IS_ENABLED(OF_PLATDATA)
892 static int conv_of_platdata(struct udevice *dev)
893 {
894 struct rk3368_sdram_params *plat = dev_get_platdata(dev);
895 struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
896
897 plat->ddr_freq = of_plat->rockchip_ddr_frequency;
898 plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
899 plat->memory_schedule = of_plat->rockchip_memory_schedule;
900
901 return 0;
902 }
903 #endif
904
905 static int rk3368_dmc_probe(struct udevice *dev)
906 {
907 #ifdef CONFIG_TPL_BUILD
908 struct rk3368_sdram_params *plat = dev_get_platdata(dev);
909 struct rk3368_ddr_pctl *pctl;
910 struct rk3368_ddrphy *ddrphy;
911 struct rk3368_cru *cru;
912 struct rk3368_grf *grf;
913 struct rk3368_msch *msch;
914 int ret;
915 struct udevice *dev_clk;
916 #endif
917 struct dram_info *priv = dev_get_priv(dev);
918
919 #if CONFIG_IS_ENABLED(OF_PLATDATA)
920 ret = conv_of_platdata(dev);
921 if (ret)
922 return ret;
923 #endif
924
925 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
926 debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
927
928 #ifdef CONFIG_TPL_BUILD
929 pctl = (struct rk3368_ddr_pctl *)plat->of_plat.reg[0];
930 ddrphy = (struct rk3368_ddrphy *)plat->of_plat.reg[2];
931 msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
932 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
933
934 priv->pctl = pctl;
935 priv->phy = ddrphy;
936 priv->msch = msch;
937 priv->grf = grf;
938
939 ret = rockchip_get_clk(&dev_clk);
940 if (ret)
941 return ret;
942 priv->ddr_clk.id = CLK_DDR;
943 ret = clk_request(dev_clk, &priv->ddr_clk);
944 if (ret)
945 return ret;
946
947 cru = rockchip_get_cru();
948 priv->cru = cru;
949 if (IS_ERR(priv->cru))
950 return PTR_ERR(priv->cru);
951
952 ret = setup_sdram(dev);
953 if (ret)
954 return ret;
955 #endif
956
957 priv->info.base = 0;
958 priv->info.size =
959 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
960
961 /*
962 * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
963 * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
964 * inaccessible for some IP controller.
965 */
966 priv->info.size = min(priv->info.size, (size_t)0xfe000000);
967
968 return 0;
969 }
970
971 static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
972 {
973 struct dram_info *priv = dev_get_priv(dev);
974
975 *info = priv->info;
976 return 0;
977 }
978
979 static struct ram_ops rk3368_dmc_ops = {
980 .get_info = rk3368_dmc_get_info,
981 };
982
983
984 static const struct udevice_id rk3368_dmc_ids[] = {
985 { .compatible = "rockchip,rk3368-dmc" },
986 { }
987 };
988
989 U_BOOT_DRIVER(dmc_rk3368) = {
990 .name = "rockchip_rk3368_dmc",
991 .id = UCLASS_RAM,
992 .of_match = rk3368_dmc_ids,
993 .ops = &rk3368_dmc_ops,
994 .probe = rk3368_dmc_probe,
995 .priv_auto_alloc_size = sizeof(struct dram_info),
996 .ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
997 .probe = rk3368_dmc_probe,
998 .priv_auto_alloc_size = sizeof(struct dram_info),
999 .platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
1000 };
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