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dm: imx: serial: Support DTE mode when using driver model
[people/ms/u-boot.git] / drivers / serial / serial_mxc.c
1 /*
2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <watchdog.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/clock.h>
13 #include <dm/platform_data/serial_mxc.h>
14 #include <serial.h>
15 #include <linux/compiler.h>
16
17 /* UART Control Register Bit Fields.*/
18 #define URXD_CHARRDY (1<<15)
19 #define URXD_ERR (1<<14)
20 #define URXD_OVRRUN (1<<13)
21 #define URXD_FRMERR (1<<12)
22 #define URXD_BRK (1<<11)
23 #define URXD_PRERR (1<<10)
24 #define URXD_RX_DATA (0xFF)
25 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
26 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
27 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
28 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
29 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
30 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
31 #define UCR1_IREN (1<<7) /* Infrared interface enable */
32 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
33 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
34 #define UCR1_SNDBRK (1<<4) /* Send break */
35 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
36 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
37 #define UCR1_DOZE (1<<1) /* Doze */
38 #define UCR1_UARTEN (1<<0) /* UART enabled */
39 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
40 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
41 #define UCR2_CTSC (1<<13) /* CTS pin control */
42 #define UCR2_CTS (1<<12) /* Clear to send */
43 #define UCR2_ESCEN (1<<11) /* Escape enable */
44 #define UCR2_PREN (1<<8) /* Parity enable */
45 #define UCR2_PROE (1<<7) /* Parity odd/even */
46 #define UCR2_STPB (1<<6) /* Stop */
47 #define UCR2_WS (1<<5) /* Word size */
48 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
49 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
50 #define UCR2_RXEN (1<<1) /* Receiver enabled */
51 #define UCR2_SRST (1<<0) /* SW reset */
52 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
53 #define UCR3_PARERREN (1<<12) /* Parity enable */
54 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
55 #define UCR3_DSR (1<<10) /* Data set ready */
56 #define UCR3_DCD (1<<9) /* Data carrier detect */
57 #define UCR3_RI (1<<8) /* Ring indicator */
58 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
59 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
60 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
61 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
62 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
63 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
64 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
65 #define UCR3_BPEN (1<<0) /* Preset registers enable */
66 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
67 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
68 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
69 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
70 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
71 #define UCR4_IRSC (1<<5) /* IR special case */
72 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
73 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
74 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
75 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
76 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
77 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
78 #define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
79 #define UFCR_DCEDTE (1<<6) /* DTE mode select */
80 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
81 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
82 #define USR1_RTSS (1<<14) /* RTS pin status */
83 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
84 #define USR1_RTSD (1<<12) /* RTS delta */
85 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
86 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
87 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
88 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
89 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
90 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
91 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
92 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
93 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
94 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
95 #define USR2_IDLE (1<<12) /* Idle condition */
96 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
97 #define USR2_WAKE (1<<7) /* Wake */
98 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
99 #define USR2_TXDC (1<<3) /* Transmitter complete */
100 #define USR2_BRCD (1<<2) /* Break condition */
101 #define USR2_ORE (1<<1) /* Overrun error */
102 #define USR2_RDR (1<<0) /* Recv data ready */
103 #define UTS_FRCPERR (1<<13) /* Force parity error */
104 #define UTS_LOOP (1<<12) /* Loop tx and rx */
105 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
106 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
107 #define UTS_TXFULL (1<<4) /* TxFIFO full */
108 #define UTS_RXFULL (1<<3) /* RxFIFO full */
109 #define UTS_SOFTRST (1<<0) /* Software reset */
110
111 #ifndef CONFIG_DM_SERIAL
112
113 #ifndef CONFIG_MXC_UART_BASE
114 #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
115 #endif
116
117 #define UART_PHYS CONFIG_MXC_UART_BASE
118
119 #define __REG(x) (*((volatile u32 *)(x)))
120
121 /* Register definitions */
122 #define URXD 0x0 /* Receiver Register */
123 #define UTXD 0x40 /* Transmitter Register */
124 #define UCR1 0x80 /* Control Register 1 */
125 #define UCR2 0x84 /* Control Register 2 */
126 #define UCR3 0x88 /* Control Register 3 */
127 #define UCR4 0x8c /* Control Register 4 */
128 #define UFCR 0x90 /* FIFO Control Register */
129 #define USR1 0x94 /* Status Register 1 */
130 #define USR2 0x98 /* Status Register 2 */
131 #define UESC 0x9c /* Escape Character Register */
132 #define UTIM 0xa0 /* Escape Timer Register */
133 #define UBIR 0xa4 /* BRM Incremental Register */
134 #define UBMR 0xa8 /* BRM Modulator Register */
135 #define UBRC 0xac /* Baud Rate Count Register */
136 #define UTS 0xb4 /* UART Test Register (mx31) */
137
138 DECLARE_GLOBAL_DATA_PTR;
139
140 #define TXTL 2 /* reset default */
141 #define RXTL 1 /* reset default */
142 #define RFDIV 4 /* divide input clock by 2 */
143
144 static void mxc_serial_setbrg(void)
145 {
146 u32 clk = imx_get_uartclk();
147
148 if (!gd->baudrate)
149 gd->baudrate = CONFIG_BAUDRATE;
150
151 __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
152 | (TXTL << UFCR_TXTL_SHF)
153 | (RXTL << UFCR_RXTL_SHF);
154 __REG(UART_PHYS + UFCR) |= UFCR_DCEDTE;
155 __REG(UART_PHYS + UBIR) = 0xf;
156 __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
157
158 }
159
160 static int mxc_serial_getc(void)
161 {
162 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
163 WATCHDOG_RESET();
164 return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
165 }
166
167 static void mxc_serial_putc(const char c)
168 {
169 /* If \n, also do \r */
170 if (c == '\n')
171 serial_putc('\r');
172
173 __REG(UART_PHYS + UTXD) = c;
174
175 /* wait for transmitter to be ready */
176 while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
177 WATCHDOG_RESET();
178 }
179
180 /*
181 * Test whether a character is in the RX buffer
182 */
183 static int mxc_serial_tstc(void)
184 {
185 /* If receive fifo is empty, return false */
186 if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
187 return 0;
188 return 1;
189 }
190
191 /*
192 * Initialise the serial port with the given baudrate. The settings
193 * are always 8 data bits, no parity, 1 stop bit, no start bits.
194 *
195 */
196 static int mxc_serial_init(void)
197 {
198 __REG(UART_PHYS + UCR1) = 0x0;
199 __REG(UART_PHYS + UCR2) = 0x0;
200
201 while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
202
203 __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP;
204 __REG(UART_PHYS + UCR4) = 0x8000;
205 __REG(UART_PHYS + UESC) = 0x002b;
206 __REG(UART_PHYS + UTIM) = 0x0;
207
208 __REG(UART_PHYS + UTS) = 0x0;
209
210 serial_setbrg();
211
212 __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
213
214 __REG(UART_PHYS + UCR1) = UCR1_UARTEN;
215
216 return 0;
217 }
218
219 static struct serial_device mxc_serial_drv = {
220 .name = "mxc_serial",
221 .start = mxc_serial_init,
222 .stop = NULL,
223 .setbrg = mxc_serial_setbrg,
224 .putc = mxc_serial_putc,
225 .puts = default_serial_puts,
226 .getc = mxc_serial_getc,
227 .tstc = mxc_serial_tstc,
228 };
229
230 void mxc_serial_initialize(void)
231 {
232 serial_register(&mxc_serial_drv);
233 }
234
235 __weak struct serial_device *default_serial_console(void)
236 {
237 return &mxc_serial_drv;
238 }
239 #endif
240
241 #ifdef CONFIG_DM_SERIAL
242
243 struct mxc_uart {
244 u32 rxd;
245 u32 spare0[15];
246
247 u32 txd;
248 u32 spare1[15];
249
250 u32 cr1;
251 u32 cr2;
252 u32 cr3;
253 u32 cr4;
254
255 u32 fcr;
256 u32 sr1;
257 u32 sr2;
258 u32 esc;
259
260 u32 tim;
261 u32 bir;
262 u32 bmr;
263 u32 brc;
264
265 u32 onems;
266 u32 ts;
267 };
268
269 int mxc_serial_setbrg(struct udevice *dev, int baudrate)
270 {
271 struct mxc_serial_platdata *plat = dev->platdata;
272 struct mxc_uart *const uart = plat->reg;
273 u32 clk = imx_get_uartclk();
274 u32 tmp;
275
276 tmp = 4 << UFCR_RFDIV_SHF;
277 if (plat->use_dte)
278 tmp |= UFCR_DCEDTE;
279 writel(tmp, &uart->fcr);
280
281 writel(0xf, &uart->bir);
282 writel(clk / (2 * baudrate), &uart->bmr);
283
284 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
285 &uart->cr2);
286 writel(UCR1_UARTEN, &uart->cr1);
287
288 return 0;
289 }
290
291 static int mxc_serial_probe(struct udevice *dev)
292 {
293 struct mxc_serial_platdata *plat = dev->platdata;
294 struct mxc_uart *const uart = plat->reg;
295
296 writel(0, &uart->cr1);
297 writel(0, &uart->cr2);
298 while (!(readl(&uart->cr2) & UCR2_SRST));
299 writel(0x704 | UCR3_ADNIMP, &uart->cr3);
300 writel(0x8000, &uart->cr4);
301 writel(0x2b, &uart->esc);
302 writel(0, &uart->tim);
303 writel(0, &uart->ts);
304
305 return 0;
306 }
307
308 static int mxc_serial_getc(struct udevice *dev)
309 {
310 struct mxc_serial_platdata *plat = dev->platdata;
311 struct mxc_uart *const uart = plat->reg;
312
313 if (readl(&uart->ts) & UTS_RXEMPTY)
314 return -EAGAIN;
315
316 return readl(&uart->rxd) & URXD_RX_DATA;
317 }
318
319 static int mxc_serial_putc(struct udevice *dev, const char ch)
320 {
321 struct mxc_serial_platdata *plat = dev->platdata;
322 struct mxc_uart *const uart = plat->reg;
323
324 if (!(readl(&uart->ts) & UTS_TXEMPTY))
325 return -EAGAIN;
326
327 writel(ch, &uart->txd);
328
329 return 0;
330 }
331
332 static int mxc_serial_pending(struct udevice *dev, bool input)
333 {
334 struct mxc_serial_platdata *plat = dev->platdata;
335 struct mxc_uart *const uart = plat->reg;
336 uint32_t sr2 = readl(&uart->sr2);
337
338 if (input)
339 return sr2 & USR2_RDR ? 1 : 0;
340 else
341 return sr2 & USR2_TXDC ? 0 : 1;
342 }
343
344 static const struct dm_serial_ops mxc_serial_ops = {
345 .putc = mxc_serial_putc,
346 .pending = mxc_serial_pending,
347 .getc = mxc_serial_getc,
348 .setbrg = mxc_serial_setbrg,
349 };
350
351 U_BOOT_DRIVER(serial_mxc) = {
352 .name = "serial_mxc",
353 .id = UCLASS_SERIAL,
354 .probe = mxc_serial_probe,
355 .ops = &mxc_serial_ops,
356 .flags = DM_FLAG_PRE_RELOC,
357 };
358 #endif
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