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arm64: dts: sun50i: h5: Order nodes in alphabetic for orangepi-prime
[people/ms/u-boot.git] / drivers / serial / serial_sh.h
1 /*
2 * Copy and modify from linux/drivers/serial/sh-sci.h
3 */
4
5 #include <dm/platform_data/serial_sh.h>
6
7 struct uart_port {
8 unsigned long iobase; /* in/out[bwl] */
9 unsigned char *membase; /* read/write[bwl] */
10 unsigned long mapbase; /* for ioremap */
11 enum sh_serial_type type; /* port type */
12 enum sh_clk_mode clk_mode; /* clock mode */
13 };
14
15 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
16 #include <asm/regs306x.h>
17 #endif
18 #if defined(CONFIG_H8S2678)
19 #include <asm/regs267x.h>
20 #endif
21
22 #if defined(CONFIG_CPU_SH7706) || \
23 defined(CONFIG_CPU_SH7707) || \
24 defined(CONFIG_CPU_SH7708) || \
25 defined(CONFIG_CPU_SH7709)
26 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
27 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
28 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
29 #elif defined(CONFIG_CPU_SH7705)
30 # define SCIF0 0xA4400000
31 # define SCIF2 0xA4410000
32 # define SCSMR_Ir 0xA44A0000
33 # define IRDA_SCIF SCIF0
34 # define SCPCR 0xA4000116
35 # define SCPDR 0xA4000136
36
37 /* Set the clock source,
38 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
39 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
40 */
41 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
42 #elif defined(CONFIG_CPU_SH7720) || \
43 defined(CONFIG_CPU_SH7721) || \
44 defined(CONFIG_ARCH_SH7367) || \
45 defined(CONFIG_ARCH_SH7377) || \
46 defined(CONFIG_ARCH_SH7372) || \
47 defined(CONFIG_SH73A0) || \
48 defined(CONFIG_R8A7740)
49 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
50 # define PORT_PTCR 0xA405011EUL
51 # define PORT_PVCR 0xA4050122UL
52 # define SCIF_ORER 0x0200 /* overrun error bit */
53 #elif defined(CONFIG_SH_RTS7751R2D)
54 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
56 # define SCIF_ORER 0x0001 /* overrun error bit */
57 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
58 #elif defined(CONFIG_CPU_SH7750) || \
59 defined(CONFIG_CPU_SH7750R) || \
60 defined(CONFIG_CPU_SH7750S) || \
61 defined(CONFIG_CPU_SH7091) || \
62 defined(CONFIG_CPU_SH7751) || \
63 defined(CONFIG_CPU_SH7751R)
64 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
66 # define SCIF_ORER 0x0001 /* overrun error bit */
67 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
70 #elif defined(CONFIG_CPU_SH7760)
71 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
72 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
73 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
74 # define SCIF_ORER 0x0001 /* overrun error bit */
75 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
76 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
77 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
78 # define SCIF_ORER 0x0001 /* overrun error bit */
79 # define PACR 0xa4050100
80 # define PBCR 0xa4050102
81 # define SCSCR_INIT(port) 0x3B
82 #elif defined(CONFIG_CPU_SH7343)
83 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
84 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
85 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
86 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */
87 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
88 #elif defined(CONFIG_CPU_SH7722)
89 # define PADR 0xA4050120
90 # undef PSDR
91 # define PSDR 0xA405013e
92 # define PWDR 0xA4050166
93 # define PSCR 0xA405011E
94 # define SCIF_ORER 0x0001 /* overrun error bit */
95 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
96 #elif defined(CONFIG_CPU_SH7366)
97 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
98 # define SCSPTR0 SCPDR0
99 # define SCIF_ORER 0x0001 /* overrun error bit */
100 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
101 #elif defined(CONFIG_CPU_SH7723)
102 # define SCSPTR0 0xa4050160
103 # define SCSPTR1 0xa405013e
104 # define SCSPTR2 0xa4050160
105 # define SCSPTR3 0xa405013e
106 # define SCSPTR4 0xa4050128
107 # define SCSPTR5 0xa4050128
108 # define SCIF_ORER 0x0001 /* overrun error bit */
109 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
110 #elif defined(CONFIG_CPU_SH7724)
111 # define SCIF_ORER 0x0001 /* overrun error bit */
112 # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
113 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
114 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
115 #elif defined(CONFIG_CPU_SH7734)
116 # define SCSPTR0 0xFFE40020
117 # define SCSPTR1 0xFFE41020
118 # define SCSPTR2 0xFFE42020
119 # define SCSPTR3 0xFFE43020
120 # define SCSPTR4 0xFFE44020
121 # define SCSPTR5 0xFFE45020
122 # define SCIF_ORER 0x0001 /* overrun error bit */
123 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
124 #elif defined(CONFIG_CPU_SH4_202)
125 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
126 # define SCIF_ORER 0x0001 /* overrun error bit */
127 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
128 #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
129 # define SCIF_BASE_ADDR 0x01030000
130 # define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
131 # define SCIF_PTR2_OFFS 0x0000020
132 # define SCIF_LSR2_OFFS 0x0000024
133 # define SCSPTR\
134 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
135 # define SCLSR2\
136 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
137 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
138 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
139 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
140 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
141 #elif defined(CONFIG_H8S2678)
142 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
143 # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
144 #elif defined(CONFIG_CPU_SH7757) || \
145 defined(CONFIG_CPU_SH7752) || \
146 defined(CONFIG_CPU_SH7753)
147 # define SCSPTR0 0xfe4b0020
148 # define SCSPTR1 0xfe4b0020
149 # define SCSPTR2 0xfe4b0020
150 # define SCIF_ORER 0x0001
151 # define SCSCR_INIT(port) 0x38
152 # define SCIF_ONLY
153 #elif defined(CONFIG_CPU_SH7763)
154 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
155 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
156 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
157 # define SCIF_ORER 0x0001 /* overrun error bit */
158 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
159 #elif defined(CONFIG_CPU_SH7770)
160 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
161 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
162 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
163 # define SCIF_ORER 0x0001 /* overrun error bit */
164 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
165 #elif defined(CONFIG_CPU_SH7780)
166 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
167 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
168 # define SCIF_ORER 0x0001 /* Overrun error bit */
169
170 #if defined(CONFIG_SH_SH2007)
171 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
172 # define SCSCR_INIT(port) 0x38
173 #else
174 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
175 # define SCSCR_INIT(port) 0x3a
176 #endif
177
178 #elif defined(CONFIG_CPU_SH7785) || \
179 defined(CONFIG_CPU_SH7786)
180 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
181 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
182 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
183 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */
184 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */
185 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */
186 # define SCIF_ORER 0x0001 /* Overrun error bit */
187 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
188 #elif defined(CONFIG_CPU_SH7201) || \
189 defined(CONFIG_CPU_SH7203) || \
190 defined(CONFIG_CPU_SH7206) || \
191 defined(CONFIG_CPU_SH7263) || \
192 defined(CONFIG_CPU_SH7264)
193 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
194 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
195 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
196 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
197 # if defined(CONFIG_CPU_SH7201)
198 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
199 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
200 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
201 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
202 # endif
203 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
204 #elif defined(CONFIG_CPU_SH7269)
205 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */
206 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */
207 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */
208 # define SCSPTR3 0xe8008820 /* 16 bit SCIF */
209 # define SCSPTR4 0xe8009020 /* 16 bit SCIF */
210 # define SCSPTR5 0xe8009820 /* 16 bit SCIF */
211 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */
212 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */
213 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
214 #elif defined(CONFIG_CPU_SH7619)
215 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
216 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
217 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
218 # define SCIF_ORER 0x0001 /* overrun error bit */
219 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
220 #elif defined(CONFIG_CPU_SHX3)
221 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */
222 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */
223 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */
224 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */
225 # define SCIF_ORER 0x0001 /* Overrun error bit */
226 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
227 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
228 defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \
229 defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795) || \
230 defined(CONFIG_R8A7796)
231 # if defined(CONFIG_SCIF_A)
232 # define SCIF_ORER 0x0200
233 # else
234 # define SCIF_ORER 0x0001
235 # endif
236 # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
237 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
238 #else
239 # error CPU subtype not defined
240 #endif
241
242 /* SCSCR */
243 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
244 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
245 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
246 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
247 #if defined(CONFIG_CPU_SH7750) || \
248 defined(CONFIG_CPU_SH7091) || \
249 defined(CONFIG_CPU_SH7750R) || \
250 defined(CONFIG_CPU_SH7722) || \
251 defined(CONFIG_CPU_SH7734) || \
252 defined(CONFIG_CPU_SH7750S) || \
253 defined(CONFIG_CPU_SH7751) || \
254 defined(CONFIG_CPU_SH7751R) || \
255 defined(CONFIG_CPU_SH7763) || \
256 defined(CONFIG_CPU_SH7780) || \
257 defined(CONFIG_CPU_SH7785) || \
258 defined(CONFIG_CPU_SH7786) || \
259 defined(CONFIG_CPU_SHX3)
260 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
261 #elif defined(CONFIG_CPU_SH7724)
262 #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
263 #else
264 #define SCI_CTRL_FLAGS_REIE 0
265 #endif
266 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
267 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
268 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
269 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
270
271 /* SCxSR SCI */
272 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
273 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
274 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
275 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
276 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
277 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
278 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
279 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
280
281 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
282
283 /* SCxSR SCIF */
284 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
285 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
286 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
287 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
288 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
289 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
290 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
291 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
292
293 #if defined(CONFIG_CPU_SH7705) || \
294 defined(CONFIG_CPU_SH7720) || \
295 defined(CONFIG_CPU_SH7721) || \
296 defined(CONFIG_ARCH_SH7367) || \
297 defined(CONFIG_ARCH_SH7377) || \
298 defined(CONFIG_ARCH_SH7372) || \
299 defined(CONFIG_SH73A0) || \
300 defined(CONFIG_R8A7740)
301 # define SCIF_ORER 0x0200
302 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
303 # define SCIF_RFDC_MASK 0x007f
304 # define SCIF_TXROOM_MAX 64
305 #elif defined(CONFIG_CPU_SH7763)
306 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
307 # define SCIF_RFDC_MASK 0x007f
308 # define SCIF_TXROOM_MAX 64
309 /* SH7763 SCIF2 support */
310 # define SCIF2_RFDC_MASK 0x001f
311 # define SCIF2_TXROOM_MAX 16
312 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
313 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
314 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
315 # if defined(CONFIG_SCIF_A)
316 # define SCIF_RFDC_MASK 0x007f
317 # else
318 # define SCIF_RFDC_MASK 0x001f
319 # endif
320 #else
321 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
322 # define SCIF_RFDC_MASK 0x001f
323 # define SCIF_TXROOM_MAX 16
324 #endif
325
326 #ifndef SCIF_ORER
327 #define SCIF_ORER 0x0000
328 #endif
329
330 #define SCxSR_TEND(port)\
331 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
332 #define SCxSR_ERRORS(port)\
333 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
334 #define SCxSR_RDxF(port)\
335 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
336 #define SCxSR_TDxE(port)\
337 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
338 #define SCxSR_FER(port)\
339 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
340 #define SCxSR_PER(port)\
341 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
342 #define SCxSR_BRK(port)\
343 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
344 #define SCxSR_ORER(port)\
345 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
346
347 #if defined(CONFIG_CPU_SH7705) || \
348 defined(CONFIG_CPU_SH7720) || \
349 defined(CONFIG_CPU_SH7721) || \
350 defined(CONFIG_ARCH_SH7367) || \
351 defined(CONFIG_ARCH_SH7377) || \
352 defined(CONFIG_ARCH_SH7372) || \
353 defined(CONFIG_SH73A0) || \
354 defined(CONFIG_R8A7740)
355 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
356 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
357 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
358 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
359 #else
360 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
361 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
362 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
363 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
364 #endif
365
366 /* SCFCR */
367 #define SCFCR_RFRST 0x0002
368 #define SCFCR_TFRST 0x0004
369 #define SCFCR_TCRST 0x4000
370 #define SCFCR_MCE 0x0008
371
372 #define SCI_MAJOR 204
373 #define SCI_MINOR_START 8
374
375 /* Generic serial flags */
376 #define SCI_RX_THROTTLE 0x0000001
377
378 #define SCI_MAGIC 0xbabeface
379
380 /*
381 * Events are used to schedule things to happen at timer-interrupt
382 * time, instead of at rs interrupt time.
383 */
384 #define SCI_EVENT_WRITE_WAKEUP 0
385
386 #define SCI_IN(size, offset)\
387 if ((size) == 8) {\
388 return readb(port->membase + (offset));\
389 } else {\
390 return readw(port->membase + (offset));\
391 }
392 #define SCI_OUT(size, offset, value)\
393 if ((size) == 8) {\
394 writeb(value, port->membase + (offset));\
395 } else if ((size) == 16) {\
396 writew(value, port->membase + (offset));\
397 }
398
399 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
400 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
401 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
402 SCI_IN(scif_size, scif_offset)\
403 } else { /* PORT_SCI or PORT_SCIFA */\
404 SCI_IN(sci_size, sci_offset);\
405 }\
406 }\
407 static inline void sci_##name##_out(struct uart_port *port,\
408 unsigned int value) {\
409 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
410 SCI_OUT(scif_size, scif_offset, value)\
411 } else { /* PORT_SCI or PORT_SCIFA */\
412 SCI_OUT(sci_size, sci_offset, value);\
413 }\
414 }
415
416 #ifdef CONFIG_H8300
417 /* h8300 don't have SCIF */
418 #define CPU_SCIF_FNS(name) \
419 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
420 return 0;\
421 }\
422 static inline void sci_##name##_out(struct uart_port *port,\
423 unsigned int value) {\
424 }
425 #else
426 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
427 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
428 SCI_IN(scif_size, scif_offset);\
429 }\
430 static inline void sci_##name##_out(struct uart_port *port,\
431 unsigned int value) {\
432 SCI_OUT(scif_size, scif_offset, value);\
433 }
434 #endif
435
436 #define CPU_SCI_FNS(name, sci_offset, sci_size)\
437 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
438 SCI_IN(sci_size, sci_offset);\
439 }\
440 static inline void sci_##name##_out(struct uart_port *port,\
441 unsigned int value) {\
442 SCI_OUT(sci_size, sci_offset, value);\
443 }
444
445 #if defined(CONFIG_CPU_SH3) || \
446 defined(CONFIG_ARCH_SH7367) || \
447 defined(CONFIG_ARCH_SH7377) || \
448 defined(CONFIG_ARCH_SH7372) || \
449 defined(CONFIG_SH73A0) || \
450 defined(CONFIG_R8A7740)
451 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
452 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
453 sh4_sci_offset, sh4_sci_size, \
454 sh3_scif_offset, sh3_scif_size, \
455 sh4_scif_offset, sh4_scif_size, \
456 h8_sci_offset, h8_sci_size) \
457 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
458 sh4_scif_offset, sh4_scif_size)
459 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
460 sh4_scif_offset, sh4_scif_size) \
461 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
462 #elif defined(CONFIG_CPU_SH7705) || \
463 defined(CONFIG_CPU_SH7720) || \
464 defined(CONFIG_CPU_SH7721) || \
465 defined(CONFIG_ARCH_SH7367) || \
466 defined(CONFIG_ARCH_SH7377) || \
467 defined(CONFIG_SH73A0)
468 #define SCIF_FNS(name, scif_offset, scif_size) \
469 CPU_SCIF_FNS(name, scif_offset, scif_size)
470 #elif defined(CONFIG_ARCH_SH7372) || \
471 defined(CONFIG_R8A7740)
472 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
473 sh4_scifb_offset, sh4_scifb_size) \
474 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
475 sh4_scifb_offset, sh4_scifb_size)
476 #define SCIF_FNS(name, scif_offset, scif_size) \
477 CPU_SCIF_FNS(name, scif_offset, scif_size)
478 #else
479 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
480 sh4_sci_offset, sh4_sci_size, \
481 sh3_scif_offset, sh3_scif_size,\
482 sh4_scif_offset, sh4_scif_size, \
483 h8_sci_offset, h8_sci_size) \
484 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
485 sh3_scif_offset, sh3_scif_size)
486 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
487 sh4_scif_offset, sh4_scif_size) \
488 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
489 #endif
490 #elif defined(__H8300H__) || defined(__H8300S__)
491 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
492 sh4_sci_offset, sh4_sci_size, \
493 sh3_scif_offset, sh3_scif_size,\
494 sh4_scif_offset, sh4_scif_size, \
495 h8_sci_offset, h8_sci_size) \
496 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
497 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
498 sh4_scif_offset, sh4_scif_size) \
499 CPU_SCIF_FNS(name)
500 #elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
501 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
502 sh4_scif_offset, sh4_scif_size) \
503 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
504 sh4_scif_offset, sh4_scif_size)
505 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
506 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
507 #else
508 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
509 sh4_sci_offset, sh4_sci_size, \
510 sh3_scif_offset, sh3_scif_size,\
511 sh4_scif_offset, sh4_scif_size, \
512 h8_sci_offset, h8_sci_size) \
513 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
514 sh4_scif_offset, sh4_scif_size)
515 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
516 sh4_scif_offset, sh4_scif_size) \
517 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
518 #endif
519
520 #if defined(CONFIG_CPU_SH7705) || \
521 defined(CONFIG_CPU_SH7720) || \
522 defined(CONFIG_CPU_SH7721) || \
523 defined(CONFIG_ARCH_SH7367) || \
524 defined(CONFIG_ARCH_SH7377) || \
525 defined(CONFIG_SH73A0)
526
527 SCIF_FNS(SCSMR, 0x00, 16)
528 SCIF_FNS(SCBRR, 0x04, 8)
529 SCIF_FNS(SCSCR, 0x08, 16)
530 SCIF_FNS(SCTDSR, 0x0c, 8)
531 SCIF_FNS(SCFER, 0x10, 16)
532 SCIF_FNS(SCxSR, 0x14, 16)
533 SCIF_FNS(SCFCR, 0x18, 16)
534 SCIF_FNS(SCFDR, 0x1c, 16)
535 SCIF_FNS(SCxTDR, 0x20, 8)
536 SCIF_FNS(SCxRDR, 0x24, 8)
537 SCIF_FNS(SCLSR, 0x00, 0)
538 SCIF_FNS(DL, 0x00, 0) /* dummy */
539 #elif defined(CONFIG_ARCH_SH7372) || \
540 defined(CONFIG_R8A7740)
541 SCIF_FNS(SCSMR, 0x00, 16)
542 SCIF_FNS(SCBRR, 0x04, 8)
543 SCIF_FNS(SCSCR, 0x08, 16)
544 SCIF_FNS(SCTDSR, 0x0c, 16)
545 SCIF_FNS(SCFER, 0x10, 16)
546 SCIF_FNS(SCxSR, 0x14, 16)
547 SCIF_FNS(SCFCR, 0x18, 16)
548 SCIF_FNS(SCFDR, 0x1c, 16)
549 SCIF_FNS(SCTFDR, 0x38, 16)
550 SCIF_FNS(SCRFDR, 0x3c, 16)
551 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
552 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
553 SCIF_FNS(SCLSR, 0x00, 0)
554 SCIF_FNS(DL, 0x00, 0) /* dummy */
555 #elif defined(CONFIG_CPU_SH7723) ||\
556 defined(CONFIG_CPU_SH7724)
557 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
558 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
559 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
560 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
561 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
562 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
563 SCIx_FNS(SCSPTR, 0, 0, 0, 0)
564 SCIF_FNS(SCTDSR, 0x0c, 8)
565 SCIF_FNS(SCFER, 0x10, 16)
566 SCIF_FNS(SCFCR, 0x18, 16)
567 SCIF_FNS(SCFDR, 0x1c, 16)
568 SCIF_FNS(SCLSR, 0x24, 16)
569 SCIF_FNS(DL, 0x00, 0) /* dummy */
570 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
571 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
572 /* SCIFA and SCIF register offsets and size */
573 SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
574 SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0)
575 SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0)
576 SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0)
577 SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0)
578 SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0)
579 SCIF_FNS(SCFCR, 0, 0, 0x18, 16)
580 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
581 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
582 SCIF_FNS(DL, 0, 0, 0x30, 16)
583 SCIF_FNS(CKS, 0, 0, 0x34, 16)
584 #if defined(CONFIG_SCIF_A)
585 SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
586 #else
587 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
588 #endif
589 #else
590 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
591 /* name off sz off sz off sz off sz off sz*/
592 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
593 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
594 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
595 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
596 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
597 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
598 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
599 #if defined(CONFIG_CPU_SH7760) || \
600 defined(CONFIG_CPU_SH7780) || \
601 defined(CONFIG_CPU_SH7785) || \
602 defined(CONFIG_CPU_SH7786)
603 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
604 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
605 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
606 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
607 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
608 #elif defined(CONFIG_CPU_SH7763)
609 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
610 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
611 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
612 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
613 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
614 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
615 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
616 #else
617
618 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
619 #if defined(CONFIG_CPU_SH7722)
620 SCIF_FNS(SCSPTR, 0, 0, 0, 0)
621 #else
622 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
623 #endif
624 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
625 #endif
626 SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
627 #endif
628 #define sci_in(port, reg) sci_##reg##_in(port)
629 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
630
631 /* H8/300 series SCI pins assignment */
632 #if defined(__H8300H__) || defined(__H8300S__)
633 static const struct __attribute__((packed)) {
634 int port; /* GPIO port no */
635 unsigned short rx, tx; /* GPIO bit no */
636 } h8300_sci_pins[] = {
637 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
638 { /* SCI0 */
639 .port = H8300_GPIO_P9,
640 .rx = H8300_GPIO_B2,
641 .tx = H8300_GPIO_B0,
642 },
643 { /* SCI1 */
644 .port = H8300_GPIO_P9,
645 .rx = H8300_GPIO_B3,
646 .tx = H8300_GPIO_B1,
647 },
648 { /* SCI2 */
649 .port = H8300_GPIO_PB,
650 .rx = H8300_GPIO_B7,
651 .tx = H8300_GPIO_B6,
652 }
653 #elif defined(CONFIG_H8S2678)
654 { /* SCI0 */
655 .port = H8300_GPIO_P3,
656 .rx = H8300_GPIO_B2,
657 .tx = H8300_GPIO_B0,
658 },
659 { /* SCI1 */
660 .port = H8300_GPIO_P3,
661 .rx = H8300_GPIO_B3,
662 .tx = H8300_GPIO_B1,
663 },
664 { /* SCI2 */
665 .port = H8300_GPIO_P5,
666 .rx = H8300_GPIO_B1,
667 .tx = H8300_GPIO_B0,
668 }
669 #endif
670 };
671 #endif
672
673 #if defined(CONFIG_CPU_SH7706) || \
674 defined(CONFIG_CPU_SH7707) || \
675 defined(CONFIG_CPU_SH7708) || \
676 defined(CONFIG_CPU_SH7709)
677 static inline int sci_rxd_in(struct uart_port *port)
678 {
679 if (port->mapbase == 0xfffffe80)
680 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
681 return 1;
682 }
683 #elif defined(CONFIG_CPU_SH7750) || \
684 defined(CONFIG_CPU_SH7751) || \
685 defined(CONFIG_CPU_SH7751R) || \
686 defined(CONFIG_CPU_SH7750R) || \
687 defined(CONFIG_CPU_SH7750S) || \
688 defined(CONFIG_CPU_SH7091)
689 static inline int sci_rxd_in(struct uart_port *port)
690 {
691 if (port->mapbase == 0xffe00000)
692 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
693 return 1;
694 }
695 #elif defined(__H8300H__) || defined(__H8300S__)
696 static inline int sci_rxd_in(struct uart_port *port)
697 {
698 int ch = (port->mapbase - SMR0) >> 3;
699 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
700 }
701 #else /* default case for non-SCI processors */
702 static inline int sci_rxd_in(struct uart_port *port)
703 {
704 return 1;
705 }
706 #endif
707
708 /*
709 * Values for the BitRate Register (SCBRR)
710 *
711 * The values are actually divisors for a frequency which can
712 * be internal to the SH3 (14.7456MHz) or derived from an external
713 * clock source. This driver assumes the internal clock is used;
714 * to support using an external clock source, config options or
715 * possibly command-line options would need to be added.
716 *
717 * Also, to support speeds below 2400 (why?) the lower 2 bits of
718 * the SCSMR register would also need to be set to non-zero values.
719 *
720 * -- Greg Banks 27Feb2000
721 *
722 * Answer: The SCBRR register is only eight bits, and the value in
723 * it gets larger with lower baud rates. At around 2400 (depending on
724 * the peripherial module clock) you run out of bits. However the
725 * lower two bits of SCSMR allow the module clock to be divided down,
726 * scaling the value which is needed in SCBRR.
727 *
728 * -- Stuart Menefy - 23 May 2000
729 *
730 * I meant, why would anyone bother with bitrates below 2400.
731 *
732 * -- Greg Banks - 7Jul2000
733 *
734 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
735 * tape reader as a console!
736 *
737 * -- Mitch Davis - 15 Jul 2000
738 */
739
740 #if (defined(CONFIG_CPU_SH7780) || \
741 defined(CONFIG_CPU_SH7785) || \
742 defined(CONFIG_CPU_SH7786)) && \
743 !defined(CONFIG_SH_SH2007)
744 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
745 #elif defined(CONFIG_CPU_SH7705) || \
746 defined(CONFIG_CPU_SH7720) || \
747 defined(CONFIG_CPU_SH7721) || \
748 defined(CONFIG_ARCH_SH7367) || \
749 defined(CONFIG_ARCH_SH7377) || \
750 defined(CONFIG_ARCH_SH7372) || \
751 defined(CONFIG_SH73A0) || \
752 defined(CONFIG_R8A7740)
753 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
754 #elif defined(CONFIG_CPU_SH7723) ||\
755 defined(CONFIG_CPU_SH7724)
756 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
757 {
758 if (port->type == PORT_SCIF)
759 return (clk+16*bps)/(32*bps)-1;
760 else
761 return ((clk*2)+16*bps)/(16*bps)-1;
762 }
763 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
764 #elif defined(__H8300H__) || defined(__H8300S__)
765 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
766 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
767 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
768 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
769 #if defined(CONFIG_SCIF_A)
770 #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
771 #else
772 #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
773 #endif
774 #else /* Generic SH */
775 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
776 #endif
777
778 #ifndef DL_VALUE
779 #define DL_VALUE(bps, clk) 0
780 #endif
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