drivers/sound/max98095.c

   1 /*
   2  * max98095.c -- MAX98095 ALSA SoC Audio driver
   3  *
   4  * Copyright 2011 Maxim Integrated Products
   5  *
   6  * Modified for uboot by R. Chandrasekar (rcsekar@samsung.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <asm/arch/clk.h>
  13 #include <asm/arch/cpu.h>
  14 #include <asm/arch/power.h>
  15 #include <asm/gpio.h>
  16 #include <asm/io.h>
  17 #include <common.h>
  18 #include <div64.h>
  19 #include <fdtdec.h>
  20 #include <i2c.h>
  21 #include <sound.h>
  22 #include "i2s.h"
  23 #include "max98095.h"
  24
  25 enum max98095_type {
  26         MAX98095,
  27 };
  28
  29 struct max98095_priv {
  30         enum max98095_type devtype;
  31         unsigned int sysclk;
  32         unsigned int rate;
  33         unsigned int fmt;
  34 };
  35
  36 static struct sound_codec_info g_codec_info;
  37 struct max98095_priv g_max98095_info;
  38 unsigned int g_max98095_i2c_dev_addr;
  39
  40 /* Index 0 is reserved. */
  41 int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
  42                 88200, 96000};
  43
  44 /*
  45  * Writes value to a device register through i2c
  46  *
  47  * @param reg   reg number to be write
  48  * @param data  data to be writen to the above registor
  49  *
  50  * @return      int value 1 for change, 0 for no change or negative error code.
  51  */
  52 static int max98095_i2c_write(unsigned int reg, unsigned char data)
  53 {
  54         debug("%s: Write Addr : 0x%02X, Data :  0x%02X\n",
  55               __func__, reg, data);
  56         return i2c_write(g_max98095_i2c_dev_addr, reg, 1, &data, 1);
  57 }
  58
  59 /*
  60  * Read a value from a device register through i2c
  61  *
  62  * @param reg   reg number to be read
  63  * @param data  address of read data to be stored
  64  *
  65  * @return      int value 0 for success, -1 in case of error.
  66  */
  67 static unsigned int max98095_i2c_read(unsigned int reg, unsigned char *data)
  68 {
  69         int ret;
  70
  71         ret = i2c_read(g_max98095_i2c_dev_addr, reg, 1, data, 1);
  72         if (ret != 0) {
  73                 debug("%s: Error while reading register %#04x\n",
  74                       __func__, reg);
  75                 return -1;
  76         }
  77
  78         return 0;
  79 }
  80
  81 /*
  82  * update device register bits through i2c
  83  *
  84  * @param reg   codec register
  85  * @param mask  register mask
  86  * @param value new value
  87  *
  88  * @return int value 0 for success, non-zero error code.
  89  */
  90 static int max98095_update_bits(unsigned int reg, unsigned char mask,
  91                                 unsigned char value)
  92 {
  93         int change, ret = 0;
  94         unsigned char old, new;
  95
  96         if (max98095_i2c_read(reg, &old) != 0)
  97                 return -1;
  98         new = (old & ~mask) | (value & mask);
  99         change  = (old != new) ? 1 : 0;
 100         if (change)
 101                 ret = max98095_i2c_write(reg, new);
 102         if (ret < 0)
 103                 return ret;
 104
 105         return change;
 106 }
 107
 108 /*
 109  * codec mclk clock divider coefficients based on sampling rate
 110  *
 111  * @param rate sampling rate
 112  * @param value address of indexvalue to be stored
 113  *
 114  * @return      0 for success or negative error code.
 115  */
 116 static int rate_value(int rate, u8 *value)
 117 {
 118         int i;
 119
 120         for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
 121                 if (rate_table[i] >= rate) {
 122                         *value = i;
 123                         return 0;
 124                 }
 125         }
 126         *value = 1;
 127
 128         return -1;
 129 }
 130
 131 /*
 132  * Sets hw params for max98095
 133  *
 134  * @param max98095      max98095 information pointer
 135  * @param rate          Sampling rate
 136  * @param bits_per_sample       Bits per sample
 137  *
 138  * @return -1 for error  and 0  Success.
 139  */
 140 static int max98095_hw_params(struct max98095_priv *max98095,
 141                               enum en_max_audio_interface aif_id,
 142                               unsigned int rate, unsigned int bits_per_sample)
 143 {
 144         u8 regval;
 145         int error;
 146         unsigned short M98095_DAI_CLKMODE;
 147         unsigned short M98095_DAI_FORMAT;
 148         unsigned short M98095_DAI_FILTERS;
 149
 150         if (aif_id == AIF1) {
 151                 M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE;
 152                 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
 153                 M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS;
 154         } else {
 155                 M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE;
 156                 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
 157                 M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS;
 158         }
 159
 160         switch (bits_per_sample) {
 161         case 16:
 162                 error = max98095_update_bits(M98095_DAI_FORMAT,
 163                                              M98095_DAI_WS, 0);
 164                 break;
 165         case 24:
 166                 error = max98095_update_bits(M98095_DAI_FORMAT,
 167                                              M98095_DAI_WS, M98095_DAI_WS);
 168                 break;
 169         default:
 170                 debug("%s: Illegal bits per sample %d.\n",
 171                       __func__, bits_per_sample);
 172                 return -1;
 173         }
 174
 175         if (rate_value(rate, &regval)) {
 176                 debug("%s: Failed to set sample rate to %d.\n",
 177                       __func__, rate);
 178                 return -1;
 179         }
 180         max98095->rate = rate;
 181
 182         error |= max98095_update_bits(M98095_DAI_CLKMODE,
 183                                       M98095_CLKMODE_MASK, regval);
 184
 185         /* Update sample rate mode */
 186         if (rate < 50000)
 187                 error |= max98095_update_bits(M98095_DAI_FILTERS,
 188                                               M98095_DAI_DHF, 0);
 189         else
 190                 error |= max98095_update_bits(M98095_DAI_FILTERS,
 191                                               M98095_DAI_DHF, M98095_DAI_DHF);
 192
 193         if (error < 0) {
 194                 debug("%s: Error setting hardware params.\n", __func__);
 195                 return -1;
 196         }
 197
 198         return 0;
 199 }
 200
 201 /*
 202  * Configures Audio interface system clock for the given frequency
 203  *
 204  * @param max98095      max98095 information
 205  * @param freq          Sampling frequency in Hz
 206  *
 207  * @return -1 for error and 0 success.
 208  */
 209 static int max98095_set_sysclk(struct max98095_priv *max98095,
 210                                unsigned int freq)
 211 {
 212         int error = 0;
 213
 214         /* Requested clock frequency is already setup */
 215         if (freq == max98095->sysclk)
 216                 return 0;
 217
 218         /* Setup clocks for slave mode, and using the PLL
 219          * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
 220          *      0x02 (when master clk is 20MHz to 40MHz)..
 221          *      0x03 (when master clk is 40MHz to 60MHz)..
 222          */
 223         if ((freq >= 10000000) && (freq < 20000000)) {
 224                 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x10);
 225         } else if ((freq >= 20000000) && (freq < 40000000)) {
 226                 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x20);
 227         } else if ((freq >= 40000000) && (freq < 60000000)) {
 228                 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x30);
 229         } else {
 230                 debug("%s: Invalid master clock frequency\n", __func__);
 231                 return -1;
 232         }
 233
 234         debug("%s: Clock at %uHz\n", __func__, freq);
 235
 236         if (error < 0)
 237                 return -1;
 238
 239         max98095->sysclk = freq;
 240         return 0;
 241 }
 242
 243 /*
 244  * Sets Max98095 I2S format
 245  *
 246  * @param max98095      max98095 information
 247  * @param fmt           i2S format - supports a subset of the options defined
 248  *                      in i2s.h.
 249  *
 250  * @return -1 for error and 0  Success.
 251  */
 252 static int max98095_set_fmt(struct max98095_priv *max98095, int fmt,
 253                             enum en_max_audio_interface aif_id)
 254 {
 255         u8 regval = 0;
 256         int error = 0;
 257         unsigned short M98095_DAI_CLKCFG_HI;
 258         unsigned short M98095_DAI_CLKCFG_LO;
 259         unsigned short M98095_DAI_FORMAT;
 260         unsigned short M98095_DAI_CLOCK;
 261
 262         if (fmt == max98095->fmt)
 263                 return 0;
 264
 265         max98095->fmt = fmt;
 266
 267         if (aif_id == AIF1) {
 268                 M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI;
 269                 M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO;
 270                 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
 271                 M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK;
 272         } else {
 273                 M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI;
 274                 M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO;
 275                 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
 276                 M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK;
 277         }
 278
 279         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 280         case SND_SOC_DAIFMT_CBS_CFS:
 281                 /* Slave mode PLL */
 282                 error |= max98095_i2c_write(M98095_DAI_CLKCFG_HI,
 283                                         0x80);
 284                 error |= max98095_i2c_write(M98095_DAI_CLKCFG_LO,
 285                                         0x00);
 286                 break;
 287         case SND_SOC_DAIFMT_CBM_CFM:
 288                 /* Set to master mode */
 289                 regval |= M98095_DAI_MAS;
 290                 break;
 291         case SND_SOC_DAIFMT_CBS_CFM:
 292         case SND_SOC_DAIFMT_CBM_CFS:
 293         default:
 294                 debug("%s: Clock mode unsupported\n", __func__);
 295                 return -1;
 296         }
 297
 298         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 299         case SND_SOC_DAIFMT_I2S:
 300                 regval |= M98095_DAI_DLY;
 301                 break;
 302         case SND_SOC_DAIFMT_LEFT_J:
 303                 break;
 304         default:
 305                 debug("%s: Unrecognized format.\n", __func__);
 306                 return -1;
 307         }
 308
 309         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 310         case SND_SOC_DAIFMT_NB_NF:
 311                 break;
 312         case SND_SOC_DAIFMT_NB_IF:
 313                 regval |= M98095_DAI_WCI;
 314                 break;
 315         case SND_SOC_DAIFMT_IB_NF:
 316                 regval |= M98095_DAI_BCI;
 317                 break;
 318         case SND_SOC_DAIFMT_IB_IF:
 319                 regval |= M98095_DAI_BCI | M98095_DAI_WCI;
 320                 break;
 321         default:
 322                 debug("%s: Unrecognized inversion settings.\n", __func__);
 323                 return -1;
 324         }
 325
 326         error |= max98095_update_bits(M98095_DAI_FORMAT,
 327                                       M98095_DAI_MAS | M98095_DAI_DLY |
 328                                       M98095_DAI_BCI | M98095_DAI_WCI,
 329                                       regval);
 330
 331         error |= max98095_i2c_write(M98095_DAI_CLOCK,
 332                                     M98095_DAI_BSEL64);
 333
 334         if (error < 0) {
 335                 debug("%s: Error setting i2s format.\n", __func__);
 336                 return -1;
 337         }
 338
 339         return 0;
 340 }
 341
 342 /*
 343  * resets the audio codec
 344  *
 345  * @return -1 for error and 0 success.
 346  */
 347 static int max98095_reset(void)
 348 {
 349         int i, ret;
 350
 351         /*
 352          * Gracefully reset the DSP core and the codec hardware in a proper
 353          * sequence.
 354          */
 355         ret = max98095_i2c_write(M98095_00F_HOST_CFG, 0);
 356         if (ret != 0) {
 357                 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
 358                 return ret;
 359         }
 360
 361         ret = max98095_i2c_write(M98095_097_PWR_SYS, 0);
 362         if (ret != 0) {
 363                 debug("%s: Failed to reset codec: %d\n", __func__, ret);
 364                 return ret;
 365         }
 366
 367         /*
 368          * Reset to hardware default for registers, as there is not a soft
 369          * reset hardware control register.
 370          */
 371         for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
 372                 ret = max98095_i2c_write(i, 0);
 373                 if (ret < 0) {
 374                         debug("%s: Failed to reset: %d\n", __func__, ret);
 375                         return ret;
 376                 }
 377         }
 378
 379         return 0;
 380 }
 381
 382 /*
 383  * Intialise max98095 codec device
 384  *
 385  * @param max98095      max98095 information
 386  *
 387  * @returns -1 for error  and 0 Success.
 388  */
 389 static int max98095_device_init(struct max98095_priv *max98095,
 390                                 enum en_max_audio_interface aif_id)
 391 {
 392         unsigned char id;
 393         int error = 0;
 394
 395         /* reset the codec, the DSP core, and disable all interrupts */
 396         error = max98095_reset();
 397         if (error != 0) {
 398                 debug("Reset\n");
 399                 return error;
 400         }
 401
 402         /* initialize private data */
 403         max98095->sysclk = -1U;
 404         max98095->rate = -1U;
 405         max98095->fmt = -1U;
 406
 407         error = max98095_i2c_read(M98095_0FF_REV_ID, &id);
 408         if (error < 0) {
 409                 debug("%s: Failure reading hardware revision: %d\n",
 410                       __func__, id);
 411                 goto err_access;
 412         }
 413         debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
 414
 415         error |= max98095_i2c_write(M98095_097_PWR_SYS, M98095_PWRSV);
 416
 417         /*
 418          * initialize registers to hardware default configuring audio
 419          * interface2 to DAC
 420          */
 421         if (aif_id == AIF1)
 422                 error |= max98095_i2c_write(M98095_048_MIX_DAC_LR,
 423                                             M98095_DAI1L_TO_DACL |
 424                                             M98095_DAI1R_TO_DACR);
 425         else
 426                 error |= max98095_i2c_write(M98095_048_MIX_DAC_LR,
 427                                             M98095_DAI2M_TO_DACL |
 428                                             M98095_DAI2M_TO_DACR);
 429
 430         error |= max98095_i2c_write(M98095_092_PWR_EN_OUT,
 431                                     M98095_SPK_SPREADSPECTRUM);
 432         error |= max98095_i2c_write(M98095_04E_CFG_HP, M98095_HPNORMAL);
 433         if (aif_id == AIF1)
 434                 error |= max98095_i2c_write(M98095_02C_DAI1_IOCFG,
 435                                             M98095_S1NORMAL | M98095_SDATA);
 436         else
 437                 error |= max98095_i2c_write(M98095_036_DAI2_IOCFG,
 438                                             M98095_S2NORMAL | M98095_SDATA);
 439
 440         /* take the codec out of the shut down */
 441         error |= max98095_update_bits(M98095_097_PWR_SYS, M98095_SHDNRUN,
 442                                       M98095_SHDNRUN);
 443         /* route DACL and DACR output to HO and Spekers */
 444         error |= max98095_i2c_write(M98095_050_MIX_SPK_LEFT, 0x01); /* DACL */
 445         error |= max98095_i2c_write(M98095_051_MIX_SPK_RIGHT, 0x01);/* DACR */
 446         error |= max98095_i2c_write(M98095_04C_MIX_HP_LEFT, 0x01);  /* DACL */
 447         error |= max98095_i2c_write(M98095_04D_MIX_HP_RIGHT, 0x01); /* DACR */
 448
 449         /* power Enable */
 450         error |= max98095_i2c_write(M98095_091_PWR_EN_OUT, 0xF3);
 451
 452         /* set Volume */
 453         error |= max98095_i2c_write(M98095_064_LVL_HP_L, 15);
 454         error |= max98095_i2c_write(M98095_065_LVL_HP_R, 15);
 455         error |= max98095_i2c_write(M98095_067_LVL_SPK_L, 16);
 456         error |= max98095_i2c_write(M98095_068_LVL_SPK_R, 16);
 457
 458         /* Enable DAIs */
 459         error |= max98095_i2c_write(M98095_093_BIAS_CTRL, 0x30);
 460         if (aif_id == AIF1)
 461                 error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x01);
 462         else
 463                 error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x07);
 464
 465 err_access:
 466         if (error < 0)
 467                 return -1;
 468
 469         return 0;
 470 }
 471
 472 static int max98095_do_init(struct sound_codec_info *pcodec_info,
 473                             enum en_max_audio_interface aif_id,
 474                             int sampling_rate, int mclk_freq,
 475                             int bits_per_sample)
 476 {
 477         int ret = 0;
 478
 479         /* Enable codec clock */
 480         set_xclkout();
 481
 482         /* shift the device address by 1 for 7 bit addressing */
 483         g_max98095_i2c_dev_addr = pcodec_info->i2c_dev_addr >> 1;
 484
 485         if (pcodec_info->codec_type == CODEC_MAX_98095) {
 486                 g_max98095_info.devtype = MAX98095;
 487         } else {
 488                 debug("%s: Codec id [%d] not defined\n", __func__,
 489                       pcodec_info->codec_type);
 490                 return -1;
 491         }
 492
 493         ret = max98095_device_init(&g_max98095_info, aif_id);
 494         if (ret < 0) {
 495                 debug("%s: max98095 codec chip init failed\n", __func__);
 496                 return ret;
 497         }
 498
 499         ret = max98095_set_sysclk(&g_max98095_info, mclk_freq);
 500         if (ret < 0) {
 501                 debug("%s: max98095 codec set sys clock failed\n", __func__);
 502                 return ret;
 503         }
 504
 505         ret = max98095_hw_params(&g_max98095_info, aif_id, sampling_rate,
 506                                  bits_per_sample);
 507
 508         if (ret == 0) {
 509                 ret = max98095_set_fmt(&g_max98095_info,
 510                                        SND_SOC_DAIFMT_I2S |
 511                                        SND_SOC_DAIFMT_NB_NF |
 512                                        SND_SOC_DAIFMT_CBS_CFS,
 513                                        aif_id);
 514         }
 515
 516         return ret;
 517 }
 518
 519 static int get_max98095_codec_values(struct sound_codec_info *pcodec_info,
 520                                 const void *blob)
 521 {
 522         int error = 0;
 523 #if CONFIG_IS_ENABLED(OF_CONTROL)
 524         enum fdt_compat_id compat;
 525         int node;
 526         int parent;
 527
 528         /* Get the node from FDT for codec */
 529         node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_98095_CODEC);
 530         if (node <= 0) {
 531                 debug("EXYNOS_SOUND: No node for codec in device tree\n");
 532                 debug("node = %d\n", node);
 533                 return -1;
 534         }
 535
 536         parent = fdt_parent_offset(blob, node);
 537         if (parent < 0) {
 538                 debug("%s: Cannot find node parent\n", __func__);
 539                 return -1;
 540         }
 541
 542         compat = fdtdec_lookup(blob, parent);
 543         switch (compat) {
 544         case COMPAT_SAMSUNG_S3C2440_I2C:
 545                 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
 546                 error |= pcodec_info->i2c_bus;
 547                 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
 548                 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
 549                                                         "reg", 0);
 550                 error |= pcodec_info->i2c_dev_addr;
 551                 debug("i2c dev addr = %x\n", pcodec_info->i2c_dev_addr);
 552                 break;
 553         default:
 554                 debug("%s: Unknown compat id %d\n", __func__, compat);
 555                 return -1;
 556         }
 557 #else
 558         pcodec_info->i2c_bus = AUDIO_I2C_BUS;
 559         pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
 560         debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
 561 #endif
 562         pcodec_info->codec_type = CODEC_MAX_98095;
 563         if (error == -1) {
 564                 debug("fail to get max98095 codec node properties\n");
 565                 return -1;
 566         }
 567
 568         return 0;
 569 }
 570
 571 /* max98095 Device Initialisation */
 572 int max98095_init(const void *blob, enum en_max_audio_interface aif_id,
 573                   int sampling_rate, int mclk_freq,
 574                   int bits_per_sample)
 575 {
 576         int ret;
 577         int old_bus = i2c_get_bus_num();
 578         struct sound_codec_info *pcodec_info = &g_codec_info;
 579
 580         if (get_max98095_codec_values(pcodec_info, blob) < 0) {
 581                 debug("FDT Codec values failed\n");
 582                 return -1;
 583         }
 584
 585         i2c_set_bus_num(pcodec_info->i2c_bus);
 586         ret = max98095_do_init(pcodec_info, aif_id, sampling_rate, mclk_freq,
 587                                bits_per_sample);
 588         i2c_set_bus_num(old_bus);
 589
 590         return ret;
 591 }