3 * Altera Corporation <www.altera.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/errno.h>
14 #include "cadence_qspi.h"
16 #define CQSPI_STIG_READ 0
17 #define CQSPI_STIG_WRITE 1
18 #define CQSPI_INDIRECT_READ 2
19 #define CQSPI_INDIRECT_WRITE 3
21 DECLARE_GLOBAL_DATA_PTR
;
23 static int cadence_spi_write_speed(struct udevice
*bus
, uint hz
)
25 struct cadence_spi_platdata
*plat
= bus
->platdata
;
26 struct cadence_spi_priv
*priv
= dev_get_priv(bus
);
28 cadence_qspi_apb_config_baudrate_div(priv
->regbase
,
29 CONFIG_CQSPI_REF_CLK
, hz
);
31 /* Reconfigure delay timing if speed is changed. */
32 cadence_qspi_apb_delay(priv
->regbase
, CONFIG_CQSPI_REF_CLK
, hz
,
33 plat
->tshsl_ns
, plat
->tsd2d_ns
,
34 plat
->tchsh_ns
, plat
->tslch_ns
);
39 /* Calibration sequence to determine the read data capture delay register */
40 static int spi_calibration(struct udevice
*bus
, uint hz
)
42 struct cadence_spi_priv
*priv
= dev_get_priv(bus
);
43 void *base
= priv
->regbase
;
44 u8 opcode_rdid
= 0x9F;
45 unsigned int idcode
= 0, temp
= 0;
46 int err
= 0, i
, range_lo
= -1, range_hi
= -1;
48 /* start with slowest clock (1 MHz) */
49 cadence_spi_write_speed(bus
, 1000000);
51 /* configure the read data capture delay register to 0 */
52 cadence_qspi_apb_readdata_capture(base
, 1, 0);
55 cadence_qspi_apb_controller_enable(base
);
57 /* read the ID which will be our golden value */
58 err
= cadence_qspi_apb_command_read(base
, 1, &opcode_rdid
,
61 puts("SF: Calibration failed (read)\n");
65 /* use back the intended clock and find low range */
66 cadence_spi_write_speed(bus
, hz
);
67 for (i
= 0; i
< CQSPI_READ_CAPTURE_MAX_DELAY
; i
++) {
69 cadence_qspi_apb_controller_disable(base
);
71 /* reconfigure the read data capture delay register */
72 cadence_qspi_apb_readdata_capture(base
, 1, i
);
74 /* Enable back QSPI */
75 cadence_qspi_apb_controller_enable(base
);
77 /* issue a RDID to get the ID value */
78 err
= cadence_qspi_apb_command_read(base
, 1, &opcode_rdid
,
81 puts("SF: Calibration failed (read)\n");
85 /* search for range lo */
86 if (range_lo
== -1 && temp
== idcode
) {
91 /* search for range hi */
92 if (range_lo
!= -1 && temp
!= idcode
) {
100 puts("SF: Calibration failed (low range)\n");
104 /* Disable QSPI for subsequent initialization */
105 cadence_qspi_apb_controller_disable(base
);
107 /* configure the final value for read data capture delay register */
108 cadence_qspi_apb_readdata_capture(base
, 1, (range_hi
+ range_lo
) / 2);
109 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
110 (range_hi
+ range_lo
) / 2, range_lo
, range_hi
);
112 /* just to ensure we do once only when speed or chip select change */
113 priv
->qspi_calibrated_hz
= hz
;
114 priv
->qspi_calibrated_cs
= spi_chip_select(bus
);
119 static int cadence_spi_set_speed(struct udevice
*bus
, uint hz
)
121 struct cadence_spi_platdata
*plat
= bus
->platdata
;
122 struct cadence_spi_priv
*priv
= dev_get_priv(bus
);
125 if (hz
> plat
->max_hz
)
129 cadence_qspi_apb_controller_disable(priv
->regbase
);
132 * Calibration required for different current SCLK speed, requested
133 * SCLK speed or chip select
135 if (priv
->previous_hz
!= hz
||
136 priv
->qspi_calibrated_hz
!= hz
||
137 priv
->qspi_calibrated_cs
!= spi_chip_select(bus
)) {
138 err
= spi_calibration(bus
, hz
);
142 /* prevent calibration run when same as previous request */
143 priv
->previous_hz
= hz
;
147 cadence_qspi_apb_controller_enable(priv
->regbase
);
149 debug("%s: speed=%d\n", __func__
, hz
);
154 static int cadence_spi_probe(struct udevice
*bus
)
156 struct cadence_spi_platdata
*plat
= bus
->platdata
;
157 struct cadence_spi_priv
*priv
= dev_get_priv(bus
);
159 priv
->regbase
= plat
->regbase
;
160 priv
->ahbbase
= plat
->ahbbase
;
162 if (!priv
->qspi_is_init
) {
163 cadence_qspi_apb_controller_init(plat
);
164 priv
->qspi_is_init
= 1;
170 static int cadence_spi_set_mode(struct udevice
*bus
, uint mode
)
172 struct cadence_spi_priv
*priv
= dev_get_priv(bus
);
175 cadence_qspi_apb_controller_disable(priv
->regbase
);
178 cadence_qspi_apb_set_clk_mode(priv
->regbase
, mode
);
181 cadence_qspi_apb_controller_enable(priv
->regbase
);
186 static int cadence_spi_xfer(struct udevice
*dev
, unsigned int bitlen
,
187 const void *dout
, void *din
, unsigned long flags
)
189 struct udevice
*bus
= dev
->parent
;
190 struct cadence_spi_platdata
*plat
= bus
->platdata
;
191 struct cadence_spi_priv
*priv
= dev_get_priv(bus
);
192 struct dm_spi_slave_platdata
*dm_plat
= dev_get_parent_platdata(dev
);
193 void *base
= priv
->regbase
;
194 u8
*cmd_buf
= priv
->cmd_buf
;
197 u32 mode
= CQSPI_STIG_WRITE
;
199 if (flags
& SPI_XFER_BEGIN
) {
200 /* copy command to local buffer */
201 priv
->cmd_len
= bitlen
/ 8;
202 memcpy(cmd_buf
, dout
, priv
->cmd_len
);
205 if (flags
== (SPI_XFER_BEGIN
| SPI_XFER_END
)) {
206 /* if start and end bit are set, the data bytes is 0. */
209 data_bytes
= bitlen
/ 8;
211 debug("%s: len=%d [bytes]\n", __func__
, data_bytes
);
213 /* Set Chip select */
214 cadence_qspi_apb_chipselect(base
, spi_chip_select(dev
),
215 plat
->is_decoded_cs
);
217 if ((flags
& SPI_XFER_END
) || (flags
== 0)) {
218 if (priv
->cmd_len
== 0) {
219 printf("QSPI: Error, command is empty.\n");
223 if (din
&& data_bytes
) {
225 /* Use STIG if no address. */
226 if (!CQSPI_IS_ADDR(priv
->cmd_len
))
227 mode
= CQSPI_STIG_READ
;
229 mode
= CQSPI_INDIRECT_READ
;
230 } else if (dout
&& !(flags
& SPI_XFER_BEGIN
)) {
232 if (!CQSPI_IS_ADDR(priv
->cmd_len
))
233 mode
= CQSPI_STIG_WRITE
;
235 mode
= CQSPI_INDIRECT_WRITE
;
239 case CQSPI_STIG_READ
:
240 err
= cadence_qspi_apb_command_read(
241 base
, priv
->cmd_len
, cmd_buf
,
245 case CQSPI_STIG_WRITE
:
246 err
= cadence_qspi_apb_command_write(base
,
247 priv
->cmd_len
, cmd_buf
,
250 case CQSPI_INDIRECT_READ
:
251 err
= cadence_qspi_apb_indirect_read_setup(plat
,
252 priv
->cmd_len
, dm_plat
->mode
, cmd_buf
);
254 err
= cadence_qspi_apb_indirect_read_execute
255 (plat
, data_bytes
, din
);
258 case CQSPI_INDIRECT_WRITE
:
259 err
= cadence_qspi_apb_indirect_write_setup
260 (plat
, priv
->cmd_len
, cmd_buf
);
262 err
= cadence_qspi_apb_indirect_write_execute
263 (plat
, data_bytes
, dout
);
271 if (flags
& SPI_XFER_END
) {
272 /* clear command buffer */
273 memset(cmd_buf
, 0, sizeof(priv
->cmd_buf
));
281 static int cadence_spi_ofdata_to_platdata(struct udevice
*bus
)
283 struct cadence_spi_platdata
*plat
= bus
->platdata
;
284 const void *blob
= gd
->fdt_blob
;
285 int node
= dev_of_offset(bus
);
290 /* 2 base addresses are needed, lets get them from the DT */
291 ret
= fdtdec_get_int_array(blob
, node
, "reg", data
, ARRAY_SIZE(data
));
293 printf("Error: Can't get base addresses (ret=%d)!\n", ret
);
297 plat
->regbase
= (void *)data
[0];
298 plat
->ahbbase
= (void *)data
[2];
299 plat
->is_decoded_cs
= fdtdec_get_bool(blob
, node
, "cdns,is-decoded-cs");
300 plat
->fifo_depth
= fdtdec_get_uint(blob
, node
, "cdns,fifo-depth", 128);
301 plat
->fifo_width
= fdtdec_get_uint(blob
, node
, "cdns,fifo-width", 4);
302 plat
->trigger_address
= fdtdec_get_uint(blob
, node
,
303 "cdns,trigger-address", 0);
305 /* All other paramters are embedded in the child node */
306 subnode
= fdt_first_subnode(blob
, node
);
308 printf("Error: subnode with SPI flash config missing!\n");
312 /* Use 500 KHz as a suitable default */
313 plat
->max_hz
= fdtdec_get_uint(blob
, subnode
, "spi-max-frequency",
316 /* Read other parameters from DT */
317 plat
->page_size
= fdtdec_get_uint(blob
, subnode
, "page-size", 256);
318 plat
->block_size
= fdtdec_get_uint(blob
, subnode
, "block-size", 16);
319 plat
->tshsl_ns
= fdtdec_get_uint(blob
, subnode
, "cdns,tshsl-ns", 200);
320 plat
->tsd2d_ns
= fdtdec_get_uint(blob
, subnode
, "cdns,tsd2d-ns", 255);
321 plat
->tchsh_ns
= fdtdec_get_uint(blob
, subnode
, "cdns,tchsh-ns", 20);
322 plat
->tslch_ns
= fdtdec_get_uint(blob
, subnode
, "cdns,tslch-ns", 20);
324 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
325 __func__
, plat
->regbase
, plat
->ahbbase
, plat
->max_hz
,
331 static const struct dm_spi_ops cadence_spi_ops
= {
332 .xfer
= cadence_spi_xfer
,
333 .set_speed
= cadence_spi_set_speed
,
334 .set_mode
= cadence_spi_set_mode
,
336 * cs_info is not needed, since we require all chip selects to be
337 * in the device tree explicitly
341 static const struct udevice_id cadence_spi_ids
[] = {
342 { .compatible
= "cadence,qspi" },
346 U_BOOT_DRIVER(cadence_spi
) = {
347 .name
= "cadence_spi",
349 .of_match
= cadence_spi_ids
,
350 .ops
= &cadence_spi_ops
,
351 .ofdata_to_platdata
= cadence_spi_ofdata_to_platdata
,
352 .platdata_auto_alloc_size
= sizeof(struct cadence_spi_platdata
),
353 .priv_auto_alloc_size
= sizeof(struct cadence_spi_priv
),
354 .probe
= cadence_spi_probe
,