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spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
[people/ms/u-boot.git] / drivers / spi / cadence_qspi_apb.c
1 /*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * - Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * - Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * - Neither the name of the Altera Corporation nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <common.h>
29 #include <asm/io.h>
30 #include <linux/errno.h>
31 #include <wait_bit.h>
32 #include <spi.h>
33 #include <bouncebuf.h>
34 #include "cadence_qspi.h"
35
36 #define CQSPI_REG_POLL_US 1 /* 1us */
37 #define CQSPI_REG_RETRY 10000
38 #define CQSPI_POLL_IDLE_RETRY 3
39
40 #define CQSPI_FIFO_WIDTH 4
41
42 #define CQSPI_REG_SRAM_THRESHOLD_WORDS 50
43
44 /* Transfer mode */
45 #define CQSPI_INST_TYPE_SINGLE 0
46 #define CQSPI_INST_TYPE_DUAL 1
47 #define CQSPI_INST_TYPE_QUAD 2
48
49 #define CQSPI_STIG_DATA_LEN_MAX 8
50
51 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
52 #define CQSPI_DUMMY_BYTES_MAX 4
53
54 #define CQSPI_REG_SRAM_FILL_THRESHOLD \
55 ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
56
57 /****************************************************************************
58 * Controller's configuration and status register (offset from QSPI_BASE)
59 ****************************************************************************/
60 #define CQSPI_REG_CONFIG 0x00
61 #define CQSPI_REG_CONFIG_ENABLE BIT(0)
62 #define CQSPI_REG_CONFIG_CLK_POL BIT(1)
63 #define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
64 #define CQSPI_REG_CONFIG_DIRECT BIT(7)
65 #define CQSPI_REG_CONFIG_DECODE BIT(9)
66 #define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
67 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
68 #define CQSPI_REG_CONFIG_BAUD_LSB 19
69 #define CQSPI_REG_CONFIG_IDLE_LSB 31
70 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
71 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
72
73 #define CQSPI_REG_RD_INSTR 0x04
74 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
75 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
76 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
77 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
78 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
79 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
80 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
81 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
82 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
83 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
84
85 #define CQSPI_REG_WR_INSTR 0x08
86 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
87
88 #define CQSPI_REG_DELAY 0x0C
89 #define CQSPI_REG_DELAY_TSLCH_LSB 0
90 #define CQSPI_REG_DELAY_TCHSH_LSB 8
91 #define CQSPI_REG_DELAY_TSD2D_LSB 16
92 #define CQSPI_REG_DELAY_TSHSL_LSB 24
93 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
94 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
95 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
96 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
97
98 #define CQSPI_REG_RD_DATA_CAPTURE 0x10
99 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
100 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
101 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
102
103 #define CQSPI_REG_SIZE 0x14
104 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
105 #define CQSPI_REG_SIZE_PAGE_LSB 4
106 #define CQSPI_REG_SIZE_BLOCK_LSB 16
107 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
108 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
109 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
110
111 #define CQSPI_REG_SRAMPARTITION 0x18
112 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
113
114 #define CQSPI_REG_REMAP 0x24
115 #define CQSPI_REG_MODE_BIT 0x28
116
117 #define CQSPI_REG_SDRAMLEVEL 0x2C
118 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
119 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
120 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
121 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
122
123 #define CQSPI_REG_IRQSTATUS 0x40
124 #define CQSPI_REG_IRQMASK 0x44
125
126 #define CQSPI_REG_INDIRECTRD 0x60
127 #define CQSPI_REG_INDIRECTRD_START BIT(0)
128 #define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
129 #define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
130 #define CQSPI_REG_INDIRECTRD_DONE BIT(5)
131
132 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
133 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
134 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
135
136 #define CQSPI_REG_CMDCTRL 0x90
137 #define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
138 #define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
139 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
140 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
141 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
142 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
143 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
144 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
145 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
146 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
147 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
148 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
149 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
150 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
151 #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
152
153 #define CQSPI_REG_INDIRECTWR 0x70
154 #define CQSPI_REG_INDIRECTWR_START BIT(0)
155 #define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
156 #define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
157 #define CQSPI_REG_INDIRECTWR_DONE BIT(5)
158
159 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
160 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
161 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
162
163 #define CQSPI_REG_CMDADDRESS 0x94
164 #define CQSPI_REG_CMDREADDATALOWER 0xA0
165 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
166 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
167 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
168
169 #define CQSPI_REG_IS_IDLE(base) \
170 ((readl(base + CQSPI_REG_CONFIG) >> \
171 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
172
173 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
174 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
175 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
176
177 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
178 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
179 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
180
181 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
182 unsigned int addr_width)
183 {
184 unsigned int addr;
185
186 addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
187
188 if (addr_width == 4)
189 addr = (addr << 8) | addr_buf[3];
190
191 return addr;
192 }
193
194 void cadence_qspi_apb_controller_enable(void *reg_base)
195 {
196 unsigned int reg;
197 reg = readl(reg_base + CQSPI_REG_CONFIG);
198 reg |= CQSPI_REG_CONFIG_ENABLE;
199 writel(reg, reg_base + CQSPI_REG_CONFIG);
200 }
201
202 void cadence_qspi_apb_controller_disable(void *reg_base)
203 {
204 unsigned int reg;
205 reg = readl(reg_base + CQSPI_REG_CONFIG);
206 reg &= ~CQSPI_REG_CONFIG_ENABLE;
207 writel(reg, reg_base + CQSPI_REG_CONFIG);
208 }
209
210 /* Return 1 if idle, otherwise return 0 (busy). */
211 static unsigned int cadence_qspi_wait_idle(void *reg_base)
212 {
213 unsigned int start, count = 0;
214 /* timeout in unit of ms */
215 unsigned int timeout = 5000;
216
217 start = get_timer(0);
218 for ( ; get_timer(start) < timeout ; ) {
219 if (CQSPI_REG_IS_IDLE(reg_base))
220 count++;
221 else
222 count = 0;
223 /*
224 * Ensure the QSPI controller is in true idle state after
225 * reading back the same idle status consecutively
226 */
227 if (count >= CQSPI_POLL_IDLE_RETRY)
228 return 1;
229 }
230
231 /* Timeout, still in busy mode. */
232 printf("QSPI: QSPI is still busy after poll for %d times.\n",
233 CQSPI_REG_RETRY);
234 return 0;
235 }
236
237 void cadence_qspi_apb_readdata_capture(void *reg_base,
238 unsigned int bypass, unsigned int delay)
239 {
240 unsigned int reg;
241 cadence_qspi_apb_controller_disable(reg_base);
242
243 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
244
245 if (bypass)
246 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
247 else
248 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
249
250 reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
251 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
252
253 reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
254 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
255
256 writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
257
258 cadence_qspi_apb_controller_enable(reg_base);
259 }
260
261 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
262 unsigned int ref_clk_hz, unsigned int sclk_hz)
263 {
264 unsigned int reg;
265 unsigned int div;
266
267 cadence_qspi_apb_controller_disable(reg_base);
268 reg = readl(reg_base + CQSPI_REG_CONFIG);
269 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
270
271 /*
272 * The baud_div field in the config reg is 4 bits, and the ref clock is
273 * divided by 2 * (baud_div + 1). Round up the divider to ensure the
274 * SPI clock rate is less than or equal to the requested clock rate.
275 */
276 div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
277
278 /* ensure the baud rate doesn't exceed the max value */
279 if (div > CQSPI_REG_CONFIG_BAUD_MASK)
280 div = CQSPI_REG_CONFIG_BAUD_MASK;
281
282 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
283 ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
284
285 reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
286 writel(reg, reg_base + CQSPI_REG_CONFIG);
287
288 cadence_qspi_apb_controller_enable(reg_base);
289 }
290
291 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
292 {
293 unsigned int reg;
294
295 cadence_qspi_apb_controller_disable(reg_base);
296 reg = readl(reg_base + CQSPI_REG_CONFIG);
297 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
298
299 if (mode & SPI_CPOL)
300 reg |= CQSPI_REG_CONFIG_CLK_POL;
301 if (mode & SPI_CPHA)
302 reg |= CQSPI_REG_CONFIG_CLK_PHA;
303
304 writel(reg, reg_base + CQSPI_REG_CONFIG);
305
306 cadence_qspi_apb_controller_enable(reg_base);
307 }
308
309 void cadence_qspi_apb_chipselect(void *reg_base,
310 unsigned int chip_select, unsigned int decoder_enable)
311 {
312 unsigned int reg;
313
314 cadence_qspi_apb_controller_disable(reg_base);
315
316 debug("%s : chipselect %d decode %d\n", __func__, chip_select,
317 decoder_enable);
318
319 reg = readl(reg_base + CQSPI_REG_CONFIG);
320 /* docoder */
321 if (decoder_enable) {
322 reg |= CQSPI_REG_CONFIG_DECODE;
323 } else {
324 reg &= ~CQSPI_REG_CONFIG_DECODE;
325 /* Convert CS if without decoder.
326 * CS0 to 4b'1110
327 * CS1 to 4b'1101
328 * CS2 to 4b'1011
329 * CS3 to 4b'0111
330 */
331 chip_select = 0xF & ~(1 << chip_select);
332 }
333
334 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
335 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
336 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
337 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
338 writel(reg, reg_base + CQSPI_REG_CONFIG);
339
340 cadence_qspi_apb_controller_enable(reg_base);
341 }
342
343 void cadence_qspi_apb_delay(void *reg_base,
344 unsigned int ref_clk, unsigned int sclk_hz,
345 unsigned int tshsl_ns, unsigned int tsd2d_ns,
346 unsigned int tchsh_ns, unsigned int tslch_ns)
347 {
348 unsigned int ref_clk_ns;
349 unsigned int sclk_ns;
350 unsigned int tshsl, tchsh, tslch, tsd2d;
351 unsigned int reg;
352
353 cadence_qspi_apb_controller_disable(reg_base);
354
355 /* Convert to ns. */
356 ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
357
358 /* Convert to ns. */
359 sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
360
361 /* The controller adds additional delay to that programmed in the reg */
362 if (tshsl_ns >= sclk_ns + ref_clk_ns)
363 tshsl_ns -= sclk_ns + ref_clk_ns;
364 if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
365 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
366 tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
367 tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
368 tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
369 tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
370
371 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
372 << CQSPI_REG_DELAY_TSHSL_LSB);
373 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
374 << CQSPI_REG_DELAY_TCHSH_LSB);
375 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
376 << CQSPI_REG_DELAY_TSLCH_LSB);
377 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
378 << CQSPI_REG_DELAY_TSD2D_LSB);
379 writel(reg, reg_base + CQSPI_REG_DELAY);
380
381 cadence_qspi_apb_controller_enable(reg_base);
382 }
383
384 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
385 {
386 unsigned reg;
387
388 cadence_qspi_apb_controller_disable(plat->regbase);
389
390 /* Configure the device size and address bytes */
391 reg = readl(plat->regbase + CQSPI_REG_SIZE);
392 /* Clear the previous value */
393 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
394 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
395 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
396 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
397 writel(reg, plat->regbase + CQSPI_REG_SIZE);
398
399 /* Configure the remap address register, no remap */
400 writel(0, plat->regbase + CQSPI_REG_REMAP);
401
402 /* Indirect mode configurations */
403 writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
404
405 /* Disable all interrupts */
406 writel(0, plat->regbase + CQSPI_REG_IRQMASK);
407
408 cadence_qspi_apb_controller_enable(plat->regbase);
409 }
410
411 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
412 unsigned int reg)
413 {
414 unsigned int retry = CQSPI_REG_RETRY;
415
416 /* Write the CMDCTRL without start execution. */
417 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
418 /* Start execute */
419 reg |= CQSPI_REG_CMDCTRL_EXECUTE;
420 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
421
422 while (retry--) {
423 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
424 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
425 break;
426 udelay(1);
427 }
428
429 if (!retry) {
430 printf("QSPI: flash command execution timeout\n");
431 return -EIO;
432 }
433
434 /* Polling QSPI idle status. */
435 if (!cadence_qspi_wait_idle(reg_base))
436 return -EIO;
437
438 return 0;
439 }
440
441 /* For command RDID, RDSR. */
442 int cadence_qspi_apb_command_read(void *reg_base,
443 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
444 u8 *rxbuf)
445 {
446 unsigned int reg;
447 unsigned int read_len;
448 int status;
449
450 if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
451 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
452 cmdlen, rxlen);
453 return -EINVAL;
454 }
455
456 reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
457
458 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
459
460 /* 0 means 1 byte. */
461 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
462 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
463 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
464 if (status != 0)
465 return status;
466
467 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
468
469 /* Put the read value into rx_buf */
470 read_len = (rxlen > 4) ? 4 : rxlen;
471 memcpy(rxbuf, &reg, read_len);
472 rxbuf += read_len;
473
474 if (rxlen > 4) {
475 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
476
477 read_len = rxlen - read_len;
478 memcpy(rxbuf, &reg, read_len);
479 }
480 return 0;
481 }
482
483 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
484 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
485 const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf)
486 {
487 unsigned int reg = 0;
488 unsigned int addr_value;
489 unsigned int wr_data;
490 unsigned int wr_len;
491
492 if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
493 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
494 cmdlen, txlen);
495 return -EINVAL;
496 }
497
498 reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
499
500 if (cmdlen == 4 || cmdlen == 5) {
501 /* Command with address */
502 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
503 /* Number of bytes to write. */
504 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
505 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
506 /* Get address */
507 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
508 cmdlen >= 5 ? 4 : 3);
509
510 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
511 }
512
513 if (txlen) {
514 /* writing data = yes */
515 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
516 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
517 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
518
519 wr_len = txlen > 4 ? 4 : txlen;
520 memcpy(&wr_data, txbuf, wr_len);
521 writel(wr_data, reg_base +
522 CQSPI_REG_CMDWRITEDATALOWER);
523
524 if (txlen > 4) {
525 txbuf += wr_len;
526 wr_len = txlen - wr_len;
527 memcpy(&wr_data, txbuf, wr_len);
528 writel(wr_data, reg_base +
529 CQSPI_REG_CMDWRITEDATAUPPER);
530 }
531 }
532
533 /* Execute the command */
534 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
535 }
536
537 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
538 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
539 unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
540 {
541 unsigned int reg;
542 unsigned int rd_reg;
543 unsigned int addr_value;
544 unsigned int dummy_clk;
545 unsigned int dummy_bytes;
546 unsigned int addr_bytes;
547
548 /*
549 * Identify addr_byte. All NOR flash device drivers are using fast read
550 * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
551 * With that, the length is in value of 5 or 6. Only FRAM chip from
552 * ramtron using normal read (which won't need dummy byte).
553 * Unlikely NOR flash using normal read due to performance issue.
554 */
555 if (cmdlen >= 5)
556 /* to cater fast read where cmd + addr + dummy */
557 addr_bytes = cmdlen - 2;
558 else
559 /* for normal read (only ramtron as of now) */
560 addr_bytes = cmdlen - 1;
561
562 /* Setup the indirect trigger address */
563 writel((u32)plat->ahbbase,
564 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
565
566 /* Configure the opcode */
567 rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
568
569 if (rx_width & SPI_RX_QUAD)
570 /* Instruction and address at DQ0, data at DQ0-3. */
571 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
572
573 /* Get address */
574 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
575 writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
576
577 /* The remaining lenght is dummy bytes. */
578 dummy_bytes = cmdlen - addr_bytes - 1;
579 if (dummy_bytes) {
580 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
581 dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
582
583 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
584 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
585 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
586 #else
587 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
588 #endif
589
590 /* Convert to clock cycles. */
591 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
592 /* Need to minus the mode byte (8 clocks). */
593 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
594
595 if (dummy_clk)
596 rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
597 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
598 }
599
600 writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
601
602 /* set device size */
603 reg = readl(plat->regbase + CQSPI_REG_SIZE);
604 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
605 reg |= (addr_bytes - 1);
606 writel(reg, plat->regbase + CQSPI_REG_SIZE);
607 return 0;
608 }
609
610 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
611 {
612 u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
613 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
614 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
615 }
616
617 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
618 {
619 unsigned int timeout = 10000;
620 u32 reg;
621
622 while (timeout--) {
623 reg = cadence_qspi_get_rd_sram_level(plat);
624 if (reg)
625 return reg;
626 udelay(1);
627 }
628
629 return -ETIMEDOUT;
630 }
631
632 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
633 unsigned int n_rx, u8 *rxbuf)
634 {
635 unsigned int remaining = n_rx;
636 unsigned int bytes_to_read = 0;
637 int ret;
638
639 writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
640
641 /* Start the indirect read transfer */
642 writel(CQSPI_REG_INDIRECTRD_START,
643 plat->regbase + CQSPI_REG_INDIRECTRD);
644
645 while (remaining > 0) {
646 ret = cadence_qspi_wait_for_data(plat);
647 if (ret < 0) {
648 printf("Indirect write timed out (%i)\n", ret);
649 goto failrd;
650 }
651
652 bytes_to_read = ret;
653
654 while (bytes_to_read != 0) {
655 bytes_to_read *= CQSPI_FIFO_WIDTH;
656 bytes_to_read = bytes_to_read > remaining ?
657 remaining : bytes_to_read;
658 /* Handle non-4-byte aligned access to avoid data abort. */
659 if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
660 readsb(plat->ahbbase, rxbuf, bytes_to_read);
661 else
662 readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
663 rxbuf += bytes_to_read;
664 remaining -= bytes_to_read;
665 bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
666 }
667 }
668
669 /* Check indirect done status */
670 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
671 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
672 if (ret) {
673 printf("Indirect read completion error (%i)\n", ret);
674 goto failrd;
675 }
676
677 /* Clear indirect completion status */
678 writel(CQSPI_REG_INDIRECTRD_DONE,
679 plat->regbase + CQSPI_REG_INDIRECTRD);
680
681 return 0;
682
683 failrd:
684 /* Cancel the indirect read */
685 writel(CQSPI_REG_INDIRECTRD_CANCEL,
686 plat->regbase + CQSPI_REG_INDIRECTRD);
687 return ret;
688 }
689
690 /* Opcode + Address (3/4 bytes) */
691 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
692 unsigned int cmdlen, const u8 *cmdbuf)
693 {
694 unsigned int reg;
695 unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
696
697 if (cmdlen < 4 || cmdbuf == NULL) {
698 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
699 cmdlen, (unsigned int)cmdbuf);
700 return -EINVAL;
701 }
702 /* Setup the indirect trigger address */
703 writel((u32)plat->ahbbase,
704 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
705
706 /* Configure the opcode */
707 reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
708 writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
709
710 /* Setup write address. */
711 reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
712 writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
713
714 reg = readl(plat->regbase + CQSPI_REG_SIZE);
715 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
716 reg |= (addr_bytes - 1);
717 writel(reg, plat->regbase + CQSPI_REG_SIZE);
718 return 0;
719 }
720
721 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
722 unsigned int n_tx, const u8 *txbuf)
723 {
724 unsigned int page_size = plat->page_size;
725 unsigned int remaining = n_tx;
726 unsigned int write_bytes;
727 int ret;
728 struct bounce_buffer bb;
729 u8 *bb_txbuf;
730
731 /*
732 * Handle non-4-byte aligned accesses via bounce buffer to
733 * avoid data abort.
734 */
735 ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ);
736 if (ret)
737 return ret;
738 bb_txbuf = bb.bounce_buffer;
739
740 /* Configure the indirect read transfer bytes */
741 writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
742
743 /* Start the indirect write transfer */
744 writel(CQSPI_REG_INDIRECTWR_START,
745 plat->regbase + CQSPI_REG_INDIRECTWR);
746
747 while (remaining > 0) {
748 write_bytes = remaining > page_size ? page_size : remaining;
749 writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
750 if (write_bytes % 4)
751 writesb(plat->ahbbase,
752 bb_txbuf + rounddown(write_bytes, 4),
753 write_bytes % 4);
754
755 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
756 CQSPI_REG_SDRAMLEVEL_WR_MASK <<
757 CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
758 if (ret) {
759 printf("Indirect write timed out (%i)\n", ret);
760 goto failwr;
761 }
762
763 bb_txbuf += write_bytes;
764 remaining -= write_bytes;
765 }
766
767 /* Check indirect done status */
768 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
769 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
770 if (ret) {
771 printf("Indirect write completion error (%i)\n", ret);
772 goto failwr;
773 }
774 bounce_buffer_stop(&bb);
775
776 /* Clear indirect completion status */
777 writel(CQSPI_REG_INDIRECTWR_DONE,
778 plat->regbase + CQSPI_REG_INDIRECTWR);
779 return 0;
780
781 failwr:
782 /* Cancel the indirect write */
783 writel(CQSPI_REG_INDIRECTWR_CANCEL,
784 plat->regbase + CQSPI_REG_INDIRECTWR);
785 bounce_buffer_stop(&bb);
786 return ret;
787 }
788
789 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
790 {
791 unsigned int reg;
792
793 /* enter XiP mode immediately and enable direct mode */
794 reg = readl(reg_base + CQSPI_REG_CONFIG);
795 reg |= CQSPI_REG_CONFIG_ENABLE;
796 reg |= CQSPI_REG_CONFIG_DIRECT;
797 reg |= CQSPI_REG_CONFIG_XIP_IMM;
798 writel(reg, reg_base + CQSPI_REG_CONFIG);
799
800 /* keep the XiP mode */
801 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
802
803 /* Enable mode bit at devrd */
804 reg = readl(reg_base + CQSPI_REG_RD_INSTR);
805 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
806 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
807 }
"Das U-Boot" Source Tree