drivers/spi/exynos_spi.c

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Padmavathi Venna <padma.v@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <malloc.h>
  10 #include <spi.h>
  11 #include <fdtdec.h>
  12 #include <asm/arch/clk.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/gpio.h>
  16 #include <asm/arch/pinmux.h>
  17 #include <asm/arch-exynos/spi.h>
  18 #include <asm/io.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 /* Information about each SPI controller */
  23 struct spi_bus {
  24         enum periph_id periph_id;
  25         s32 frequency;          /* Default clock frequency, -1 for none */
  26         struct exynos_spi *regs;
  27         int inited;             /* 1 if this bus is ready for use */
  28         int node;
  29 };
  30
  31 /* A list of spi buses that we know about */
  32 static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
  33 static unsigned int bus_count;
  34
  35 struct exynos_spi_slave {
  36         struct spi_slave slave;
  37         struct exynos_spi *regs;
  38         unsigned int freq;              /* Default frequency */
  39         unsigned int mode;
  40         enum periph_id periph_id;       /* Peripheral ID for this device */
  41         unsigned int fifo_size;
  42         int skip_preamble;
  43 };
  44
  45 static struct spi_bus *spi_get_bus(unsigned dev_index)
  46 {
  47         if (dev_index < bus_count)
  48                 return &spi_bus[dev_index];
  49         debug("%s: invalid bus %d", __func__, dev_index);
  50
  51         return NULL;
  52 }
  53
  54 static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
  55 {
  56         return container_of(slave, struct exynos_spi_slave, slave);
  57 }
  58
  59 /**
  60  * Setup the driver private data
  61  *
  62  * @param bus           ID of the bus that the slave is attached to
  63  * @param cs            ID of the chip select connected to the slave
  64  * @param max_hz        Required spi frequency
  65  * @param mode          Required spi mode (clk polarity, clk phase and
  66  *                      master or slave)
  67  * @return new device or NULL
  68  */
  69 struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
  70                         unsigned int max_hz, unsigned int mode)
  71 {
  72         struct exynos_spi_slave *spi_slave;
  73         struct spi_bus *bus;
  74
  75         if (!spi_cs_is_valid(busnum, cs)) {
  76                 debug("%s: Invalid bus/chip select %d, %d\n", __func__,
  77                       busnum, cs);
  78                 return NULL;
  79         }
  80
  81         spi_slave = spi_alloc_slave(struct exynos_spi_slave, busnum, cs);
  82         if (!spi_slave) {
  83                 debug("%s: Could not allocate spi_slave\n", __func__);
  84                 return NULL;
  85         }
  86
  87         bus = &spi_bus[busnum];
  88         spi_slave->regs = bus->regs;
  89         spi_slave->mode = mode;
  90         spi_slave->periph_id = bus->periph_id;
  91         if (bus->periph_id == PERIPH_ID_SPI1 ||
  92             bus->periph_id == PERIPH_ID_SPI2)
  93                 spi_slave->fifo_size = 64;
  94         else
  95                 spi_slave->fifo_size = 256;
  96
  97         spi_slave->skip_preamble = 0;
  98
  99         spi_slave->freq = bus->frequency;
 100         if (max_hz)
 101                 spi_slave->freq = min(max_hz, spi_slave->freq);
 102
 103         return &spi_slave->slave;
 104 }
 105
 106 /**
 107  * Free spi controller
 108  *
 109  * @param slave Pointer to spi_slave to which controller has to
 110  *              communicate with
 111  */
 112 void spi_free_slave(struct spi_slave *slave)
 113 {
 114         struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
 115
 116         free(spi_slave);
 117 }
 118
 119 /**
 120  * Flush spi tx, rx fifos and reset the SPI controller
 121  *
 122  * @param slave Pointer to spi_slave to which controller has to
 123  *              communicate with
 124  */
 125 static void spi_flush_fifo(struct spi_slave *slave)
 126 {
 127         struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
 128         struct exynos_spi *regs = spi_slave->regs;
 129
 130         clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
 131         clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
 132         setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
 133 }
 134
 135 /**
 136  * Initialize the spi base registers, set the required clock frequency and
 137  * initialize the gpios
 138  *
 139  * @param slave Pointer to spi_slave to which controller has to
 140  *              communicate with
 141  * @return zero on success else a negative value
 142  */
 143 int spi_claim_bus(struct spi_slave *slave)
 144 {
 145         struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
 146         struct exynos_spi *regs = spi_slave->regs;
 147         u32 reg = 0;
 148         int ret;
 149
 150         ret = set_spi_clk(spi_slave->periph_id,
 151                                         spi_slave->freq);
 152         if (ret < 0) {
 153                 debug("%s: Failed to setup spi clock\n", __func__);
 154                 return ret;
 155         }
 156
 157         exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
 158
 159         spi_flush_fifo(slave);
 160
 161         reg = readl(&regs->ch_cfg);
 162         reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
 163
 164         if (spi_slave->mode & SPI_CPHA)
 165                 reg |= SPI_CH_CPHA_B;
 166
 167         if (spi_slave->mode & SPI_CPOL)
 168                 reg |= SPI_CH_CPOL_L;
 169
 170         writel(reg, &regs->ch_cfg);
 171         writel(SPI_FB_DELAY_180, &regs->fb_clk);
 172
 173         return 0;
 174 }
 175
 176 /**
 177  * Reset the spi H/W and flush the tx and rx fifos
 178  *
 179  * @param slave Pointer to spi_slave to which controller has to
 180  *              communicate with
 181  */
 182 void spi_release_bus(struct spi_slave *slave)
 183 {
 184         spi_flush_fifo(slave);
 185 }
 186
 187 static void spi_get_fifo_levels(struct exynos_spi *regs,
 188         int *rx_lvl, int *tx_lvl)
 189 {
 190         uint32_t spi_sts = readl(&regs->spi_sts);
 191
 192         *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
 193         *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
 194 }
 195
 196 /**
 197  * If there's something to transfer, do a software reset and set a
 198  * transaction size.
 199  *
 200  * @param regs  SPI peripheral registers
 201  * @param count Number of bytes to transfer
 202  */
 203 static void spi_request_bytes(struct exynos_spi *regs, int count)
 204 {
 205         assert(count && count < (1 << 16));
 206         setbits_le32(&regs->ch_cfg, SPI_CH_RST);
 207         clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
 208         writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
 209 }
 210
 211 static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
 212                         void **dinp, void const **doutp, unsigned long flags)
 213 {
 214         struct exynos_spi *regs = spi_slave->regs;
 215         uchar *rxp = *dinp;
 216         const uchar *txp = *doutp;
 217         int rx_lvl, tx_lvl;
 218         uint out_bytes, in_bytes;
 219         int toread;
 220         unsigned start = get_timer(0);
 221         int stopping;
 222
 223         out_bytes = in_bytes = todo;
 224
 225         stopping = spi_slave->skip_preamble && (flags & SPI_XFER_END) &&
 226                                         !(spi_slave->mode & SPI_SLAVE);
 227
 228         /*
 229          * If there's something to send, do a software reset and set a
 230          * transaction size.
 231          */
 232         spi_request_bytes(regs, todo);
 233
 234         /*
 235          * Bytes are transmitted/received in pairs. Wait to receive all the
 236          * data because then transmission will be done as well.
 237          */
 238         toread = in_bytes;
 239
 240         while (in_bytes) {
 241                 int temp;
 242
 243                 /* Keep the fifos full/empty. */
 244                 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
 245                 if (tx_lvl < spi_slave->fifo_size && out_bytes) {
 246                         temp = txp ? *txp++ : 0xff;
 247                         writel(temp, &regs->tx_data);
 248                         out_bytes--;
 249                 }
 250                 if (rx_lvl > 0) {
 251                         temp = readl(&regs->rx_data);
 252                         if (spi_slave->skip_preamble) {
 253                                 if (temp == SPI_PREAMBLE_END_BYTE) {
 254                                         spi_slave->skip_preamble = 0;
 255                                         stopping = 0;
 256                                 }
 257                         } else {
 258                                 if (rxp || stopping)
 259                                         *rxp++ = temp;
 260                                 in_bytes--;
 261                         }
 262                         toread--;
 263                 } else if (!toread) {
 264                         /*
 265                          * We have run out of input data, but haven't read
 266                          * enough bytes after the preamble yet. Read some more,
 267                          * and make sure that we transmit dummy bytes too, to
 268                          * keep things going.
 269                          */
 270                         assert(!out_bytes);
 271                         out_bytes = in_bytes;
 272                         toread = in_bytes;
 273                         txp = NULL;
 274                         spi_request_bytes(regs, toread);
 275                 }
 276                 if (spi_slave->skip_preamble && get_timer(start) > 100) {
 277                         printf("SPI timeout: in_bytes=%d, out_bytes=%d, ",
 278                                in_bytes, out_bytes);
 279                         return -1;
 280                 }
 281         }
 282
 283         *dinp = rxp;
 284         *doutp = txp;
 285
 286         return 0;
 287 }
 288
 289 /**
 290  * Transfer and receive data
 291  *
 292  * @param slave         Pointer to spi_slave to which controller has to
 293  *                      communicate with
 294  * @param bitlen        No of bits to tranfer or receive
 295  * @param dout          Pointer to transfer buffer
 296  * @param din           Pointer to receive buffer
 297  * @param flags         Flags for transfer begin and end
 298  * @return zero on success else a negative value
 299  */
 300 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 301              void *din, unsigned long flags)
 302 {
 303         struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
 304         int upto, todo;
 305         int bytelen;
 306         int ret = 0;
 307
 308         /* spi core configured to do 8 bit transfers */
 309         if (bitlen % 8) {
 310                 debug("Non byte aligned SPI transfer.\n");
 311                 return -1;
 312         }
 313
 314         /* Start the transaction, if necessary. */
 315         if ((flags & SPI_XFER_BEGIN))
 316                 spi_cs_activate(slave);
 317
 318         /* Exynos SPI limits each transfer to 65535 bytes */
 319         bytelen =  bitlen / 8;
 320         for (upto = 0; !ret && upto < bytelen; upto += todo) {
 321                 todo = min(bytelen - upto, (1 << 16) - 1);
 322                 ret = spi_rx_tx(spi_slave, todo, &din, &dout, flags);
 323                 if (ret)
 324                         break;
 325         }
 326
 327         /* Stop the transaction, if necessary. */
 328         if ((flags & SPI_XFER_END) && !(spi_slave->mode & SPI_SLAVE)) {
 329                 spi_cs_deactivate(slave);
 330                 if (spi_slave->skip_preamble) {
 331                         assert(!spi_slave->skip_preamble);
 332                         debug("Failed to complete premable transaction\n");
 333                         ret = -1;
 334                 }
 335         }
 336
 337         return ret;
 338 }
 339
 340 /**
 341  * Validates the bus and chip select numbers
 342  *
 343  * @param bus   ID of the bus that the slave is attached to
 344  * @param cs    ID of the chip select connected to the slave
 345  * @return one on success else zero
 346  */
 347 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 348 {
 349         return spi_get_bus(bus) && cs == 0;
 350 }
 351
 352 /**
 353  * Activate the CS by driving it LOW
 354  *
 355  * @param slave Pointer to spi_slave to which controller has to
 356  *              communicate with
 357  */
 358 void spi_cs_activate(struct spi_slave *slave)
 359 {
 360         struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
 361
 362         clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
 363         debug("Activate CS, bus %d\n", spi_slave->slave.bus);
 364         spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
 365 }
 366
 367 /**
 368  * Deactivate the CS by driving it HIGH
 369  *
 370  * @param slave Pointer to spi_slave to which controller has to
 371  *              communicate with
 372  */
 373 void spi_cs_deactivate(struct spi_slave *slave)
 374 {
 375         struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
 376
 377         setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
 378         debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
 379 }
 380
 381 static inline struct exynos_spi *get_spi_base(int dev_index)
 382 {
 383         if (dev_index < 3)
 384                 return (struct exynos_spi *)samsung_get_base_spi() + dev_index;
 385         else
 386                 return (struct exynos_spi *)samsung_get_base_spi_isp() +
 387                                         (dev_index - 3);
 388 }
 389
 390 /*
 391  * Read the SPI config from the device tree node.
 392  *
 393  * @param blob  FDT blob to read from
 394  * @param node  Node offset to read from
 395  * @param bus   SPI bus structure to fill with information
 396  * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
 397  */
 398 #ifdef CONFIG_OF_CONTROL
 399 static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
 400 {
 401         bus->node = node;
 402         bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
 403         bus->periph_id = pinmux_decode_periph_id(blob, node);
 404
 405         if (bus->periph_id == PERIPH_ID_NONE) {
 406                 debug("%s: Invalid peripheral ID %d\n", __func__,
 407                         bus->periph_id);
 408                 return -FDT_ERR_NOTFOUND;
 409         }
 410
 411         /* Use 500KHz as a suitable default */
 412         bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
 413                                         500000);
 414
 415         return 0;
 416 }
 417
 418 /*
 419  * Process a list of nodes, adding them to our list of SPI ports.
 420  *
 421  * @param blob          fdt blob
 422  * @param node_list     list of nodes to process (any <=0 are ignored)
 423  * @param count         number of nodes to process
 424  * @param is_dvc        1 if these are DVC ports, 0 if standard I2C
 425  * @return 0 if ok, -1 on error
 426  */
 427 static int process_nodes(const void *blob, int node_list[], int count)
 428 {
 429         int i;
 430
 431         /* build the i2c_controllers[] for each controller */
 432         for (i = 0; i < count; i++) {
 433                 int node = node_list[i];
 434                 struct spi_bus *bus;
 435
 436                 if (node <= 0)
 437                         continue;
 438
 439                 bus = &spi_bus[i];
 440                 if (spi_get_config(blob, node, bus)) {
 441                         printf("exynos spi_init: failed to decode bus %d\n",
 442                                 i);
 443                         return -1;
 444                 }
 445
 446                 debug("spi: controller bus %d at %p, periph_id %d\n",
 447                       i, bus->regs, bus->periph_id);
 448                 bus->inited = 1;
 449                 bus_count++;
 450         }
 451
 452         return 0;
 453 }
 454 #endif
 455
 456 /**
 457  * Set up a new SPI slave for an fdt node
 458  *
 459  * @param blob          Device tree blob
 460  * @param node          SPI peripheral node to use
 461  * @return 0 if ok, -1 on error
 462  */
 463 struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
 464                 unsigned int cs, unsigned int max_hz, unsigned int mode)
 465 {
 466         struct spi_bus *bus;
 467         unsigned int i;
 468
 469         for (i = 0, bus = spi_bus; i < bus_count; i++, bus++) {
 470                 if (bus->node == node)
 471                         return spi_setup_slave(i, cs, max_hz, mode);
 472         }
 473
 474         debug("%s: Failed to find bus node %d\n", __func__, node);
 475         return NULL;
 476 }
 477
 478 /* Sadly there is no error return from this function */
 479 void spi_init(void)
 480 {
 481         int count;
 482
 483 #ifdef CONFIG_OF_CONTROL
 484         int node_list[EXYNOS5_SPI_NUM_CONTROLLERS];
 485         const void *blob = gd->fdt_blob;
 486
 487         count = fdtdec_find_aliases_for_id(blob, "spi",
 488                         COMPAT_SAMSUNG_EXYNOS_SPI, node_list,
 489                         EXYNOS5_SPI_NUM_CONTROLLERS);
 490         if (process_nodes(blob, node_list, count))
 491                 return;
 492
 493 #else
 494         struct spi_bus *bus;
 495
 496         for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) {
 497                 bus = &spi_bus[count];
 498                 bus->regs = get_spi_base(count);
 499                 bus->periph_id = PERIPH_ID_SPI0 + count;
 500
 501                 /* Although Exynos5 supports upto 50Mhz speed,
 502                  * we are setting it to 10Mhz for safe side
 503                  */
 504                 bus->frequency = 10000000;
 505                 bus->inited = 1;
 506                 bus->node = 0;
 507                 bus_count = EXYNOS5_SPI_NUM_CONTROLLERS;
 508         }
 509 #endif
 510 }