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[people/ms/u-boot.git] / drivers / spi / fsl_qspi.c
1 /*
2 * Copyright 2013-2015 Freescale Semiconductor, Inc.
3 *
4 * Freescale Quad Serial Peripheral Interface (QSPI) driver
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <malloc.h>
11 #include <spi.h>
12 #include <asm/io.h>
13 #include <linux/sizes.h>
14 #include <dm.h>
15 #include <errno.h>
16 #include <watchdog.h>
17 #include "fsl_qspi.h"
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #define RX_BUFFER_SIZE 0x80
22 #ifdef CONFIG_MX6SX
23 #define TX_BUFFER_SIZE 0x200
24 #else
25 #define TX_BUFFER_SIZE 0x40
26 #endif
27
28 #define OFFSET_BITS_MASK GENMASK(23, 0)
29
30 #define FLASH_STATUS_WEL 0x02
31
32 /* SEQID */
33 #define SEQID_WREN 1
34 #define SEQID_FAST_READ 2
35 #define SEQID_RDSR 3
36 #define SEQID_SE 4
37 #define SEQID_CHIP_ERASE 5
38 #define SEQID_PP 6
39 #define SEQID_RDID 7
40 #define SEQID_BE_4K 8
41 #ifdef CONFIG_SPI_FLASH_BAR
42 #define SEQID_BRRD 9
43 #define SEQID_BRWR 10
44 #define SEQID_RDEAR 11
45 #define SEQID_WREAR 12
46 #endif
47 #define SEQID_WRAR 13
48 #define SEQID_RDAR 14
49
50 /* QSPI CMD */
51 #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
52 #define QSPI_CMD_RDSR 0x05 /* Read status register */
53 #define QSPI_CMD_WREN 0x06 /* Write enable */
54 #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */
55 #define QSPI_CMD_BE_4K 0x20 /* 4K erase */
56 #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */
57 #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
58 #define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */
59
60 /* Used for Micron, winbond and Macronix flashes */
61 #define QSPI_CMD_WREAR 0xc5 /* EAR register write */
62 #define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */
63
64 /* Used for Spansion flashes only. */
65 #define QSPI_CMD_BRRD 0x16 /* Bank register read */
66 #define QSPI_CMD_BRWR 0x17 /* Bank register write */
67
68 /* Used for Spansion S25FS-S family flash only. */
69 #define QSPI_CMD_RDAR 0x65 /* Read any device register */
70 #define QSPI_CMD_WRAR 0x71 /* Write any device register */
71
72 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
73 #define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
74 #define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
75 #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
76
77 /* fsl_qspi_platdata flags */
78 #define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
79
80 /* default SCK frequency, unit: HZ */
81 #define FSL_QSPI_DEFAULT_SCK_FREQ 50000000
82
83 /* QSPI max chipselect signals number */
84 #define FSL_QSPI_MAX_CHIPSELECT_NUM 4
85
86 #ifdef CONFIG_DM_SPI
87 /**
88 * struct fsl_qspi_platdata - platform data for Freescale QSPI
89 *
90 * @flags: Flags for QSPI QSPI_FLAG_...
91 * @speed_hz: Default SCK frequency
92 * @reg_base: Base address of QSPI registers
93 * @amba_base: Base address of QSPI memory mapping
94 * @amba_total_size: size of QSPI memory mapping
95 * @flash_num: Number of active slave devices
96 * @num_chipselect: Number of QSPI chipselect signals
97 */
98 struct fsl_qspi_platdata {
99 u32 flags;
100 u32 speed_hz;
101 fdt_addr_t reg_base;
102 fdt_addr_t amba_base;
103 fdt_size_t amba_total_size;
104 u32 flash_num;
105 u32 num_chipselect;
106 };
107 #endif
108
109 /**
110 * struct fsl_qspi_priv - private data for Freescale QSPI
111 *
112 * @flags: Flags for QSPI QSPI_FLAG_...
113 * @bus_clk: QSPI input clk frequency
114 * @speed_hz: Default SCK frequency
115 * @cur_seqid: current LUT table sequence id
116 * @sf_addr: flash access offset
117 * @amba_base: Base address of QSPI memory mapping of every CS
118 * @amba_total_size: size of QSPI memory mapping
119 * @cur_amba_base: Base address of QSPI memory mapping of current CS
120 * @flash_num: Number of active slave devices
121 * @num_chipselect: Number of QSPI chipselect signals
122 * @regs: Point to QSPI register structure for I/O access
123 */
124 struct fsl_qspi_priv {
125 u32 flags;
126 u32 bus_clk;
127 u32 speed_hz;
128 u32 cur_seqid;
129 u32 sf_addr;
130 u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
131 u32 amba_total_size;
132 u32 cur_amba_base;
133 u32 flash_num;
134 u32 num_chipselect;
135 struct fsl_qspi_regs *regs;
136 };
137
138 #ifndef CONFIG_DM_SPI
139 struct fsl_qspi {
140 struct spi_slave slave;
141 struct fsl_qspi_priv priv;
142 };
143 #endif
144
145 static u32 qspi_read32(u32 flags, u32 *addr)
146 {
147 return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
148 in_be32(addr) : in_le32(addr);
149 }
150
151 static void qspi_write32(u32 flags, u32 *addr, u32 val)
152 {
153 flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
154 out_be32(addr, val) : out_le32(addr, val);
155 }
156
157 /* QSPI support swapping the flash read/write data
158 * in hardware for LS102xA, but not for VF610 */
159 static inline u32 qspi_endian_xchg(u32 data)
160 {
161 #ifdef CONFIG_VF610
162 return swab32(data);
163 #else
164 return data;
165 #endif
166 }
167
168 static void qspi_set_lut(struct fsl_qspi_priv *priv)
169 {
170 struct fsl_qspi_regs *regs = priv->regs;
171 u32 lut_base;
172
173 /* Unlock the LUT */
174 qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
175 qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
176
177 /* Write Enable */
178 lut_base = SEQID_WREN * 4;
179 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
180 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
181 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
182 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
183 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
184
185 /* Fast Read */
186 lut_base = SEQID_FAST_READ * 4;
187 #ifdef CONFIG_SPI_FLASH_BAR
188 qspi_write32(priv->flags, &regs->lut[lut_base],
189 OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
190 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
191 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
192 #else
193 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
194 qspi_write32(priv->flags, &regs->lut[lut_base],
195 OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
196 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
197 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
198 else
199 qspi_write32(priv->flags, &regs->lut[lut_base],
200 OPRND0(QSPI_CMD_FAST_READ_4B) |
201 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
202 OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
203 INSTR1(LUT_ADDR));
204 #endif
205 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
206 OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
207 OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
208 INSTR1(LUT_READ));
209 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
210 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
211
212 /* Read Status */
213 lut_base = SEQID_RDSR * 4;
214 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
215 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
216 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
217 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
218 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
219 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
220
221 /* Erase a sector */
222 lut_base = SEQID_SE * 4;
223 #ifdef CONFIG_SPI_FLASH_BAR
224 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
225 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
226 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
227 #else
228 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
229 qspi_write32(priv->flags, &regs->lut[lut_base],
230 OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
231 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
232 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
233 else
234 qspi_write32(priv->flags, &regs->lut[lut_base],
235 OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
236 INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
237 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
238 #endif
239 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
240 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
241 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
242
243 /* Erase the whole chip */
244 lut_base = SEQID_CHIP_ERASE * 4;
245 qspi_write32(priv->flags, &regs->lut[lut_base],
246 OPRND0(QSPI_CMD_CHIP_ERASE) |
247 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
248 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
249 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
250 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
251
252 /* Page Program */
253 lut_base = SEQID_PP * 4;
254 #ifdef CONFIG_SPI_FLASH_BAR
255 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
256 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
257 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
258 #else
259 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
260 qspi_write32(priv->flags, &regs->lut[lut_base],
261 OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
262 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
263 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
264 else
265 qspi_write32(priv->flags, &regs->lut[lut_base],
266 OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
267 INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
268 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
269 #endif
270 #ifdef CONFIG_MX6SX
271 /*
272 * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
273 * So, Use IDATSZ in IPCR to determine the size and here set 0.
274 */
275 qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
276 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
277 #else
278 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
279 OPRND0(TX_BUFFER_SIZE) |
280 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
281 #endif
282 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
283 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
284
285 /* READ ID */
286 lut_base = SEQID_RDID * 4;
287 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
288 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
289 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
290 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
291 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
292 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
293
294 /* SUB SECTOR 4K ERASE */
295 lut_base = SEQID_BE_4K * 4;
296 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
297 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
298 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
299
300 #ifdef CONFIG_SPI_FLASH_BAR
301 /*
302 * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
303 * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
304 * initialization.
305 */
306 lut_base = SEQID_BRRD * 4;
307 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
308 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
309 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
310
311 lut_base = SEQID_BRWR * 4;
312 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
313 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
314 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
315
316 lut_base = SEQID_RDEAR * 4;
317 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
318 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
319 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
320
321 lut_base = SEQID_WREAR * 4;
322 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
323 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
324 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
325 #endif
326
327 /*
328 * Read any device register.
329 * Used for Spansion S25FS-S family flash only.
330 */
331 lut_base = SEQID_RDAR * 4;
332 qspi_write32(priv->flags, &regs->lut[lut_base],
333 OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
334 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
335 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
336 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
337 OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
338 OPRND1(1) | PAD1(LUT_PAD1) |
339 INSTR1(LUT_READ));
340
341 /*
342 * Write any device register.
343 * Used for Spansion S25FS-S family flash only.
344 */
345 lut_base = SEQID_WRAR * 4;
346 qspi_write32(priv->flags, &regs->lut[lut_base],
347 OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
348 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
349 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
350 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
351 OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
352
353 /* Lock the LUT */
354 qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
355 qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
356 }
357
358 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
359 /*
360 * If we have changed the content of the flash by writing or erasing,
361 * we need to invalidate the AHB buffer. If we do not do so, we may read out
362 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
363 * domain at the same time.
364 */
365 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
366 {
367 struct fsl_qspi_regs *regs = priv->regs;
368 u32 reg;
369
370 reg = qspi_read32(priv->flags, &regs->mcr);
371 reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
372 qspi_write32(priv->flags, &regs->mcr, reg);
373
374 /*
375 * The minimum delay : 1 AHB + 2 SFCK clocks.
376 * Delay 1 us is enough.
377 */
378 udelay(1);
379
380 reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
381 qspi_write32(priv->flags, &regs->mcr, reg);
382 }
383
384 /* Read out the data from the AHB buffer. */
385 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
386 {
387 struct fsl_qspi_regs *regs = priv->regs;
388 u32 mcr_reg;
389 void *rx_addr = NULL;
390
391 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
392
393 qspi_write32(priv->flags, &regs->mcr,
394 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
395 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
396
397 rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
398 /* Read out the data directly from the AHB buffer. */
399 memcpy(rxbuf, rx_addr, len);
400
401 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
402 }
403
404 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
405 {
406 u32 reg, reg2;
407 struct fsl_qspi_regs *regs = priv->regs;
408
409 reg = qspi_read32(priv->flags, &regs->mcr);
410 /* Disable the module */
411 qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
412
413 /* Set the Sampling Register for DDR */
414 reg2 = qspi_read32(priv->flags, &regs->smpr);
415 reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
416 reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
417 qspi_write32(priv->flags, &regs->smpr, reg2);
418
419 /* Enable the module again (enable the DDR too) */
420 reg |= QSPI_MCR_DDR_EN_MASK;
421 /* Enable bit 29 for imx6sx */
422 reg |= BIT(29);
423
424 qspi_write32(priv->flags, &regs->mcr, reg);
425 }
426
427 /*
428 * There are two different ways to read out the data from the flash:
429 * the "IP Command Read" and the "AHB Command Read".
430 *
431 * The IC guy suggests we use the "AHB Command Read" which is faster
432 * then the "IP Command Read". (What's more is that there is a bug in
433 * the "IP Command Read" in the Vybrid.)
434 *
435 * After we set up the registers for the "AHB Command Read", we can use
436 * the memcpy to read the data directly. A "missed" access to the buffer
437 * causes the controller to clear the buffer, and use the sequence pointed
438 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
439 */
440 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
441 {
442 struct fsl_qspi_regs *regs = priv->regs;
443
444 /* AHB configuration for access buffer 0/1/2 .*/
445 qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
446 qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
447 qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
448 qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
449 (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
450
451 /* We only use the buffer3 */
452 qspi_write32(priv->flags, &regs->buf0ind, 0);
453 qspi_write32(priv->flags, &regs->buf1ind, 0);
454 qspi_write32(priv->flags, &regs->buf2ind, 0);
455
456 /*
457 * Set the default lut sequence for AHB Read.
458 * Parallel mode is disabled.
459 */
460 qspi_write32(priv->flags, &regs->bfgencr,
461 SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
462
463 /*Enable DDR Mode*/
464 qspi_enable_ddr_mode(priv);
465 }
466 #endif
467
468 #ifdef CONFIG_SPI_FLASH_BAR
469 /* Bank register read/write, EAR register read/write */
470 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
471 {
472 struct fsl_qspi_regs *regs = priv->regs;
473 u32 reg, mcr_reg, data, seqid;
474
475 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
476 qspi_write32(priv->flags, &regs->mcr,
477 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
478 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
479 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
480
481 qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
482
483 if (priv->cur_seqid == QSPI_CMD_BRRD)
484 seqid = SEQID_BRRD;
485 else
486 seqid = SEQID_RDEAR;
487
488 qspi_write32(priv->flags, &regs->ipcr,
489 (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
490
491 /* Wait previous command complete */
492 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
493 ;
494
495 while (1) {
496 WATCHDOG_RESET();
497
498 reg = qspi_read32(priv->flags, &regs->rbsr);
499 if (reg & QSPI_RBSR_RDBFL_MASK) {
500 data = qspi_read32(priv->flags, &regs->rbdr[0]);
501 data = qspi_endian_xchg(data);
502 memcpy(rxbuf, &data, len);
503 qspi_write32(priv->flags, &regs->mcr,
504 qspi_read32(priv->flags, &regs->mcr) |
505 QSPI_MCR_CLR_RXF_MASK);
506 break;
507 }
508 }
509
510 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
511 }
512 #endif
513
514 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
515 {
516 struct fsl_qspi_regs *regs = priv->regs;
517 u32 mcr_reg, rbsr_reg, data, size;
518 int i;
519
520 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
521 qspi_write32(priv->flags, &regs->mcr,
522 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
523 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
524 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
525
526 qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
527
528 qspi_write32(priv->flags, &regs->ipcr,
529 (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
530 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
531 ;
532
533 i = 0;
534 while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
535 WATCHDOG_RESET();
536
537 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
538 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
539 data = qspi_read32(priv->flags, &regs->rbdr[i]);
540 data = qspi_endian_xchg(data);
541 size = (len < 4) ? len : 4;
542 memcpy(rxbuf, &data, size);
543 len -= size;
544 rxbuf++;
545 i++;
546 }
547 }
548
549 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
550 }
551
552 /* If not use AHB read, read data from ip interface */
553 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
554 {
555 struct fsl_qspi_regs *regs = priv->regs;
556 u32 mcr_reg, data;
557 int i, size;
558 u32 to_or_from;
559 u32 seqid;
560
561 if (priv->cur_seqid == QSPI_CMD_RDAR)
562 seqid = SEQID_RDAR;
563 else
564 seqid = SEQID_FAST_READ;
565
566 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
567 qspi_write32(priv->flags, &regs->mcr,
568 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
569 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
570 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
571
572 to_or_from = priv->sf_addr + priv->cur_amba_base;
573
574 while (len > 0) {
575 WATCHDOG_RESET();
576
577 qspi_write32(priv->flags, &regs->sfar, to_or_from);
578
579 size = (len > RX_BUFFER_SIZE) ?
580 RX_BUFFER_SIZE : len;
581
582 qspi_write32(priv->flags, &regs->ipcr,
583 (seqid << QSPI_IPCR_SEQID_SHIFT) |
584 size);
585 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
586 ;
587
588 to_or_from += size;
589 len -= size;
590
591 i = 0;
592 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
593 data = qspi_read32(priv->flags, &regs->rbdr[i]);
594 data = qspi_endian_xchg(data);
595 if (size < 4)
596 memcpy(rxbuf, &data, size);
597 else
598 memcpy(rxbuf, &data, 4);
599 rxbuf++;
600 size -= 4;
601 i++;
602 }
603 qspi_write32(priv->flags, &regs->mcr,
604 qspi_read32(priv->flags, &regs->mcr) |
605 QSPI_MCR_CLR_RXF_MASK);
606 }
607
608 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
609 }
610
611 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
612 {
613 struct fsl_qspi_regs *regs = priv->regs;
614 u32 mcr_reg, data, reg, status_reg, seqid;
615 int i, size, tx_size;
616 u32 to_or_from = 0;
617
618 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
619 qspi_write32(priv->flags, &regs->mcr,
620 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
621 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
622 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
623
624 status_reg = 0;
625 while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
626 WATCHDOG_RESET();
627
628 qspi_write32(priv->flags, &regs->ipcr,
629 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
630 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
631 ;
632
633 qspi_write32(priv->flags, &regs->ipcr,
634 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
635 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
636 ;
637
638 reg = qspi_read32(priv->flags, &regs->rbsr);
639 if (reg & QSPI_RBSR_RDBFL_MASK) {
640 status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
641 status_reg = qspi_endian_xchg(status_reg);
642 }
643 qspi_write32(priv->flags, &regs->mcr,
644 qspi_read32(priv->flags, &regs->mcr) |
645 QSPI_MCR_CLR_RXF_MASK);
646 }
647
648 /* Default is page programming */
649 seqid = SEQID_PP;
650 if (priv->cur_seqid == QSPI_CMD_WRAR)
651 seqid = SEQID_WRAR;
652 #ifdef CONFIG_SPI_FLASH_BAR
653 if (priv->cur_seqid == QSPI_CMD_BRWR)
654 seqid = SEQID_BRWR;
655 else if (priv->cur_seqid == QSPI_CMD_WREAR)
656 seqid = SEQID_WREAR;
657 #endif
658
659 to_or_from = priv->sf_addr + priv->cur_amba_base;
660
661 qspi_write32(priv->flags, &regs->sfar, to_or_from);
662
663 tx_size = (len > TX_BUFFER_SIZE) ?
664 TX_BUFFER_SIZE : len;
665
666 size = tx_size / 4;
667 for (i = 0; i < size; i++) {
668 memcpy(&data, txbuf, 4);
669 data = qspi_endian_xchg(data);
670 qspi_write32(priv->flags, &regs->tbdr, data);
671 txbuf += 4;
672 }
673
674 size = tx_size % 4;
675 if (size) {
676 data = 0;
677 memcpy(&data, txbuf, size);
678 data = qspi_endian_xchg(data);
679 qspi_write32(priv->flags, &regs->tbdr, data);
680 }
681
682 qspi_write32(priv->flags, &regs->ipcr,
683 (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
684 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
685 ;
686
687 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
688 }
689
690 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
691 {
692 struct fsl_qspi_regs *regs = priv->regs;
693 u32 mcr_reg, reg, data;
694
695 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
696 qspi_write32(priv->flags, &regs->mcr,
697 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
698 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
699 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
700
701 qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
702
703 qspi_write32(priv->flags, &regs->ipcr,
704 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
705 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
706 ;
707
708 while (1) {
709 WATCHDOG_RESET();
710
711 reg = qspi_read32(priv->flags, &regs->rbsr);
712 if (reg & QSPI_RBSR_RDBFL_MASK) {
713 data = qspi_read32(priv->flags, &regs->rbdr[0]);
714 data = qspi_endian_xchg(data);
715 memcpy(rxbuf, &data, len);
716 qspi_write32(priv->flags, &regs->mcr,
717 qspi_read32(priv->flags, &regs->mcr) |
718 QSPI_MCR_CLR_RXF_MASK);
719 break;
720 }
721 }
722
723 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
724 }
725
726 static void qspi_op_erase(struct fsl_qspi_priv *priv)
727 {
728 struct fsl_qspi_regs *regs = priv->regs;
729 u32 mcr_reg;
730 u32 to_or_from = 0;
731
732 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
733 qspi_write32(priv->flags, &regs->mcr,
734 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
735 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
736 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
737
738 to_or_from = priv->sf_addr + priv->cur_amba_base;
739 qspi_write32(priv->flags, &regs->sfar, to_or_from);
740
741 qspi_write32(priv->flags, &regs->ipcr,
742 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
743 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
744 ;
745
746 if (priv->cur_seqid == QSPI_CMD_SE) {
747 qspi_write32(priv->flags, &regs->ipcr,
748 (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
749 } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
750 qspi_write32(priv->flags, &regs->ipcr,
751 (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
752 }
753 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
754 ;
755
756 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
757 }
758
759 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
760 const void *dout, void *din, unsigned long flags)
761 {
762 u32 bytes = DIV_ROUND_UP(bitlen, 8);
763 static u32 wr_sfaddr;
764 u32 txbuf;
765
766 WATCHDOG_RESET();
767
768 if (dout) {
769 if (flags & SPI_XFER_BEGIN) {
770 priv->cur_seqid = *(u8 *)dout;
771 memcpy(&txbuf, dout, 4);
772 }
773
774 if (flags == SPI_XFER_END) {
775 priv->sf_addr = wr_sfaddr;
776 qspi_op_write(priv, (u8 *)dout, bytes);
777 return 0;
778 }
779
780 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
781 priv->cur_seqid == QSPI_CMD_RDAR) {
782 priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
783 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
784 (priv->cur_seqid == QSPI_CMD_BE_4K)) {
785 priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
786 qspi_op_erase(priv);
787 } else if (priv->cur_seqid == QSPI_CMD_PP ||
788 priv->cur_seqid == QSPI_CMD_WRAR) {
789 wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
790 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
791 (priv->cur_seqid == QSPI_CMD_WREAR)) {
792 #ifdef CONFIG_SPI_FLASH_BAR
793 wr_sfaddr = 0;
794 #endif
795 }
796 }
797
798 if (din) {
799 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
800 #ifdef CONFIG_SYS_FSL_QSPI_AHB
801 qspi_ahb_read(priv, din, bytes);
802 #else
803 qspi_op_read(priv, din, bytes);
804 #endif
805 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
806 qspi_op_read(priv, din, bytes);
807 } else if (priv->cur_seqid == QSPI_CMD_RDID)
808 qspi_op_rdid(priv, din, bytes);
809 else if (priv->cur_seqid == QSPI_CMD_RDSR)
810 qspi_op_rdsr(priv, din, bytes);
811 #ifdef CONFIG_SPI_FLASH_BAR
812 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
813 (priv->cur_seqid == QSPI_CMD_RDEAR)) {
814 priv->sf_addr = 0;
815 qspi_op_rdbank(priv, din, bytes);
816 }
817 #endif
818 }
819
820 #ifdef CONFIG_SYS_FSL_QSPI_AHB
821 if ((priv->cur_seqid == QSPI_CMD_SE) ||
822 (priv->cur_seqid == QSPI_CMD_PP) ||
823 (priv->cur_seqid == QSPI_CMD_BE_4K) ||
824 (priv->cur_seqid == QSPI_CMD_WREAR) ||
825 (priv->cur_seqid == QSPI_CMD_BRWR))
826 qspi_ahb_invalid(priv);
827 #endif
828
829 return 0;
830 }
831
832 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
833 {
834 u32 mcr_val;
835
836 mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
837 if (disable)
838 mcr_val |= QSPI_MCR_MDIS_MASK;
839 else
840 mcr_val &= ~QSPI_MCR_MDIS_MASK;
841 qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
842 }
843
844 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
845 {
846 u32 smpr_val;
847
848 smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
849 smpr_val &= ~clear_bits;
850 smpr_val |= set_bits;
851 qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
852 }
853 #ifndef CONFIG_DM_SPI
854 static unsigned long spi_bases[] = {
855 QSPI0_BASE_ADDR,
856 #ifdef CONFIG_MX6SX
857 QSPI1_BASE_ADDR,
858 #endif
859 };
860
861 static unsigned long amba_bases[] = {
862 QSPI0_AMBA_BASE,
863 #ifdef CONFIG_MX6SX
864 QSPI1_AMBA_BASE,
865 #endif
866 };
867
868 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
869 {
870 return container_of(slave, struct fsl_qspi, slave);
871 }
872
873 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
874 unsigned int max_hz, unsigned int mode)
875 {
876 u32 mcr_val;
877 struct fsl_qspi *qspi;
878 struct fsl_qspi_regs *regs;
879 u32 total_size;
880
881 if (bus >= ARRAY_SIZE(spi_bases))
882 return NULL;
883
884 if (cs >= FSL_QSPI_FLASH_NUM)
885 return NULL;
886
887 qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
888 if (!qspi)
889 return NULL;
890
891 #ifdef CONFIG_SYS_FSL_QSPI_BE
892 qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
893 #endif
894
895 regs = (struct fsl_qspi_regs *)spi_bases[bus];
896 qspi->priv.regs = regs;
897 /*
898 * According cs, use different amba_base to choose the
899 * corresponding flash devices.
900 *
901 * If not, only one flash device is used even if passing
902 * different cs using `sf probe`
903 */
904 qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
905
906 qspi->slave.max_write_size = TX_BUFFER_SIZE;
907
908 mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);
909 qspi_write32(qspi->priv.flags, &regs->mcr,
910 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
911 (mcr_val & QSPI_MCR_END_CFD_MASK));
912
913 qspi_cfg_smpr(&qspi->priv,
914 ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
915 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
916
917 total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
918 /*
919 * Any read access to non-implemented addresses will provide
920 * undefined results.
921 *
922 * In case single die flash devices, TOP_ADDR_MEMA2 and
923 * TOP_ADDR_MEMB2 should be initialized/programmed to
924 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
925 * setting the size of these devices to 0. This would ensure
926 * that the complete memory map is assigned to only one flash device.
927 */
928 qspi_write32(qspi->priv.flags, &regs->sfa1ad,
929 FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
930 qspi_write32(qspi->priv.flags, &regs->sfa2ad,
931 FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
932 qspi_write32(qspi->priv.flags, &regs->sfb1ad,
933 total_size | amba_bases[bus]);
934 qspi_write32(qspi->priv.flags, &regs->sfb2ad,
935 total_size | amba_bases[bus]);
936
937 qspi_set_lut(&qspi->priv);
938
939 #ifdef CONFIG_SYS_FSL_QSPI_AHB
940 qspi_init_ahb_read(&qspi->priv);
941 #endif
942
943 qspi_module_disable(&qspi->priv, 0);
944
945 return &qspi->slave;
946 }
947
948 void spi_free_slave(struct spi_slave *slave)
949 {
950 struct fsl_qspi *qspi = to_qspi_spi(slave);
951
952 free(qspi);
953 }
954
955 int spi_claim_bus(struct spi_slave *slave)
956 {
957 return 0;
958 }
959
960 void spi_release_bus(struct spi_slave *slave)
961 {
962 /* Nothing to do */
963 }
964
965 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
966 const void *dout, void *din, unsigned long flags)
967 {
968 struct fsl_qspi *qspi = to_qspi_spi(slave);
969
970 return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);
971 }
972
973 void spi_init(void)
974 {
975 /* Nothing to do */
976 }
977 #else
978 static int fsl_qspi_child_pre_probe(struct udevice *dev)
979 {
980 struct spi_slave *slave = dev_get_parent_priv(dev);
981
982 slave->max_write_size = TX_BUFFER_SIZE;
983
984 return 0;
985 }
986
987 static int fsl_qspi_probe(struct udevice *bus)
988 {
989 u32 mcr_val;
990 u32 amba_size_per_chip;
991 struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
992 struct fsl_qspi_priv *priv = dev_get_priv(bus);
993 struct dm_spi_bus *dm_spi_bus;
994 int i;
995
996 dm_spi_bus = bus->uclass_priv;
997
998 dm_spi_bus->max_hz = plat->speed_hz;
999
1000 priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
1001 priv->flags = plat->flags;
1002
1003 priv->speed_hz = plat->speed_hz;
1004 /*
1005 * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
1006 * AMBA memory zone should be located on the 0~4GB space
1007 * even on a 64bits cpu.
1008 */
1009 priv->amba_base[0] = (u32)plat->amba_base;
1010 priv->amba_total_size = (u32)plat->amba_total_size;
1011 priv->flash_num = plat->flash_num;
1012 priv->num_chipselect = plat->num_chipselect;
1013
1014 mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
1015 qspi_write32(priv->flags, &priv->regs->mcr,
1016 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
1017 (mcr_val & QSPI_MCR_END_CFD_MASK));
1018
1019 qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
1020 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
1021
1022 /*
1023 * Assign AMBA memory zone for every chipselect
1024 * QuadSPI has two channels, every channel has two chipselects.
1025 * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
1026 * into two parts and assign to every channel. This indicate that every
1027 * channel only has one valid chipselect.
1028 * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
1029 * into four parts and assign to every chipselect.
1030 * Every channel will has two valid chipselects.
1031 */
1032 amba_size_per_chip = priv->amba_total_size >>
1033 (priv->num_chipselect >> 1);
1034 for (i = 1 ; i < priv->num_chipselect ; i++)
1035 priv->amba_base[i] =
1036 amba_size_per_chip + priv->amba_base[i - 1];
1037
1038 /*
1039 * Any read access to non-implemented addresses will provide
1040 * undefined results.
1041 *
1042 * In case single die flash devices, TOP_ADDR_MEMA2 and
1043 * TOP_ADDR_MEMB2 should be initialized/programmed to
1044 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
1045 * setting the size of these devices to 0. This would ensure
1046 * that the complete memory map is assigned to only one flash device.
1047 */
1048 qspi_write32(priv->flags, &priv->regs->sfa1ad,
1049 priv->amba_base[0] + amba_size_per_chip);
1050 switch (priv->num_chipselect) {
1051 case 1:
1052 break;
1053 case 2:
1054 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1055 priv->amba_base[1]);
1056 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1057 priv->amba_base[1] + amba_size_per_chip);
1058 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1059 priv->amba_base[1] + amba_size_per_chip);
1060 break;
1061 case 4:
1062 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1063 priv->amba_base[2]);
1064 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1065 priv->amba_base[3]);
1066 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1067 priv->amba_base[3] + amba_size_per_chip);
1068 break;
1069 default:
1070 debug("Error: Unsupported chipselect number %u!\n",
1071 priv->num_chipselect);
1072 qspi_module_disable(priv, 1);
1073 return -EINVAL;
1074 }
1075
1076 qspi_set_lut(priv);
1077
1078 #ifdef CONFIG_SYS_FSL_QSPI_AHB
1079 qspi_init_ahb_read(priv);
1080 #endif
1081
1082 qspi_module_disable(priv, 0);
1083
1084 return 0;
1085 }
1086
1087 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
1088 {
1089 struct fdt_resource res_regs, res_mem;
1090 struct fsl_qspi_platdata *plat = bus->platdata;
1091 const void *blob = gd->fdt_blob;
1092 int node = dev_of_offset(bus);
1093 int ret, flash_num = 0, subnode;
1094
1095 if (fdtdec_get_bool(blob, node, "big-endian"))
1096 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
1097
1098 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1099 "QuadSPI", &res_regs);
1100 if (ret) {
1101 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1102 return -ENOMEM;
1103 }
1104 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1105 "QuadSPI-memory", &res_mem);
1106 if (ret) {
1107 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1108 return -ENOMEM;
1109 }
1110
1111 /* Count flash numbers */
1112 fdt_for_each_subnode(subnode, blob, node)
1113 ++flash_num;
1114
1115 if (flash_num == 0) {
1116 debug("Error: Missing flashes!\n");
1117 return -ENODEV;
1118 }
1119
1120 plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1121 FSL_QSPI_DEFAULT_SCK_FREQ);
1122 plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1123 FSL_QSPI_MAX_CHIPSELECT_NUM);
1124
1125 plat->reg_base = res_regs.start;
1126 plat->amba_base = res_mem.start;
1127 plat->amba_total_size = res_mem.end - res_mem.start + 1;
1128 plat->flash_num = flash_num;
1129
1130 debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1131 __func__,
1132 (u64)plat->reg_base,
1133 (u64)plat->amba_base,
1134 (u64)plat->amba_total_size,
1135 plat->speed_hz,
1136 plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1137 );
1138
1139 return 0;
1140 }
1141
1142 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1143 const void *dout, void *din, unsigned long flags)
1144 {
1145 struct fsl_qspi_priv *priv;
1146 struct udevice *bus;
1147
1148 bus = dev->parent;
1149 priv = dev_get_priv(bus);
1150
1151 return qspi_xfer(priv, bitlen, dout, din, flags);
1152 }
1153
1154 static int fsl_qspi_claim_bus(struct udevice *dev)
1155 {
1156 struct fsl_qspi_priv *priv;
1157 struct udevice *bus;
1158 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1159
1160 bus = dev->parent;
1161 priv = dev_get_priv(bus);
1162
1163 priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1164
1165 qspi_module_disable(priv, 0);
1166
1167 return 0;
1168 }
1169
1170 static int fsl_qspi_release_bus(struct udevice *dev)
1171 {
1172 struct fsl_qspi_priv *priv;
1173 struct udevice *bus;
1174
1175 bus = dev->parent;
1176 priv = dev_get_priv(bus);
1177
1178 qspi_module_disable(priv, 1);
1179
1180 return 0;
1181 }
1182
1183 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1184 {
1185 /* Nothing to do */
1186 return 0;
1187 }
1188
1189 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1190 {
1191 /* Nothing to do */
1192 return 0;
1193 }
1194
1195 static const struct dm_spi_ops fsl_qspi_ops = {
1196 .claim_bus = fsl_qspi_claim_bus,
1197 .release_bus = fsl_qspi_release_bus,
1198 .xfer = fsl_qspi_xfer,
1199 .set_speed = fsl_qspi_set_speed,
1200 .set_mode = fsl_qspi_set_mode,
1201 };
1202
1203 static const struct udevice_id fsl_qspi_ids[] = {
1204 { .compatible = "fsl,vf610-qspi" },
1205 { .compatible = "fsl,imx6sx-qspi" },
1206 { }
1207 };
1208
1209 U_BOOT_DRIVER(fsl_qspi) = {
1210 .name = "fsl_qspi",
1211 .id = UCLASS_SPI,
1212 .of_match = fsl_qspi_ids,
1213 .ops = &fsl_qspi_ops,
1214 .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1215 .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1216 .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1217 .probe = fsl_qspi_probe,
1218 .child_pre_probe = fsl_qspi_child_pre_probe,
1219 };
1220 #endif
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