drivers/spi/mxc_spi.c

   1 /*
   2  * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  *
  19  */
  20
  21 #include <common.h>
  22 #include <malloc.h>
  23 #include <spi.h>
  24 #include <asm/io.h>
  25
  26 #ifdef CONFIG_MX27
  27 /* i.MX27 has a completely wrong register layout and register definitions in the
  28  * datasheet, the correct one is in the Freescale's Linux driver */
  29
  30 #error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
  31 "See linux mxc_spi driver from Freescale for details."
  32
  33 #else
  34
  35 #define MXC_CSPIRXDATA          0x00
  36 #define MXC_CSPITXDATA          0x04
  37 #define MXC_CSPICTRL            0x08
  38 #define MXC_CSPIINT             0x0C
  39 #define MXC_CSPIDMA             0x10
  40 #define MXC_CSPISTAT            0x14
  41 #define MXC_CSPIPERIOD          0x18
  42 #define MXC_CSPITEST            0x1C
  43 #define MXC_CSPIRESET           0x00
  44
  45 #define MXC_CSPICTRL_EN         (1 << 0)
  46 #define MXC_CSPICTRL_MODE       (1 << 1)
  47 #define MXC_CSPICTRL_XCH        (1 << 2)
  48 #define MXC_CSPICTRL_SMC        (1 << 3)
  49 #define MXC_CSPICTRL_POL        (1 << 4)
  50 #define MXC_CSPICTRL_PHA        (1 << 5)
  51 #define MXC_CSPICTRL_SSCTL      (1 << 6)
  52 #define MXC_CSPICTRL_SSPOL      (1 << 7)
  53 #define MXC_CSPICTRL_CHIPSELECT(x)      (((x) & 0x3) << 24)
  54 #define MXC_CSPICTRL_BITCOUNT(x)        (((x) & 0x1f) << 8)
  55 #define MXC_CSPICTRL_DATARATE(x)        (((x) & 0x7) << 16)
  56
  57 #define MXC_CSPIPERIOD_32KHZ    (1 << 15)
  58
  59 static unsigned long spi_bases[] = {
  60         0x43fa4000,
  61         0x50010000,
  62         0x53f84000,
  63 };
  64
  65 #endif
  66
  67 struct mxc_spi_slave {
  68         struct spi_slave slave;
  69         unsigned long   base;
  70         u32             ctrl_reg;
  71 };
  72
  73 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
  74 {
  75         return container_of(slave, struct mxc_spi_slave, slave);
  76 }
  77
  78 static inline u32 reg_read(unsigned long addr)
  79 {
  80         return *(volatile unsigned long*)addr;
  81 }
  82
  83 static inline void reg_write(unsigned long addr, u32 val)
  84 {
  85         *(volatile unsigned long*)addr = val;
  86 }
  87
  88 static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
  89 {
  90         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
  91         unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
  92
  93         if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) {
  94                 cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
  95                         MXC_CSPICTRL_BITCOUNT(bitlen - 1);
  96                 reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
  97         }
  98
  99         reg_write(mxcs->base + MXC_CSPITXDATA, data);
 100
 101         cfg_reg |= MXC_CSPICTRL_XCH;
 102
 103         reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
 104
 105         while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
 106                 ;
 107
 108         return reg_read(mxcs->base + MXC_CSPIRXDATA);
 109 }
 110
 111 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 112                 void *din, unsigned long flags)
 113 {
 114         int n_blks = (bitlen + 31) / 32;
 115         u32 *out_l, *in_l;
 116         int i;
 117
 118         if ((int)dout & 3 || (int)din & 3) {
 119                 printf("Error: unaligned buffers in: %p, out: %p\n", din, dout);
 120                 return 1;
 121         }
 122
 123         for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
 124              i < n_blks;
 125              i++, in_l++, out_l++, bitlen -= 32)
 126                 *in_l = spi_xchg_single(slave, *out_l, bitlen);
 127
 128         return 0;
 129 }
 130
 131 void spi_init(void)
 132 {
 133 }
 134
 135 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 136                         unsigned int max_hz, unsigned int mode)
 137 {
 138         unsigned int ctrl_reg;
 139         struct mxc_spi_slave *mxcs;
 140
 141         if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) ||
 142             cs > 3)
 143                 return NULL;
 144
 145         ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
 146                 MXC_CSPICTRL_BITCOUNT(31) |
 147                 MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
 148                 MXC_CSPICTRL_EN |
 149                 MXC_CSPICTRL_MODE;
 150
 151         if (mode & SPI_CPHA)
 152                 ctrl_reg |= MXC_CSPICTRL_PHA;
 153         if (!(mode & SPI_CPOL))
 154                 ctrl_reg |= MXC_CSPICTRL_POL;
 155         if (mode & SPI_CS_HIGH)
 156                 ctrl_reg |= MXC_CSPICTRL_SSPOL;
 157
 158         mxcs = malloc(sizeof(struct mxc_spi_slave));
 159         if (!mxcs)
 160                 return NULL;
 161
 162         mxcs->slave.bus = bus;
 163         mxcs->slave.cs = cs;
 164         mxcs->base = spi_bases[bus];
 165         mxcs->ctrl_reg = ctrl_reg;
 166
 167         return &mxcs->slave;
 168 }
 169
 170 void spi_free_slave(struct spi_slave *slave)
 171 {
 172         free(slave);
 173 }
 174
 175 int spi_claim_bus(struct spi_slave *slave)
 176 {
 177         struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 178
 179         reg_write(mxcs->base + MXC_CSPIRESET, 1);
 180         udelay(1);
 181         reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
 182         reg_write(mxcs->base + MXC_CSPIPERIOD,
 183                   MXC_CSPIPERIOD_32KHZ);
 184         reg_write(mxcs->base + MXC_CSPIINT, 0);
 185
 186         return 0;
 187 }
 188
 189 void spi_release_bus(struct spi_slave *slave)
 190 {
 191         /* TODO: Shut the controller down */
 192 }