drivers/spi/mxs_spi.c

   1 /*
   2  * Freescale i.MX28 SPI driver
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  * NOTE: This driver only supports the SPI-controller chipselects,
  23  *       GPIO driven chipselects are not supported.
  24  */
  25
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <spi.h>
  29 #include <asm/errno.h>
  30 #include <asm/io.h>
  31 #include <asm/arch/clock.h>
  32 #include <asm/arch/imx-regs.h>
  33 #include <asm/arch/sys_proto.h>
  34 #include <asm/arch/dma.h>
  35
  36 #define MXS_SPI_MAX_TIMEOUT     1000000
  37 #define MXS_SPI_PORT_OFFSET     0x2000
  38 #define MXS_SSP_CHIPSELECT_MASK         0x00300000
  39 #define MXS_SSP_CHIPSELECT_SHIFT        20
  40
  41 #define MXSSSP_SMALL_TRANSFER   512
  42
  43 struct mxs_spi_slave {
  44         struct spi_slave        slave;
  45         uint32_t                max_khz;
  46         uint32_t                mode;
  47         struct mxs_ssp_regs     *regs;
  48 };
  49
  50 static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
  51 {
  52         return container_of(slave, struct mxs_spi_slave, slave);
  53 }
  54
  55 void spi_init(void)
  56 {
  57 }
  58
  59 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  60 {
  61         /* MXS SPI: 4 ports and 3 chip selects maximum */
  62         if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
  63                 return 0;
  64         else
  65                 return 1;
  66 }
  67
  68 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  69                                   unsigned int max_hz, unsigned int mode)
  70 {
  71         struct mxs_spi_slave *mxs_slave;
  72         struct mxs_ssp_regs *ssp_regs;
  73         int reg;
  74
  75         if (!spi_cs_is_valid(bus, cs)) {
  76                 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
  77                 return NULL;
  78         }
  79
  80         mxs_slave = calloc(sizeof(struct mxs_spi_slave), 1);
  81         if (!mxs_slave)
  82                 return NULL;
  83
  84         if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
  85                 goto err_init;
  86
  87         mxs_slave->slave.bus = bus;
  88         mxs_slave->slave.cs = cs;
  89         mxs_slave->max_khz = max_hz / 1000;
  90         mxs_slave->mode = mode;
  91         mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
  92         ssp_regs = mxs_slave->regs;
  93
  94         reg = readl(&ssp_regs->hw_ssp_ctrl0);
  95         reg &= ~(MXS_SSP_CHIPSELECT_MASK);
  96         reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;
  97
  98         writel(reg, &ssp_regs->hw_ssp_ctrl0);
  99         return &mxs_slave->slave;
 100
 101 err_init:
 102         free(mxs_slave);
 103         return NULL;
 104 }
 105
 106 void spi_free_slave(struct spi_slave *slave)
 107 {
 108         struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
 109         free(mxs_slave);
 110 }
 111
 112 int spi_claim_bus(struct spi_slave *slave)
 113 {
 114         struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
 115         struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
 116         uint32_t reg = 0;
 117
 118         mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
 119
 120         writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
 121
 122         reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
 123         reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
 124         reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
 125         writel(reg, &ssp_regs->hw_ssp_ctrl1);
 126
 127         writel(0, &ssp_regs->hw_ssp_cmd0);
 128
 129         mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
 130
 131         return 0;
 132 }
 133
 134 void spi_release_bus(struct spi_slave *slave)
 135 {
 136 }
 137
 138 static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
 139 {
 140         writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
 141         writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
 142 }
 143
 144 static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
 145 {
 146         writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
 147         writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
 148 }
 149
 150 static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
 151                         char *data, int length, int write, unsigned long flags)
 152 {
 153         struct mxs_ssp_regs *ssp_regs = slave->regs;
 154
 155         if (flags & SPI_XFER_BEGIN)
 156                 mxs_spi_start_xfer(ssp_regs);
 157
 158         while (length--) {
 159                 /* We transfer 1 byte */
 160 #if defined(CONFIG_MX23)
 161                 writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
 162                 writel(1, &ssp_regs->hw_ssp_ctrl0_set);
 163 #elif defined(CONFIG_MX28)
 164                 writel(1, &ssp_regs->hw_ssp_xfer_size);
 165 #endif
 166
 167                 if ((flags & SPI_XFER_END) && !length)
 168                         mxs_spi_end_xfer(ssp_regs);
 169
 170                 if (write)
 171                         writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
 172                 else
 173                         writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
 174
 175                 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
 176
 177                 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
 178                         SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
 179                         printf("MXS SPI: Timeout waiting for start\n");
 180                         return -ETIMEDOUT;
 181                 }
 182
 183                 if (write)
 184                         writel(*data++, &ssp_regs->hw_ssp_data);
 185
 186                 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
 187
 188                 if (!write) {
 189                         if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
 190                                 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
 191                                 printf("MXS SPI: Timeout waiting for data\n");
 192                                 return -ETIMEDOUT;
 193                         }
 194
 195                         *data = readl(&ssp_regs->hw_ssp_data);
 196                         data++;
 197                 }
 198
 199                 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
 200                         SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
 201                         printf("MXS SPI: Timeout waiting for finish\n");
 202                         return -ETIMEDOUT;
 203                 }
 204         }
 205
 206         return 0;
 207 }
 208
 209 static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
 210                         char *data, int length, int write, unsigned long flags)
 211 {
 212         const int xfer_max_sz = 0xff00;
 213         const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
 214         struct mxs_ssp_regs *ssp_regs = slave->regs;
 215         struct mxs_dma_desc *dp;
 216         uint32_t ctrl0;
 217         uint32_t cache_data_count;
 218         const uint32_t dstart = (uint32_t)data;
 219         int dmach;
 220         int tl;
 221         int ret = 0;
 222
 223 #if defined(CONFIG_MX23)
 224         const int mxs_spi_pio_words = 1;
 225 #elif defined(CONFIG_MX28)
 226         const int mxs_spi_pio_words = 4;
 227 #endif
 228
 229         ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
 230
 231         memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
 232
 233         ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
 234         ctrl0 |= SSP_CTRL0_DATA_XFER;
 235
 236         if (flags & SPI_XFER_BEGIN)
 237                 ctrl0 |= SSP_CTRL0_LOCK_CS;
 238         if (!write)
 239                 ctrl0 |= SSP_CTRL0_READ;
 240
 241         if (length % ARCH_DMA_MINALIGN)
 242                 cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
 243         else
 244                 cache_data_count = length;
 245
 246         /* Flush data to DRAM so DMA can pick them up */
 247         if (write)
 248                 flush_dcache_range(dstart, dstart + cache_data_count);
 249
 250         /* Invalidate the area, so no writeback into the RAM races with DMA */
 251         invalidate_dcache_range(dstart, dstart + cache_data_count);
 252
 253         dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
 254
 255         dp = desc;
 256         while (length) {
 257                 dp->address = (dma_addr_t)dp;
 258                 dp->cmd.address = (dma_addr_t)data;
 259
 260                 /*
 261                  * This is correct, even though it does indeed look insane.
 262                  * I hereby have to, wholeheartedly, thank Freescale Inc.,
 263                  * for always inventing insane hardware and keeping me busy
 264                  * and employed ;-)
 265                  */
 266                 if (write)
 267                         dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
 268                 else
 269                         dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
 270
 271                 /*
 272                  * The DMA controller can transfer large chunks (64kB) at
 273                  * time by setting the transfer length to 0. Setting tl to
 274                  * 0x10000 will overflow below and make .data contain 0.
 275                  * Otherwise, 0xff00 is the transfer maximum.
 276                  */
 277                 if (length >= 0x10000)
 278                         tl = 0x10000;
 279                 else
 280                         tl = min(length, xfer_max_sz);
 281
 282                 dp->cmd.data |=
 283                         ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
 284                         (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
 285                         MXS_DMA_DESC_HALT_ON_TERMINATE |
 286                         MXS_DMA_DESC_TERMINATE_FLUSH;
 287
 288                 data += tl;
 289                 length -= tl;
 290
 291                 if (!length) {
 292                         dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
 293
 294                         if (flags & SPI_XFER_END) {
 295                                 ctrl0 &= ~SSP_CTRL0_LOCK_CS;
 296                                 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
 297                         }
 298                 }
 299
 300                 /*
 301                  * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
 302                  * case of MX28, write only CTRL0 in case of MX23 due
 303                  * to the difference in register layout. It is utterly
 304                  * essential that the XFER_SIZE register is written on
 305                  * a per-descriptor basis with the same size as is the
 306                  * descriptor!
 307                  */
 308                 dp->cmd.pio_words[0] = ctrl0;
 309 #ifdef CONFIG_MX28
 310                 dp->cmd.pio_words[1] = 0;
 311                 dp->cmd.pio_words[2] = 0;
 312                 dp->cmd.pio_words[3] = tl;
 313 #endif
 314
 315                 mxs_dma_desc_append(dmach, dp);
 316
 317                 dp++;
 318         }
 319
 320         if (mxs_dma_go(dmach))
 321                 ret = -EINVAL;
 322
 323         /* The data arrived into DRAM, invalidate cache over them */
 324         if (!write)
 325                 invalidate_dcache_range(dstart, dstart + cache_data_count);
 326
 327         return ret;
 328 }
 329
 330 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 331                 const void *dout, void *din, unsigned long flags)
 332 {
 333         struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
 334         struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
 335         int len = bitlen / 8;
 336         char dummy;
 337         int write = 0;
 338         char *data = NULL;
 339         int dma = 1;
 340
 341         if (bitlen == 0) {
 342                 if (flags & SPI_XFER_END) {
 343                         din = (void *)&dummy;
 344                         len = 1;
 345                 } else
 346                         return 0;
 347         }
 348
 349         /* Half-duplex only */
 350         if (din && dout)
 351                 return -EINVAL;
 352         /* No data */
 353         if (!din && !dout)
 354                 return 0;
 355
 356         if (dout) {
 357                 data = (char *)dout;
 358                 write = 1;
 359         } else if (din) {
 360                 data = (char *)din;
 361                 write = 0;
 362         }
 363
 364         /*
 365          * Check for alignment, if the buffer is aligned, do DMA transfer,
 366          * PIO otherwise. This is a temporary workaround until proper bounce
 367          * buffer is in place.
 368          */
 369         if (dma) {
 370                 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
 371                         dma = 0;
 372                 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
 373                         dma = 0;
 374         }
 375
 376         if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
 377                 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
 378                 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
 379         } else {
 380                 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
 381                 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
 382         }
 383 }