drivers/spi/rk_spi.c

   1 /*
   2  * spi driver for rockchip
   3  *
   4  * (C) Copyright 2015 Google, Inc
   5  *
   6  * (C) Copyright 2008-2013 Rockchip Electronics
   7  * Peter, Software Engineering, <superpeter.cai@gmail.com>.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <clk.h>
  14 #include <dm.h>
  15 #include <dt-structs.h>
  16 #include <errno.h>
  17 #include <spi.h>
  18 #include <linux/errno.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/periph.h>
  22 #include <dm/pinctrl.h>
  23 #include "rk_spi.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* Change to 1 to output registers at the start of each transaction */
  28 #define DEBUG_RK_SPI    0
  29
  30 struct rockchip_spi_platdata {
  31 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  32         struct dtd_rockchip_rk3288_spi of_plat;
  33 #endif
  34         s32 frequency;          /* Default clock frequency, -1 for none */
  35         fdt_addr_t base;
  36         uint deactivate_delay_us;       /* Delay to wait after deactivate */
  37         uint activate_delay_us;         /* Delay to wait after activate */
  38 };
  39
  40 struct rockchip_spi_priv {
  41         struct rockchip_spi *regs;
  42         struct clk clk;
  43         unsigned int max_freq;
  44         unsigned int mode;
  45         ulong last_transaction_us;      /* Time of last transaction end */
  46         u8 bits_per_word;               /* max 16 bits per word */
  47         u8 n_bytes;
  48         unsigned int speed_hz;
  49         unsigned int last_speed_hz;
  50         unsigned int tmode;
  51         uint input_rate;
  52 };
  53
  54 #define SPI_FIFO_DEPTH          32
  55
  56 static void rkspi_dump_regs(struct rockchip_spi *regs)
  57 {
  58         debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
  59         debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
  60         debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
  61         debug("ser: \t\t0x%08x\n", readl(&regs->ser));
  62         debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
  63         debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
  64         debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
  65         debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
  66         debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
  67         debug("sr: \t\t0x%08x\n", readl(&regs->sr));
  68         debug("imr: \t\t0x%08x\n", readl(&regs->imr));
  69         debug("isr: \t\t0x%08x\n", readl(&regs->isr));
  70         debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
  71         debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
  72         debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
  73 }
  74
  75 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
  76 {
  77         writel(enable ? 1 : 0, &regs->enr);
  78 }
  79
  80 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
  81 {
  82         /*
  83          * We should try not to exceed the speed requested by the caller:
  84          * when selecting a divider, we need to make sure we round up.
  85          */
  86         uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
  87
  88         /* The baudrate register (BAUDR) is defined as a 32bit register where
  89          * the upper 16bit are reserved and having 'Fsclk_out' in the lower
  90          * 16bits with 'Fsclk_out' defined as follows:
  91          *
  92          *   Fsclk_out = Fspi_clk/ SCKDV
  93          *   Where SCKDV is any even value between 2 and 65534.
  94          */
  95         if (clk_div > 0xfffe) {
  96                 clk_div = 0xfffe;
  97                 debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
  98                       __func__, speed, priv->input_rate / clk_div);
  99         }
 100
 101         /* Round up to the next even 16bit number */
 102         clk_div = (clk_div + 1) & 0xfffe;
 103
 104         debug("spi speed %u, div %u\n", speed, clk_div);
 105
 106         clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
 107         priv->last_speed_hz = speed;
 108 }
 109
 110 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
 111 {
 112         unsigned long start;
 113
 114         start = get_timer(0);
 115         while (readl(&regs->sr) & SR_BUSY) {
 116                 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
 117                         debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
 118                         return -ETIMEDOUT;
 119                 }
 120         }
 121
 122         return 0;
 123 }
 124
 125 static void spi_cs_activate(struct udevice *dev, uint cs)
 126 {
 127         struct udevice *bus = dev->parent;
 128         struct rockchip_spi_platdata *plat = bus->platdata;
 129         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 130         struct rockchip_spi *regs = priv->regs;
 131
 132         /* If it's too soon to do another transaction, wait */
 133         if (plat->deactivate_delay_us && priv->last_transaction_us) {
 134                 ulong delay_us;         /* The delay completed so far */
 135                 delay_us = timer_get_us() - priv->last_transaction_us;
 136                 if (delay_us < plat->deactivate_delay_us)
 137                         udelay(plat->deactivate_delay_us - delay_us);
 138         }
 139
 140         debug("activate cs%u\n", cs);
 141         writel(1 << cs, &regs->ser);
 142         if (plat->activate_delay_us)
 143                 udelay(plat->activate_delay_us);
 144 }
 145
 146 static void spi_cs_deactivate(struct udevice *dev, uint cs)
 147 {
 148         struct udevice *bus = dev->parent;
 149         struct rockchip_spi_platdata *plat = bus->platdata;
 150         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 151         struct rockchip_spi *regs = priv->regs;
 152
 153         debug("deactivate cs%u\n", cs);
 154         writel(0, &regs->ser);
 155
 156         /* Remember time of this transaction so we can honour the bus delay */
 157         if (plat->deactivate_delay_us)
 158                 priv->last_transaction_us = timer_get_us();
 159 }
 160
 161 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 162 static int conv_of_platdata(struct udevice *dev)
 163 {
 164         struct rockchip_spi_platdata *plat = dev->platdata;
 165         struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
 166         struct rockchip_spi_priv *priv = dev_get_priv(dev);
 167         int ret;
 168
 169         plat->base = dtplat->reg[0];
 170         plat->frequency = 20000000;
 171         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
 172         if (ret < 0)
 173                 return ret;
 174         dev->req_seq = 0;
 175
 176         return 0;
 177 }
 178 #endif
 179
 180 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 181 {
 182 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 183         struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
 184         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 185         int ret;
 186
 187         plat->base = dev_read_addr(bus);
 188
 189         ret = clk_get_by_index(bus, 0, &priv->clk);
 190         if (ret < 0) {
 191                 debug("%s: Could not get clock for %s: %d\n", __func__,
 192                       bus->name, ret);
 193                 return ret;
 194         }
 195
 196         plat->frequency =
 197                 dev_read_u32_default(bus, "spi-max-frequency", 50000000);
 198         plat->deactivate_delay_us =
 199                 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
 200         plat->activate_delay_us =
 201                 dev_read_u32_default(bus, "spi-activate-delay", 0);
 202
 203         debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
 204               __func__, (uint)plat->base, plat->frequency,
 205               plat->deactivate_delay_us);
 206 #endif
 207
 208         return 0;
 209 }
 210
 211 static int rockchip_spi_calc_modclk(ulong max_freq)
 212 {
 213         /*
 214          * While this is not strictly correct for the RK3368, as the
 215          * GPLL will be 576MHz, things will still work, as the
 216          * clk_set_rate(...) implementation in our clock-driver will
 217          * chose the next closest rate not exceeding what we request
 218          * based on the output of this function.
 219          */
 220
 221         unsigned div;
 222         const unsigned long gpll_hz = 594000000UL;
 223
 224         /*
 225          * We need to find an input clock that provides at least twice
 226          * the maximum frequency and can be generated from the assumed
 227          * speed of GPLL (594MHz) using an integer divider.
 228          *
 229          * To give us more achievable bitrates at higher speeds (these
 230          * are generated by dividing by an even 16-bit integer from
 231          * this frequency), we try to have an input frequency of at
 232          * least 4x our max_freq.
 233          */
 234
 235         div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
 236         return gpll_hz / div;
 237 }
 238
 239 static int rockchip_spi_probe(struct udevice *bus)
 240 {
 241         struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
 242         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 243         int ret;
 244
 245         debug("%s: probe\n", __func__);
 246 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 247         ret = conv_of_platdata(bus);
 248         if (ret)
 249                 return ret;
 250 #endif
 251         priv->regs = (struct rockchip_spi *)plat->base;
 252
 253         priv->last_transaction_us = timer_get_us();
 254         priv->max_freq = plat->frequency;
 255
 256         /* Clamp the value from the DTS against any hardware limits */
 257         if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
 258                 priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
 259
 260         /* Find a module-input clock that fits with the max_freq setting */
 261         ret = clk_set_rate(&priv->clk,
 262                            rockchip_spi_calc_modclk(priv->max_freq));
 263         if (ret < 0) {
 264                 debug("%s: Failed to set clock: %d\n", __func__, ret);
 265                 return ret;
 266         }
 267         priv->input_rate = ret;
 268         debug("%s: rate = %u\n", __func__, priv->input_rate);
 269         priv->bits_per_word = 8;
 270         priv->tmode = TMOD_TR; /* Tx & Rx */
 271
 272         return 0;
 273 }
 274
 275 static int rockchip_spi_claim_bus(struct udevice *dev)
 276 {
 277         struct udevice *bus = dev->parent;
 278         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 279         struct rockchip_spi *regs = priv->regs;
 280         u8 spi_dfs, spi_tf;
 281         uint ctrlr0;
 282
 283         /* Disable the SPI hardware */
 284         rkspi_enable_chip(regs, 0);
 285
 286         switch (priv->bits_per_word) {
 287         case 8:
 288                 priv->n_bytes = 1;
 289                 spi_dfs = DFS_8BIT;
 290                 spi_tf = HALF_WORD_OFF;
 291                 break;
 292         case 16:
 293                 priv->n_bytes = 2;
 294                 spi_dfs = DFS_16BIT;
 295                 spi_tf = HALF_WORD_ON;
 296                 break;
 297         default:
 298                 debug("%s: unsupported bits: %dbits\n", __func__,
 299                       priv->bits_per_word);
 300                 return -EPROTONOSUPPORT;
 301         }
 302
 303         if (priv->speed_hz != priv->last_speed_hz)
 304                 rkspi_set_clk(priv, priv->speed_hz);
 305
 306         /* Operation Mode */
 307         ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
 308
 309         /* Data Frame Size */
 310         ctrlr0 |= spi_dfs << DFS_SHIFT;
 311
 312         /* set SPI mode 0..3 */
 313         if (priv->mode & SPI_CPOL)
 314                 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
 315         if (priv->mode & SPI_CPHA)
 316                 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
 317
 318         /* Chip Select Mode */
 319         ctrlr0 |= CSM_KEEP << CSM_SHIFT;
 320
 321         /* SSN to Sclk_out delay */
 322         ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
 323
 324         /* Serial Endian Mode */
 325         ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
 326
 327         /* First Bit Mode */
 328         ctrlr0 |= FBM_MSB << FBM_SHIFT;
 329
 330         /* Byte and Halfword Transform */
 331         ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
 332
 333         /* Rxd Sample Delay */
 334         ctrlr0 |= 0 << RXDSD_SHIFT;
 335
 336         /* Frame Format */
 337         ctrlr0 |= FRF_SPI << FRF_SHIFT;
 338
 339         /* Tx and Rx mode */
 340         ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
 341
 342         writel(ctrlr0, &regs->ctrlr0);
 343
 344         return 0;
 345 }
 346
 347 static int rockchip_spi_release_bus(struct udevice *dev)
 348 {
 349         struct udevice *bus = dev->parent;
 350         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 351
 352         rkspi_enable_chip(priv->regs, false);
 353
 354         return 0;
 355 }
 356
 357 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
 358                            const void *dout, void *din, unsigned long flags)
 359 {
 360         struct udevice *bus = dev->parent;
 361         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 362         struct rockchip_spi *regs = priv->regs;
 363         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 364         int len = bitlen >> 3;
 365         const u8 *out = dout;
 366         u8 *in = din;
 367         int toread, towrite;
 368         int ret;
 369
 370         debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
 371               len, flags);
 372         if (DEBUG_RK_SPI)
 373                 rkspi_dump_regs(regs);
 374
 375         /* Assert CS before transfer */
 376         if (flags & SPI_XFER_BEGIN)
 377                 spi_cs_activate(dev, slave_plat->cs);
 378
 379         while (len > 0) {
 380                 int todo = min(len, 0xffff);
 381
 382                 rkspi_enable_chip(regs, false);
 383                 writel(todo - 1, &regs->ctrlr1);
 384                 rkspi_enable_chip(regs, true);
 385
 386                 toread = todo;
 387                 towrite = todo;
 388                 while (toread || towrite) {
 389                         u32 status = readl(&regs->sr);
 390
 391                         if (towrite && !(status & SR_TF_FULL)) {
 392                                 writel(out ? *out++ : 0, regs->txdr);
 393                                 towrite--;
 394                         }
 395                         if (toread && !(status & SR_RF_EMPT)) {
 396                                 u32 byte = readl(regs->rxdr);
 397
 398                                 if (in)
 399                                         *in++ = byte;
 400                                 toread--;
 401                         }
 402                 }
 403                 ret = rkspi_wait_till_not_busy(regs);
 404                 if (ret)
 405                         break;
 406                 len -= todo;
 407         }
 408
 409         /* Deassert CS after transfer */
 410         if (flags & SPI_XFER_END)
 411                 spi_cs_deactivate(dev, slave_plat->cs);
 412
 413         rkspi_enable_chip(regs, false);
 414
 415         return ret;
 416 }
 417
 418 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
 419 {
 420         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 421
 422         /* Clamp to the maximum frequency specified in the DTS */
 423         if (speed > priv->max_freq)
 424                 speed = priv->max_freq;
 425
 426         priv->speed_hz = speed;
 427
 428         return 0;
 429 }
 430
 431 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
 432 {
 433         struct rockchip_spi_priv *priv = dev_get_priv(bus);
 434
 435         priv->mode = mode;
 436
 437         return 0;
 438 }
 439
 440 static const struct dm_spi_ops rockchip_spi_ops = {
 441         .claim_bus      = rockchip_spi_claim_bus,
 442         .release_bus    = rockchip_spi_release_bus,
 443         .xfer           = rockchip_spi_xfer,
 444         .set_speed      = rockchip_spi_set_speed,
 445         .set_mode       = rockchip_spi_set_mode,
 446         /*
 447          * cs_info is not needed, since we require all chip selects to be
 448          * in the device tree explicitly
 449          */
 450 };
 451
 452 static const struct udevice_id rockchip_spi_ids[] = {
 453         { .compatible = "rockchip,rk3288-spi" },
 454         { .compatible = "rockchip,rk3368-spi" },
 455         { .compatible = "rockchip,rk3399-spi" },
 456         { }
 457 };
 458
 459 U_BOOT_DRIVER(rockchip_spi) = {
 460 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 461         .name   = "rockchip_rk3288_spi",
 462 #else
 463         .name   = "rockchip_spi",
 464 #endif
 465         .id     = UCLASS_SPI,
 466         .of_match = rockchip_spi_ids,
 467         .ops    = &rockchip_spi_ops,
 468         .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
 469         .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
 470         .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
 471         .probe  = rockchip_spi_probe,
 472 };