drivers/spi/tegra114_spi.c

   1 /*
   2  * NVIDIA Tegra SPI controller (T114 and later)
   3  *
   4  * Copyright (c) 2010-2013 NVIDIA Corporation
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch-tegra/clk_rst.h>
  14 #include <spi.h>
  15 #include <fdtdec.h>
  16 #include "tegra_spi.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 /* COMMAND1 */
  21 #define SPI_CMD1_GO                     BIT(31)
  22 #define SPI_CMD1_M_S                    BIT(30)
  23 #define SPI_CMD1_MODE_MASK              GENMASK(1, 0)
  24 #define SPI_CMD1_MODE_SHIFT             28
  25 #define SPI_CMD1_CS_SEL_MASK            GENMASK(1, 0)
  26 #define SPI_CMD1_CS_SEL_SHIFT           26
  27 #define SPI_CMD1_CS_POL_INACTIVE3       BIT(25)
  28 #define SPI_CMD1_CS_POL_INACTIVE2       BIT(24)
  29 #define SPI_CMD1_CS_POL_INACTIVE1       BIT(23)
  30 #define SPI_CMD1_CS_POL_INACTIVE0       BIT(22)
  31 #define SPI_CMD1_CS_SW_HW               BIT(21)
  32 #define SPI_CMD1_CS_SW_VAL              BIT(20)
  33 #define SPI_CMD1_IDLE_SDA_MASK          GENMASK(1, 0)
  34 #define SPI_CMD1_IDLE_SDA_SHIFT         18
  35 #define SPI_CMD1_BIDIR                  BIT(17)
  36 #define SPI_CMD1_LSBI_FE                BIT(16)
  37 #define SPI_CMD1_LSBY_FE                BIT(15)
  38 #define SPI_CMD1_BOTH_EN_BIT            BIT(14)
  39 #define SPI_CMD1_BOTH_EN_BYTE           BIT(13)
  40 #define SPI_CMD1_RX_EN                  BIT(12)
  41 #define SPI_CMD1_TX_EN                  BIT(11)
  42 #define SPI_CMD1_PACKED                 BIT(5)
  43 #define SPI_CMD1_BIT_LEN_MASK           GENMASK(4, 0)
  44 #define SPI_CMD1_BIT_LEN_SHIFT          0
  45
  46 /* COMMAND2 */
  47 #define SPI_CMD2_TX_CLK_TAP_DELAY       BIT(6)
  48 #define SPI_CMD2_TX_CLK_TAP_DELAY_MASK  GENMASK(11, 6)
  49 #define SPI_CMD2_RX_CLK_TAP_DELAY       BIT(0)
  50 #define SPI_CMD2_RX_CLK_TAP_DELAY_MASK  GENMASK(5, 0)
  51
  52 /* TRANSFER STATUS */
  53 #define SPI_XFER_STS_RDY                BIT(30)
  54
  55 /* FIFO STATUS */
  56 #define SPI_FIFO_STS_CS_INACTIVE        BIT(31)
  57 #define SPI_FIFO_STS_FRAME_END          BIT(30)
  58 #define SPI_FIFO_STS_RX_FIFO_FLUSH      BIT(15)
  59 #define SPI_FIFO_STS_TX_FIFO_FLUSH      BIT(14)
  60 #define SPI_FIFO_STS_ERR                BIT(8)
  61 #define SPI_FIFO_STS_TX_FIFO_OVF        BIT(7)
  62 #define SPI_FIFO_STS_TX_FIFO_UNR        BIT(6)
  63 #define SPI_FIFO_STS_RX_FIFO_OVF        BIT(5)
  64 #define SPI_FIFO_STS_RX_FIFO_UNR        BIT(4)
  65 #define SPI_FIFO_STS_TX_FIFO_FULL       BIT(3)
  66 #define SPI_FIFO_STS_TX_FIFO_EMPTY      BIT(2)
  67 #define SPI_FIFO_STS_RX_FIFO_FULL       BIT(1)
  68 #define SPI_FIFO_STS_RX_FIFO_EMPTY      BIT(0)
  69
  70 #define SPI_TIMEOUT             1000
  71 #define TEGRA_SPI_MAX_FREQ      52000000
  72
  73 struct spi_regs {
  74         u32 command1;   /* 000:SPI_COMMAND1 register */
  75         u32 command2;   /* 004:SPI_COMMAND2 register */
  76         u32 timing1;    /* 008:SPI_CS_TIM1 register */
  77         u32 timing2;    /* 00c:SPI_CS_TIM2 register */
  78         u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
  79         u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
  80         u32 tx_data;    /* 018:SPI_TX_DATA register */
  81         u32 rx_data;    /* 01c:SPI_RX_DATA register */
  82         u32 dma_ctl;    /* 020:SPI_DMA_CTL register */
  83         u32 dma_blk;    /* 024:SPI_DMA_BLK register */
  84         u32 rsvd[56];   /* 028-107 reserved */
  85         u32 tx_fifo;    /* 108:SPI_FIFO1 register */
  86         u32 rsvd2[31];  /* 10c-187 reserved */
  87         u32 rx_fifo;    /* 188:SPI_FIFO2 register */
  88         u32 spare_ctl;  /* 18c:SPI_SPARE_CTRL register */
  89 };
  90
  91 struct tegra114_spi_priv {
  92         struct spi_regs *regs;
  93         unsigned int freq;
  94         unsigned int mode;
  95         int periph_id;
  96         int valid;
  97         int last_transaction_us;
  98 };
  99
 100 static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
 101 {
 102         struct tegra_spi_platdata *plat = bus->platdata;
 103         const void *blob = gd->fdt_blob;
 104         int node = bus->of_offset;
 105
 106         plat->base = dev_get_addr(bus);
 107         plat->periph_id = clock_decode_periph_id(blob, node);
 108
 109         if (plat->periph_id == PERIPH_ID_NONE) {
 110                 debug("%s: could not decode periph id %d\n", __func__,
 111                       plat->periph_id);
 112                 return -FDT_ERR_NOTFOUND;
 113         }
 114
 115         /* Use 500KHz as a suitable default */
 116         plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
 117                                         500000);
 118         plat->deactivate_delay_us = fdtdec_get_int(blob, node,
 119                                         "spi-deactivate-delay", 0);
 120         debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
 121               __func__, plat->base, plat->periph_id, plat->frequency,
 122               plat->deactivate_delay_us);
 123
 124         return 0;
 125 }
 126
 127 static int tegra114_spi_probe(struct udevice *bus)
 128 {
 129         struct tegra_spi_platdata *plat = dev_get_platdata(bus);
 130         struct tegra114_spi_priv *priv = dev_get_priv(bus);
 131         struct spi_regs *regs;
 132         ulong rate;
 133
 134         priv->regs = (struct spi_regs *)plat->base;
 135         regs = priv->regs;
 136
 137         priv->last_transaction_us = timer_get_us();
 138         priv->freq = plat->frequency;
 139         priv->periph_id = plat->periph_id;
 140
 141         /*
 142          * Change SPI clock to correct frequency, PLLP_OUT0 source, falling
 143          * back to the oscillator if that is too fast.
 144          */
 145         rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
 146                                       priv->freq);
 147         if (rate > priv->freq + 100000) {
 148                 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
 149                                               priv->freq);
 150                 if (rate != priv->freq) {
 151                         printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
 152                                bus->name, priv->freq, rate);
 153                 }
 154         }
 155
 156         /* Clear stale status here */
 157         setbits_le32(&regs->fifo_status,
 158                      SPI_FIFO_STS_ERR           |
 159                      SPI_FIFO_STS_TX_FIFO_OVF   |
 160                      SPI_FIFO_STS_TX_FIFO_UNR   |
 161                      SPI_FIFO_STS_RX_FIFO_OVF   |
 162                      SPI_FIFO_STS_RX_FIFO_UNR   |
 163                      SPI_FIFO_STS_TX_FIFO_FULL  |
 164                      SPI_FIFO_STS_TX_FIFO_EMPTY |
 165                      SPI_FIFO_STS_RX_FIFO_FULL  |
 166                      SPI_FIFO_STS_RX_FIFO_EMPTY);
 167         debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
 168
 169         setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
 170                      (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL);
 171         debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
 172
 173         return 0;
 174 }
 175
 176 /**
 177  * Activate the CS by driving it LOW
 178  *
 179  * @param slave Pointer to spi_slave to which controller has to
 180  *              communicate with
 181  */
 182 static void spi_cs_activate(struct udevice *dev)
 183 {
 184         struct udevice *bus = dev->parent;
 185         struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
 186         struct tegra114_spi_priv *priv = dev_get_priv(bus);
 187
 188         /* If it's too soon to do another transaction, wait */
 189         if (pdata->deactivate_delay_us &&
 190             priv->last_transaction_us) {
 191                 ulong delay_us;         /* The delay completed so far */
 192                 delay_us = timer_get_us() - priv->last_transaction_us;
 193                 if (delay_us < pdata->deactivate_delay_us)
 194                         udelay(pdata->deactivate_delay_us - delay_us);
 195         }
 196
 197         clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
 198 }
 199
 200 /**
 201  * Deactivate the CS by driving it HIGH
 202  *
 203  * @param slave Pointer to spi_slave to which controller has to
 204  *              communicate with
 205  */
 206 static void spi_cs_deactivate(struct udevice *dev)
 207 {
 208         struct udevice *bus = dev->parent;
 209         struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
 210         struct tegra114_spi_priv *priv = dev_get_priv(bus);
 211
 212         setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
 213
 214         /* Remember time of this transaction so we can honour the bus delay */
 215         if (pdata->deactivate_delay_us)
 216                 priv->last_transaction_us = timer_get_us();
 217
 218         debug("Deactivate CS, bus '%s'\n", bus->name);
 219 }
 220
 221 static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
 222                              const void *data_out, void *data_in,
 223                              unsigned long flags)
 224 {
 225         struct udevice *bus = dev->parent;
 226         struct tegra114_spi_priv *priv = dev_get_priv(bus);
 227         struct spi_regs *regs = priv->regs;
 228         u32 reg, tmpdout, tmpdin = 0;
 229         const u8 *dout = data_out;
 230         u8 *din = data_in;
 231         int num_bytes;
 232         int ret;
 233
 234         debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
 235               __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
 236         if (bitlen % 8)
 237                 return -1;
 238         num_bytes = bitlen / 8;
 239
 240         ret = 0;
 241
 242         if (flags & SPI_XFER_BEGIN)
 243                 spi_cs_activate(dev);
 244
 245         /* clear all error status bits */
 246         reg = readl(&regs->fifo_status);
 247         writel(reg, &regs->fifo_status);
 248
 249         clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
 250                         SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
 251                         (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
 252
 253         /* set xfer size to 1 block (32 bits) */
 254         writel(0, &regs->dma_blk);
 255
 256         /* handle data in 32-bit chunks */
 257         while (num_bytes > 0) {
 258                 int bytes;
 259                 int tm, i;
 260
 261                 tmpdout = 0;
 262                 bytes = (num_bytes > 4) ?  4 : num_bytes;
 263
 264                 if (dout != NULL) {
 265                         for (i = 0; i < bytes; ++i)
 266                                 tmpdout = (tmpdout << 8) | dout[i];
 267                         dout += bytes;
 268                 }
 269
 270                 num_bytes -= bytes;
 271
 272                 /* clear ready bit */
 273                 setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
 274
 275                 clrsetbits_le32(&regs->command1,
 276                                 SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
 277                                 (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
 278                 writel(tmpdout, &regs->tx_fifo);
 279                 setbits_le32(&regs->command1, SPI_CMD1_GO);
 280
 281                 /*
 282                  * Wait for SPI transmit FIFO to empty, or to time out.
 283                  * The RX FIFO status will be read and cleared last
 284                  */
 285                 for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
 286                         u32 fifo_status, xfer_status;
 287
 288                         xfer_status = readl(&regs->xfer_status);
 289                         if (!(xfer_status & SPI_XFER_STS_RDY))
 290                                 continue;
 291
 292                         fifo_status = readl(&regs->fifo_status);
 293                         if (fifo_status & SPI_FIFO_STS_ERR) {
 294                                 debug("%s: got a fifo error: ", __func__);
 295                                 if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
 296                                         debug("tx FIFO overflow ");
 297                                 if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
 298                                         debug("tx FIFO underrun ");
 299                                 if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
 300                                         debug("rx FIFO overflow ");
 301                                 if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
 302                                         debug("rx FIFO underrun ");
 303                                 if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
 304                                         debug("tx FIFO full ");
 305                                 if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
 306                                         debug("tx FIFO empty ");
 307                                 if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
 308                                         debug("rx FIFO full ");
 309                                 if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
 310                                         debug("rx FIFO empty ");
 311                                 debug("\n");
 312                                 break;
 313                         }
 314
 315                         if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
 316                                 tmpdin = readl(&regs->rx_fifo);
 317
 318                                 /* swap bytes read in */
 319                                 if (din != NULL) {
 320                                         for (i = bytes - 1; i >= 0; --i) {
 321                                                 din[i] = tmpdin & 0xff;
 322                                                 tmpdin >>= 8;
 323                                         }
 324                                         din += bytes;
 325                                 }
 326
 327                                 /* We can exit when we've had both RX and TX */
 328                                 break;
 329                         }
 330                 }
 331
 332                 if (tm >= SPI_TIMEOUT)
 333                         ret = tm;
 334
 335                 /* clear ACK RDY, etc. bits */
 336                 writel(readl(&regs->fifo_status), &regs->fifo_status);
 337         }
 338
 339         if (flags & SPI_XFER_END)
 340                 spi_cs_deactivate(dev);
 341
 342         debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
 343               __func__, tmpdin, readl(&regs->fifo_status));
 344
 345         if (ret) {
 346                 printf("%s: timeout during SPI transfer, tm %d\n",
 347                        __func__, ret);
 348                 return -1;
 349         }
 350
 351         return ret;
 352 }
 353
 354 static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
 355 {
 356         struct tegra_spi_platdata *plat = bus->platdata;
 357         struct tegra114_spi_priv *priv = dev_get_priv(bus);
 358
 359         if (speed > plat->frequency)
 360                 speed = plat->frequency;
 361         priv->freq = speed;
 362         debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
 363
 364         return 0;
 365 }
 366
 367 static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
 368 {
 369         struct tegra114_spi_priv *priv = dev_get_priv(bus);
 370
 371         priv->mode = mode;
 372         debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
 373
 374         return 0;
 375 }
 376
 377 static const struct dm_spi_ops tegra114_spi_ops = {
 378         .xfer           = tegra114_spi_xfer,
 379         .set_speed      = tegra114_spi_set_speed,
 380         .set_mode       = tegra114_spi_set_mode,
 381         /*
 382          * cs_info is not needed, since we require all chip selects to be
 383          * in the device tree explicitly
 384          */
 385 };
 386
 387 static const struct udevice_id tegra114_spi_ids[] = {
 388         { .compatible = "nvidia,tegra114-spi" },
 389         { }
 390 };
 391
 392 U_BOOT_DRIVER(tegra114_spi) = {
 393         .name   = "tegra114_spi",
 394         .id     = UCLASS_SPI,
 395         .of_match = tegra114_spi_ids,
 396         .ops    = &tegra114_spi_ops,
 397         .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
 398         .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
 399         .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
 400         .probe  = tegra114_spi_probe,
 401 };