4 * Copyright (C) 2013, Texas Instruments, Incorporated
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/omap.h>
16 #include <asm/omap_gpio.h>
17 #include <asm/omap_common.h>
18 #include <asm/ti-common/ti-edma3.h>
20 DECLARE_GLOBAL_DATA_PTR
;
22 /* ti qpsi register bit masks */
23 #define QSPI_TIMEOUT 2000000
24 #define QSPI_FCLK 192000000
26 #define QSPI_CLK_EN BIT(31)
27 #define QSPI_CLK_DIV_MAX 0xffff
29 #define QSPI_EN_CS(n) (n << 28)
30 #define QSPI_WLEN(n) ((n-1) << 19)
31 #define QSPI_3_PIN BIT(18)
32 #define QSPI_RD_SNGL BIT(16)
33 #define QSPI_WR_SNGL (2 << 16)
34 #define QSPI_INVAL (4 << 16)
35 #define QSPI_RD_QUAD (7 << 16)
37 #define QSPI_DD(m, n) (m << (3 + n*8))
38 #define QSPI_CKPHA(n) (1 << (2 + n*8))
39 #define QSPI_CSPOL(n) (1 << (1 + n*8))
40 #define QSPI_CKPOL(n) (1 << (n*8))
42 #define QSPI_WC BIT(1)
43 #define QSPI_BUSY BIT(0)
44 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
45 #define QSPI_XFER_DONE QSPI_WC
46 #define MM_SWITCH 0x01
47 #define MEM_CS(cs) ((cs + 1) << 8)
48 #define MEM_CS_UNSELECT 0xfffff8ff
49 #define MMAP_START_ADDR_DRA 0x5c000000
50 #define MMAP_START_ADDR_AM43x 0x30000000
51 #define CORE_CTRL_IO 0x4a002558
53 #define QSPI_CMD_READ (0x3 << 0)
54 #define QSPI_CMD_READ_DUAL (0x6b << 0)
55 #define QSPI_CMD_READ_QUAD (0x6c << 0)
56 #define QSPI_CMD_READ_FAST (0x0b << 0)
57 #define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
58 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
59 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
60 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
61 #define QSPI_SETUP0_READ_DUAL (0x1 << 12)
62 #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
63 #define QSPI_CMD_WRITE (0x12 << 16)
64 #define QSPI_NUM_DUMMY_BITS (0x0 << 24)
66 /* ti qspi register set */
96 struct spi_slave slave
;
102 struct ti_qspi_regs
*base
;
109 static void ti_spi_set_speed(struct ti_qspi_priv
*priv
, uint hz
)
113 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz
, clk_div
);
118 clk_div
= (QSPI_FCLK
/ hz
) - 1;
121 writel(readl(&priv
->base
->clk_ctrl
) & ~QSPI_CLK_EN
,
122 &priv
->base
->clk_ctrl
);
124 /* assign clk_div values */
127 else if (clk_div
> QSPI_CLK_DIV_MAX
)
128 clk_div
= QSPI_CLK_DIV_MAX
;
131 writel(QSPI_CLK_EN
| clk_div
, &priv
->base
->clk_ctrl
);
134 static void ti_qspi_cs_deactivate(struct ti_qspi_priv
*priv
)
136 writel(priv
->cmd
| QSPI_INVAL
, &priv
->base
->cmd
);
137 /* dummy readl to ensure bus sync */
138 readl(&priv
->base
->cmd
);
141 static int __ti_qspi_set_mode(struct ti_qspi_priv
*priv
, unsigned int mode
)
145 priv
->dc
|= QSPI_CKPHA(0);
147 priv
->dc
|= QSPI_CKPOL(0);
148 if (mode
& SPI_CS_HIGH
)
149 priv
->dc
|= QSPI_CSPOL(0);
154 static int __ti_qspi_claim_bus(struct ti_qspi_priv
*priv
, int cs
)
156 writel(priv
->dc
, &priv
->base
->dc
);
157 writel(0, &priv
->base
->cmd
);
158 writel(0, &priv
->base
->data
);
161 writel(priv
->dc
, &priv
->base
->dc
);
166 static void __ti_qspi_release_bus(struct ti_qspi_priv
*priv
)
168 writel(0, &priv
->base
->dc
);
169 writel(0, &priv
->base
->cmd
);
170 writel(0, &priv
->base
->data
);
173 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap
, int cs
, bool enable
)
177 val
= readl(ctrl_mod_mmap
);
181 val
&= MEM_CS_UNSELECT
;
182 writel(val
, ctrl_mod_mmap
);
185 static int __ti_qspi_xfer(struct ti_qspi_priv
*priv
, unsigned int bitlen
,
186 const void *dout
, void *din
, unsigned long flags
,
189 uint words
= bitlen
>> 3; /* fixed 8-bit word length */
190 const uchar
*txp
= dout
;
195 /* Setup mmap flags */
196 if (flags
& SPI_XFER_MMAP
) {
197 writel(MM_SWITCH
, &priv
->base
->memswitch
);
198 if (priv
->ctrl_mod_mmap
)
199 ti_qspi_ctrl_mode_mmap(priv
->ctrl_mod_mmap
, cs
, true);
201 } else if (flags
& SPI_XFER_MMAP_END
) {
202 writel(~MM_SWITCH
, &priv
->base
->memswitch
);
203 if (priv
->ctrl_mod_mmap
)
204 ti_qspi_ctrl_mode_mmap(priv
->ctrl_mod_mmap
, cs
, false);
212 debug("spi_xfer: Non byte aligned SPI transfer\n");
216 /* Setup command reg */
218 priv
->cmd
|= QSPI_WLEN(8);
219 priv
->cmd
|= QSPI_EN_CS(cs
);
220 if (priv
->mode
& SPI_3WIRE
)
221 priv
->cmd
|= QSPI_3_PIN
;
224 /* FIXME: This delay is required for successfull
225 * completion of read/write/erase. Once its root
226 * caused, it will be remove from the driver.
233 debug("tx cmd %08x dc %08x data %02x\n",
234 priv
->cmd
| QSPI_WR_SNGL
, priv
->dc
, *txp
);
235 writel(*txp
++, &priv
->base
->data
);
236 writel(priv
->cmd
| QSPI_WR_SNGL
,
238 status
= readl(&priv
->base
->status
);
239 timeout
= QSPI_TIMEOUT
;
240 while ((status
& QSPI_WC_BUSY
) != QSPI_XFER_DONE
) {
242 printf("spi_xfer: TX timeout!\n");
245 status
= readl(&priv
->base
->status
);
247 debug("tx done, status %08x\n", status
);
250 priv
->cmd
|= QSPI_RD_SNGL
;
251 debug("rx cmd %08x dc %08x\n",
252 priv
->cmd
, priv
->dc
);
256 writel(priv
->cmd
, &priv
->base
->cmd
);
257 status
= readl(&priv
->base
->status
);
258 timeout
= QSPI_TIMEOUT
;
259 while ((status
& QSPI_WC_BUSY
) != QSPI_XFER_DONE
) {
261 printf("spi_xfer: RX timeout!\n");
264 status
= readl(&priv
->base
->status
);
266 *rxp
++ = readl(&priv
->base
->data
);
267 debug("rx done, status %08x, read %02x\n",
272 /* Terminate frame */
273 if (flags
& SPI_XFER_END
)
274 ti_qspi_cs_deactivate(priv
);
279 /* TODO: control from sf layer to here through dm-spi */
280 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
281 void spi_flash_copy_mmap(void *data
, void *offset
, size_t len
)
283 unsigned int addr
= (unsigned int) (data
);
284 unsigned int edma_slot_num
= 1;
286 /* Invalidate the area, so no writeback into the RAM races with DMA */
287 invalidate_dcache_range(addr
, addr
+ roundup(len
, ARCH_DMA_MINALIGN
));
289 /* enable edma3 clocks */
290 enable_edma3_clocks();
292 /* Call edma3 api to do actual DMA transfer */
293 edma3_transfer(EDMA3_BASE
, edma_slot_num
, data
, offset
, len
);
295 /* disable edma3 clocks */
296 disable_edma3_clocks();
298 *((unsigned int *)offset
) += len
;
302 #ifndef CONFIG_DM_SPI
304 static inline struct ti_qspi_priv
*to_ti_qspi_priv(struct spi_slave
*slave
)
306 return container_of(slave
, struct ti_qspi_priv
, slave
);
309 int spi_cs_is_valid(unsigned int bus
, unsigned int cs
)
314 void spi_cs_activate(struct spi_slave
*slave
)
316 /* CS handled in xfer */
320 void spi_cs_deactivate(struct spi_slave
*slave
)
322 struct ti_qspi_priv
*priv
= to_ti_qspi_priv(slave
);
323 ti_qspi_cs_deactivate(priv
);
331 static void ti_spi_setup_spi_register(struct ti_qspi_priv
*priv
)
335 #ifdef CONFIG_QSPI_QUAD_SUPPORT
336 struct spi_slave
*slave
= &priv
->slave
;
337 memval
|= (QSPI_CMD_READ_QUAD
| QSPI_SETUP0_NUM_A_BYTES
|
338 QSPI_SETUP0_NUM_D_BYTES_8_BITS
|
339 QSPI_SETUP0_READ_QUAD
| QSPI_CMD_WRITE
|
340 QSPI_NUM_DUMMY_BITS
);
341 slave
->mode_rx
= SPI_RX_QUAD
;
343 memval
|= QSPI_CMD_READ
| QSPI_SETUP0_NUM_A_BYTES
|
344 QSPI_SETUP0_NUM_D_BYTES_NO_BITS
|
345 QSPI_SETUP0_READ_NORMAL
| QSPI_CMD_WRITE
|
349 writel(memval
, &priv
->base
->setup0
);
352 struct spi_slave
*spi_setup_slave(unsigned int bus
, unsigned int cs
,
353 unsigned int max_hz
, unsigned int mode
)
355 struct ti_qspi_priv
*priv
;
358 gpio_request(CONFIG_QSPI_SEL_GPIO
, "qspi_gpio");
359 gpio_direction_output(CONFIG_QSPI_SEL_GPIO
, 1);
362 priv
= spi_alloc_slave(struct ti_qspi_priv
, bus
, cs
);
364 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
368 priv
->base
= (struct ti_qspi_regs
*)QSPI_BASE
;
370 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
371 priv
->ctrl_mod_mmap
= (void *)CORE_CTRL_IO
;
372 priv
->slave
.memory_map
= (void *)MMAP_START_ADDR_DRA
;
374 priv
->slave
.memory_map
= (void *)MMAP_START_ADDR_AM43x
;
377 ti_spi_set_speed(priv
, max_hz
);
379 #ifdef CONFIG_TI_SPI_MMAP
380 ti_spi_setup_spi_register(priv
);
386 void spi_free_slave(struct spi_slave
*slave
)
388 struct ti_qspi_priv
*priv
= to_ti_qspi_priv(slave
);
392 int spi_claim_bus(struct spi_slave
*slave
)
394 struct ti_qspi_priv
*priv
= to_ti_qspi_priv(slave
);
396 debug("%s: bus:%i cs:%i\n", __func__
, priv
->slave
.bus
, priv
->slave
.cs
);
397 __ti_qspi_set_mode(priv
, priv
->mode
);
398 return __ti_qspi_claim_bus(priv
, priv
->slave
.cs
);
400 void spi_release_bus(struct spi_slave
*slave
)
402 struct ti_qspi_priv
*priv
= to_ti_qspi_priv(slave
);
404 debug("%s: bus:%i cs:%i\n", __func__
, priv
->slave
.bus
, priv
->slave
.cs
);
405 __ti_qspi_release_bus(priv
);
408 int spi_xfer(struct spi_slave
*slave
, unsigned int bitlen
, const void *dout
,
409 void *din
, unsigned long flags
)
411 struct ti_qspi_priv
*priv
= to_ti_qspi_priv(slave
);
413 debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
414 priv
->slave
.bus
, priv
->slave
.cs
, bitlen
, flags
);
415 return __ti_qspi_xfer(priv
, bitlen
, dout
, din
, flags
, priv
->slave
.cs
);
418 #else /* CONFIG_DM_SPI */
420 static void __ti_qspi_setup_memorymap(struct ti_qspi_priv
*priv
,
421 struct spi_slave
*slave
,
425 u32 mode
= slave
->mode_rx
& (SPI_RX_QUAD
| SPI_RX_DUAL
);
428 writel(0, &priv
->base
->setup0
);
432 memval
= QSPI_SETUP0_NUM_A_BYTES
| QSPI_CMD_WRITE
| QSPI_NUM_DUMMY_BITS
;
436 memval
|= QSPI_CMD_READ_QUAD
;
437 memval
|= QSPI_SETUP0_NUM_D_BYTES_8_BITS
;
438 memval
|= QSPI_SETUP0_READ_QUAD
;
439 slave
->mode_rx
= SPI_RX_QUAD
;
442 memval
|= QSPI_CMD_READ_DUAL
;
443 memval
|= QSPI_SETUP0_NUM_D_BYTES_8_BITS
;
444 memval
|= QSPI_SETUP0_READ_DUAL
;
447 memval
|= QSPI_CMD_READ
;
448 memval
|= QSPI_SETUP0_NUM_D_BYTES_NO_BITS
;
449 memval
|= QSPI_SETUP0_READ_NORMAL
;
453 writel(memval
, &priv
->base
->setup0
);
457 static int ti_qspi_set_speed(struct udevice
*bus
, uint max_hz
)
459 struct ti_qspi_priv
*priv
= dev_get_priv(bus
);
461 ti_spi_set_speed(priv
, max_hz
);
466 static int ti_qspi_set_mode(struct udevice
*bus
, uint mode
)
468 struct ti_qspi_priv
*priv
= dev_get_priv(bus
);
469 return __ti_qspi_set_mode(priv
, mode
);
472 static int ti_qspi_claim_bus(struct udevice
*dev
)
474 struct dm_spi_slave_platdata
*slave_plat
= dev_get_parent_platdata(dev
);
475 struct spi_slave
*slave
= dev_get_parent_priv(dev
);
476 struct ti_qspi_priv
*priv
;
480 priv
= dev_get_priv(bus
);
482 if (slave_plat
->cs
> priv
->num_cs
) {
483 debug("invalid qspi chip select\n");
487 __ti_qspi_setup_memorymap(priv
, slave
, true);
489 return __ti_qspi_claim_bus(priv
, slave_plat
->cs
);
492 static int ti_qspi_release_bus(struct udevice
*dev
)
494 struct spi_slave
*slave
= dev_get_parent_priv(dev
);
495 struct ti_qspi_priv
*priv
;
499 priv
= dev_get_priv(bus
);
501 __ti_qspi_setup_memorymap(priv
, slave
, false);
502 __ti_qspi_release_bus(priv
);
507 static int ti_qspi_xfer(struct udevice
*dev
, unsigned int bitlen
,
508 const void *dout
, void *din
, unsigned long flags
)
510 struct dm_spi_slave_platdata
*slave
= dev_get_parent_platdata(dev
);
511 struct ti_qspi_priv
*priv
;
515 priv
= dev_get_priv(bus
);
517 if (slave
->cs
> priv
->num_cs
) {
518 debug("invalid qspi chip select\n");
522 return __ti_qspi_xfer(priv
, bitlen
, dout
, din
, flags
, slave
->cs
);
525 static int ti_qspi_probe(struct udevice
*bus
)
527 /* Nothing to do in probe */
531 static int ti_qspi_ofdata_to_platdata(struct udevice
*bus
)
533 struct ti_qspi_priv
*priv
= dev_get_priv(bus
);
534 const void *blob
= gd
->fdt_blob
;
535 int node
= bus
->of_offset
;
539 priv
->base
= map_physmem(dev_get_addr(bus
), sizeof(struct ti_qspi_regs
),
541 priv
->memory_map
= map_physmem(dev_get_addr_index(bus
, 1), 0,
543 addr
= dev_get_addr_index(bus
, 2);
544 mmap
= map_physmem(dev_get_addr_index(bus
, 2), 0, MAP_NOCACHE
);
545 priv
->ctrl_mod_mmap
= (addr
== FDT_ADDR_T_NONE
) ? NULL
: mmap
;
547 priv
->max_hz
= fdtdec_get_int(blob
, node
, "spi-max-frequency", -1);
548 if (priv
->max_hz
< 0) {
549 debug("Error: Max frequency missing\n");
552 priv
->num_cs
= fdtdec_get_int(blob
, node
, "num-cs", 4);
554 debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__
,
555 (int)priv
->base
, priv
->max_hz
);
560 static int ti_qspi_child_pre_probe(struct udevice
*dev
)
562 struct spi_slave
*slave
= dev_get_parent_priv(dev
);
563 struct udevice
*bus
= dev_get_parent(dev
);
564 struct ti_qspi_priv
*priv
= dev_get_priv(bus
);
566 slave
->memory_map
= priv
->memory_map
;
570 static const struct dm_spi_ops ti_qspi_ops
= {
571 .claim_bus
= ti_qspi_claim_bus
,
572 .release_bus
= ti_qspi_release_bus
,
573 .xfer
= ti_qspi_xfer
,
574 .set_speed
= ti_qspi_set_speed
,
575 .set_mode
= ti_qspi_set_mode
,
578 static const struct udevice_id ti_qspi_ids
[] = {
579 { .compatible
= "ti,dra7xxx-qspi" },
580 { .compatible
= "ti,am4372-qspi" },
584 U_BOOT_DRIVER(ti_qspi
) = {
587 .of_match
= ti_qspi_ids
,
589 .ofdata_to_platdata
= ti_qspi_ofdata_to_platdata
,
590 .priv_auto_alloc_size
= sizeof(struct ti_qspi_priv
),
591 .probe
= ti_qspi_probe
,
592 .child_pre_probe
= ti_qspi_child_pre_probe
,
594 #endif /* CONFIG_DM_SPI */