drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
  10  * to uboot.
  11  *
  12  * commit c00552ebaf : Merge 3.18-rc7 into usb-next
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/slab.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/list.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <linux/usb/ch9.h>
  28 #include <linux/usb/gadget.h>
  29 #include <linux/usb/composite.h>
  30
  31 #include "core.h"
  32 #include "debug.h"
  33 #include "gadget.h"
  34 #include "io.h"
  35
  36 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  37 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  38                 struct dwc3_ep *dep, struct dwc3_request *req);
  39
  40 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  41 {
  42         switch (state) {
  43         case EP0_UNCONNECTED:
  44                 return "Unconnected";
  45         case EP0_SETUP_PHASE:
  46                 return "Setup Phase";
  47         case EP0_DATA_PHASE:
  48                 return "Data Phase";
  49         case EP0_STATUS_PHASE:
  50                 return "Status Phase";
  51         default:
  52                 return "UNKNOWN";
  53         }
  54 }
  55
  56 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  57                 u32 len, u32 type)
  58 {
  59         struct dwc3_gadget_ep_cmd_params params;
  60         struct dwc3_trb                 *trb;
  61         struct dwc3_ep                  *dep;
  62
  63         int                             ret;
  64
  65         dep = dwc->eps[epnum];
  66         if (dep->flags & DWC3_EP_BUSY) {
  67                 dev_vdbg(dwc->dev, "%s still busy", dep->name);
  68                 return 0;
  69         }
  70
  71         trb = dwc->ep0_trb;
  72
  73         trb->bpl = lower_32_bits(buf_dma);
  74         trb->bph = upper_32_bits(buf_dma);
  75         trb->size = len;
  76         trb->ctrl = type;
  77
  78         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  79                         | DWC3_TRB_CTRL_LST
  80                         | DWC3_TRB_CTRL_IOC
  81                         | DWC3_TRB_CTRL_ISP_IMI);
  82
  83         memset(&params, 0, sizeof(params));
  84         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  85         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  86
  87         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  88                         DWC3_DEPCMD_STARTTRANSFER, &params);
  89         if (ret < 0) {
  90                 dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
  91                 return ret;
  92         }
  93
  94         dep->flags |= DWC3_EP_BUSY;
  95         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
  96                         dep->number);
  97
  98         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  99
 100         return 0;
 101 }
 102
 103 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 104                 struct dwc3_request *req)
 105 {
 106         struct dwc3             *dwc = dep->dwc;
 107
 108         req->request.actual     = 0;
 109         req->request.status     = -EINPROGRESS;
 110         req->epnum              = dep->number;
 111
 112         list_add_tail(&req->list, &dep->request_list);
 113
 114         /*
 115          * Gadget driver might not be quick enough to queue a request
 116          * before we get a Transfer Not Ready event on this endpoint.
 117          *
 118          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 119          * flag is set, it's telling us that as soon as Gadget queues the
 120          * required request, we should kick the transfer here because the
 121          * IRQ we were waiting for is long gone.
 122          */
 123         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 124                 unsigned        direction;
 125
 126                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 127
 128                 if (dwc->ep0state != EP0_DATA_PHASE) {
 129                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 130                         return 0;
 131                 }
 132
 133                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 134
 135                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 136                                 DWC3_EP0_DIR_IN);
 137
 138                 return 0;
 139         }
 140
 141         /*
 142          * In case gadget driver asked us to delay the STATUS phase,
 143          * handle it here.
 144          */
 145         if (dwc->delayed_status) {
 146                 unsigned        direction;
 147
 148                 direction = !dwc->ep0_expect_in;
 149                 dwc->delayed_status = false;
 150                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 151
 152                 if (dwc->ep0state == EP0_STATUS_PHASE)
 153                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 154                 else
 155                         dev_dbg(dwc->dev, "too early for delayed status");
 156
 157                 return 0;
 158         }
 159
 160         /*
 161          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 162          *
 163          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 164          * come before issueing Start Transfer command, but if we do, we will
 165          * miss situations where the host starts another SETUP phase instead of
 166          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 167          * Layer Compliance Suite.
 168          *
 169          * The problem surfaces due to the fact that in case of back-to-back
 170          * SETUP packets there will be no XferNotReady(DATA) generated and we
 171          * will be stuck waiting for XferNotReady(DATA) forever.
 172          *
 173          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 174          * it tells us to start Data Phase right away. It also mentions that if
 175          * we receive a SETUP phase instead of the DATA phase, core will issue
 176          * XferComplete for the DATA phase, before actually initiating it in
 177          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 178          * can only be used to print some debugging logs, as the core expects
 179          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 180          * just so it completes right away, without transferring anything and,
 181          * only then, we can go back to the SETUP phase.
 182          *
 183          * Because of this scenario, SNPS decided to change the programming
 184          * model of control transfers and support on-demand transfers only for
 185          * the STATUS phase. To fix the issue we have now, we will always wait
 186          * for gadget driver to queue the DATA phase's struct usb_request, then
 187          * start it right away.
 188          *
 189          * If we're actually in a 2-stage transfer, we will wait for
 190          * XferNotReady(STATUS).
 191          */
 192         if (dwc->three_stage_setup) {
 193                 unsigned        direction;
 194
 195                 direction = dwc->ep0_expect_in;
 196                 dwc->ep0state = EP0_DATA_PHASE;
 197
 198                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 199
 200                 dep->flags &= ~DWC3_EP0_DIR_IN;
 201         }
 202
 203         return 0;
 204 }
 205
 206 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 207                 gfp_t gfp_flags)
 208 {
 209         struct dwc3_request             *req = to_dwc3_request(request);
 210         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 211         struct dwc3                     *dwc = dep->dwc;
 212
 213         unsigned long                   flags;
 214
 215         int                             ret;
 216
 217         spin_lock_irqsave(&dwc->lock, flags);
 218         if (!dep->endpoint.desc) {
 219                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
 220                                 request, dep->name);
 221                 ret = -ESHUTDOWN;
 222                 goto out;
 223         }
 224
 225         /* we share one TRB for ep0/1 */
 226         if (!list_empty(&dep->request_list)) {
 227                 ret = -EBUSY;
 228                 goto out;
 229         }
 230
 231         dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
 232                         request, dep->name, request->length,
 233                         dwc3_ep0_state_string(dwc->ep0state));
 234
 235         ret = __dwc3_gadget_ep0_queue(dep, req);
 236
 237 out:
 238         spin_unlock_irqrestore(&dwc->lock, flags);
 239
 240         return ret;
 241 }
 242
 243 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 244 {
 245         struct dwc3_ep          *dep;
 246
 247         /* reinitialize physical ep1 */
 248         dep = dwc->eps[1];
 249         dep->flags = DWC3_EP_ENABLED;
 250
 251         /* stall is always issued on EP0 */
 252         dep = dwc->eps[0];
 253         __dwc3_gadget_ep_set_halt(dep, 1, false);
 254         dep->flags = DWC3_EP_ENABLED;
 255         dwc->delayed_status = false;
 256
 257         if (!list_empty(&dep->request_list)) {
 258                 struct dwc3_request     *req;
 259
 260                 req = next_request(&dep->request_list);
 261                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 262         }
 263
 264         dwc->ep0state = EP0_SETUP_PHASE;
 265         dwc3_ep0_out_start(dwc);
 266 }
 267
 268 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 269 {
 270         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 271         struct dwc3                     *dwc = dep->dwc;
 272
 273         dwc3_ep0_stall_and_restart(dwc);
 274
 275         return 0;
 276 }
 277
 278 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 279 {
 280         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 281         struct dwc3                     *dwc = dep->dwc;
 282         unsigned long                   flags;
 283         int                             ret;
 284
 285         spin_lock_irqsave(&dwc->lock, flags);
 286         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 287         spin_unlock_irqrestore(&dwc->lock, flags);
 288
 289         return ret;
 290 }
 291
 292 void dwc3_ep0_out_start(struct dwc3 *dwc)
 293 {
 294         int                             ret;
 295
 296         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 297                         DWC3_TRBCTL_CONTROL_SETUP);
 298         WARN_ON(ret < 0);
 299 }
 300
 301 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 302 {
 303         struct dwc3_ep          *dep;
 304         u32                     windex = le16_to_cpu(wIndex_le);
 305         u32                     epnum;
 306
 307         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 308         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 309                 epnum |= 1;
 310
 311         dep = dwc->eps[epnum];
 312         if (dep->flags & DWC3_EP_ENABLED)
 313                 return dep;
 314
 315         return NULL;
 316 }
 317
 318 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 319 {
 320 }
 321 /*
 322  * ch 9.4.5
 323  */
 324 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 325                 struct usb_ctrlrequest *ctrl)
 326 {
 327         struct dwc3_ep          *dep;
 328         u32                     recip;
 329         u32                     reg;
 330         u16                     usb_status = 0;
 331         __le16                  *response_pkt;
 332
 333         recip = ctrl->bRequestType & USB_RECIP_MASK;
 334         switch (recip) {
 335         case USB_RECIP_DEVICE:
 336                 /*
 337                  * LTM will be set once we know how to set this in HW.
 338                  */
 339                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 340
 341                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 342                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 343                         if (reg & DWC3_DCTL_INITU1ENA)
 344                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 345                         if (reg & DWC3_DCTL_INITU2ENA)
 346                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 347                 }
 348
 349                 break;
 350
 351         case USB_RECIP_INTERFACE:
 352                 /*
 353                  * Function Remote Wake Capable D0
 354                  * Function Remote Wakeup       D1
 355                  */
 356                 break;
 357
 358         case USB_RECIP_ENDPOINT:
 359                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 360                 if (!dep)
 361                         return -EINVAL;
 362
 363                 if (dep->flags & DWC3_EP_STALL)
 364                         usb_status = 1 << USB_ENDPOINT_HALT;
 365                 break;
 366         default:
 367                 return -EINVAL;
 368         }
 369
 370         response_pkt = (__le16 *) dwc->setup_buf;
 371         *response_pkt = cpu_to_le16(usb_status);
 372
 373         dep = dwc->eps[0];
 374         dwc->ep0_usb_req.dep = dep;
 375         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 376         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 377         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 378
 379         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 380 }
 381
 382 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 383                 struct usb_ctrlrequest *ctrl, int set)
 384 {
 385         struct dwc3_ep          *dep;
 386         u32                     recip;
 387         u32                     wValue;
 388         u32                     wIndex;
 389         u32                     reg;
 390         int                     ret;
 391         enum usb_device_state   state;
 392
 393         wValue = le16_to_cpu(ctrl->wValue);
 394         wIndex = le16_to_cpu(ctrl->wIndex);
 395         recip = ctrl->bRequestType & USB_RECIP_MASK;
 396         state = dwc->gadget.state;
 397
 398         switch (recip) {
 399         case USB_RECIP_DEVICE:
 400
 401                 switch (wValue) {
 402                 case USB_DEVICE_REMOTE_WAKEUP:
 403                         break;
 404                 /*
 405                  * 9.4.1 says only only for SS, in AddressState only for
 406                  * default control pipe
 407                  */
 408                 case USB_DEVICE_U1_ENABLE:
 409                         if (state != USB_STATE_CONFIGURED)
 410                                 return -EINVAL;
 411                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 412                                 return -EINVAL;
 413
 414                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 415                         if (set)
 416                                 reg |= DWC3_DCTL_INITU1ENA;
 417                         else
 418                                 reg &= ~DWC3_DCTL_INITU1ENA;
 419                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 420                         break;
 421
 422                 case USB_DEVICE_U2_ENABLE:
 423                         if (state != USB_STATE_CONFIGURED)
 424                                 return -EINVAL;
 425                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 426                                 return -EINVAL;
 427
 428                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 429                         if (set)
 430                                 reg |= DWC3_DCTL_INITU2ENA;
 431                         else
 432                                 reg &= ~DWC3_DCTL_INITU2ENA;
 433                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 434                         break;
 435
 436                 case USB_DEVICE_LTM_ENABLE:
 437                         return -EINVAL;
 438
 439                 case USB_DEVICE_TEST_MODE:
 440                         if ((wIndex & 0xff) != 0)
 441                                 return -EINVAL;
 442                         if (!set)
 443                                 return -EINVAL;
 444
 445                         dwc->test_mode_nr = wIndex >> 8;
 446                         dwc->test_mode = true;
 447                         break;
 448                 default:
 449                         return -EINVAL;
 450                 }
 451                 break;
 452
 453         case USB_RECIP_INTERFACE:
 454                 switch (wValue) {
 455                 case USB_INTRF_FUNC_SUSPEND:
 456                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 457                                 /* XXX enable Low power suspend */
 458                                 ;
 459                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 460                                 /* XXX enable remote wakeup */
 461                                 ;
 462                         break;
 463                 default:
 464                         return -EINVAL;
 465                 }
 466                 break;
 467
 468         case USB_RECIP_ENDPOINT:
 469                 switch (wValue) {
 470                 case USB_ENDPOINT_HALT:
 471                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 472                         if (!dep)
 473                                 return -EINVAL;
 474                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 475                                 break;
 476                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 477                         if (ret)
 478                                 return -EINVAL;
 479                         break;
 480                 default:
 481                         return -EINVAL;
 482                 }
 483                 break;
 484
 485         default:
 486                 return -EINVAL;
 487         }
 488
 489         return 0;
 490 }
 491
 492 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 493 {
 494         enum usb_device_state state = dwc->gadget.state;
 495         u32 addr;
 496         u32 reg;
 497
 498         addr = le16_to_cpu(ctrl->wValue);
 499         if (addr > 127) {
 500                 dev_dbg(dwc->dev, "invalid device address %d", addr);
 501                 return -EINVAL;
 502         }
 503
 504         if (state == USB_STATE_CONFIGURED) {
 505                 dev_dbg(dwc->dev, "trying to set address when configured");
 506                 return -EINVAL;
 507         }
 508
 509         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 510         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 511         reg |= DWC3_DCFG_DEVADDR(addr);
 512         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 513
 514         if (addr)
 515                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 516         else
 517                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 518
 519         return 0;
 520 }
 521
 522 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 523 {
 524         int ret;
 525
 526         spin_unlock(&dwc->lock);
 527         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 528         spin_lock(&dwc->lock);
 529         return ret;
 530 }
 531
 532 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 533 {
 534         enum usb_device_state state = dwc->gadget.state;
 535         u32 cfg;
 536         int ret;
 537         u32 reg;
 538
 539         dwc->start_config_issued = false;
 540         cfg = le16_to_cpu(ctrl->wValue);
 541
 542         switch (state) {
 543         case USB_STATE_DEFAULT:
 544                 return -EINVAL;
 545
 546         case USB_STATE_ADDRESS:
 547                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 548                 /* if the cfg matches and the cfg is non zero */
 549                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 550
 551                         /*
 552                          * only change state if set_config has already
 553                          * been processed. If gadget driver returns
 554                          * USB_GADGET_DELAYED_STATUS, we will wait
 555                          * to change the state on the next usb_ep_queue()
 556                          */
 557                         if (ret == 0)
 558                                 usb_gadget_set_state(&dwc->gadget,
 559                                                 USB_STATE_CONFIGURED);
 560
 561                         /*
 562                          * Enable transition to U1/U2 state when
 563                          * nothing is pending from application.
 564                          */
 565                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 566                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 567                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 568
 569                         dwc->resize_fifos = true;
 570                         dev_dbg(dwc->dev, "resize FIFOs flag SET");
 571                 }
 572                 break;
 573
 574         case USB_STATE_CONFIGURED:
 575                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 576                 if (!cfg && !ret)
 577                         usb_gadget_set_state(&dwc->gadget,
 578                                         USB_STATE_ADDRESS);
 579                 break;
 580         default:
 581                 ret = -EINVAL;
 582         }
 583         return ret;
 584 }
 585
 586 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 587 {
 588         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 589         struct dwc3     *dwc = dep->dwc;
 590
 591         u32             param = 0;
 592         u32             reg;
 593
 594         struct timing {
 595                 u8      u1sel;
 596                 u8      u1pel;
 597                 u16     u2sel;
 598                 u16     u2pel;
 599         } __packed timing;
 600
 601         int             ret;
 602
 603         memcpy(&timing, req->buf, sizeof(timing));
 604
 605         dwc->u1sel = timing.u1sel;
 606         dwc->u1pel = timing.u1pel;
 607         dwc->u2sel = le16_to_cpu(timing.u2sel);
 608         dwc->u2pel = le16_to_cpu(timing.u2pel);
 609
 610         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 611         if (reg & DWC3_DCTL_INITU2ENA)
 612                 param = dwc->u2pel;
 613         if (reg & DWC3_DCTL_INITU1ENA)
 614                 param = dwc->u1pel;
 615
 616         /*
 617          * According to Synopsys Databook, if parameter is
 618          * greater than 125, a value of zero should be
 619          * programmed in the register.
 620          */
 621         if (param > 125)
 622                 param = 0;
 623
 624         /* now that we have the time, issue DGCMD Set Sel */
 625         ret = dwc3_send_gadget_generic_command(dwc,
 626                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 627         WARN_ON(ret < 0);
 628 }
 629
 630 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 631 {
 632         struct dwc3_ep  *dep;
 633         enum usb_device_state state = dwc->gadget.state;
 634         u16             wLength;
 635         u16             wValue;
 636
 637         if (state == USB_STATE_DEFAULT)
 638                 return -EINVAL;
 639
 640         wValue = le16_to_cpu(ctrl->wValue);
 641         wLength = le16_to_cpu(ctrl->wLength);
 642
 643         if (wLength != 6) {
 644                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 645                                 wLength);
 646                 return -EINVAL;
 647         }
 648
 649         /*
 650          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 651          * queue a usb_request for 6 bytes.
 652          *
 653          * Remember, though, this controller can't handle non-wMaxPacketSize
 654          * aligned transfers on the OUT direction, so we queue a request for
 655          * wMaxPacketSize instead.
 656          */
 657         dep = dwc->eps[0];
 658         dwc->ep0_usb_req.dep = dep;
 659         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 660         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 661         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 662
 663         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 664 }
 665
 666 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 667 {
 668         u16             wLength;
 669         u16             wValue;
 670         u16             wIndex;
 671
 672         wValue = le16_to_cpu(ctrl->wValue);
 673         wLength = le16_to_cpu(ctrl->wLength);
 674         wIndex = le16_to_cpu(ctrl->wIndex);
 675
 676         if (wIndex || wLength)
 677                 return -EINVAL;
 678
 679         /*
 680          * REVISIT It's unclear from Databook what to do with this
 681          * value. For now, just cache it.
 682          */
 683         dwc->isoch_delay = wValue;
 684
 685         return 0;
 686 }
 687
 688 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 689 {
 690         int ret;
 691
 692         switch (ctrl->bRequest) {
 693         case USB_REQ_GET_STATUS:
 694                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
 695                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 696                 break;
 697         case USB_REQ_CLEAR_FEATURE:
 698                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
 699                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 700                 break;
 701         case USB_REQ_SET_FEATURE:
 702                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
 703                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 704                 break;
 705         case USB_REQ_SET_ADDRESS:
 706                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
 707                 ret = dwc3_ep0_set_address(dwc, ctrl);
 708                 break;
 709         case USB_REQ_SET_CONFIGURATION:
 710                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
 711                 ret = dwc3_ep0_set_config(dwc, ctrl);
 712                 break;
 713         case USB_REQ_SET_SEL:
 714                 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
 715                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 716                 break;
 717         case USB_REQ_SET_ISOCH_DELAY:
 718                 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
 719                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 720                 break;
 721         default:
 722                 dev_vdbg(dwc->dev, "Forwarding to gadget driver");
 723                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 724                 break;
 725         }
 726
 727         return ret;
 728 }
 729
 730 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 731                 const struct dwc3_event_depevt *event)
 732 {
 733         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 734         int ret = -EINVAL;
 735         u32 len;
 736
 737         if (!dwc->gadget_driver)
 738                 goto out;
 739
 740         len = le16_to_cpu(ctrl->wLength);
 741         if (!len) {
 742                 dwc->three_stage_setup = false;
 743                 dwc->ep0_expect_in = false;
 744                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 745         } else {
 746                 dwc->three_stage_setup = true;
 747                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 748                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 749         }
 750
 751         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 752                 ret = dwc3_ep0_std_request(dwc, ctrl);
 753         else
 754                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 755
 756         if (ret == USB_GADGET_DELAYED_STATUS)
 757                 dwc->delayed_status = true;
 758
 759 out:
 760         if (ret < 0)
 761                 dwc3_ep0_stall_and_restart(dwc);
 762 }
 763
 764 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 765                 const struct dwc3_event_depevt *event)
 766 {
 767         struct dwc3_request     *r = NULL;
 768         struct usb_request      *ur;
 769         struct dwc3_trb         *trb;
 770         struct dwc3_ep          *ep0;
 771         u32                     transferred;
 772         u32                     status;
 773         u32                     length;
 774         u8                      epnum;
 775
 776         epnum = event->endpoint_number;
 777         ep0 = dwc->eps[0];
 778
 779         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 780
 781         trb = dwc->ep0_trb;
 782
 783         r = next_request(&ep0->request_list);
 784         if (!r)
 785                 return;
 786
 787         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 788         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 789                 dev_dbg(dwc->dev, "Setup Pending received");
 790
 791                 if (r)
 792                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 793
 794                 return;
 795         }
 796
 797         ur = &r->request;
 798
 799         length = trb->size & DWC3_TRB_SIZE_MASK;
 800
 801         if (dwc->ep0_bounced) {
 802                 unsigned transfer_size = ur->length;
 803                 unsigned maxp = ep0->endpoint.maxpacket;
 804
 805                 transfer_size += (maxp - (transfer_size % maxp));
 806                 transferred = min_t(u32, ur->length,
 807                                 transfer_size - length);
 808                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 809         } else {
 810                 transferred = ur->length - length;
 811         }
 812
 813         ur->actual += transferred;
 814
 815         if ((epnum & 1) && ur->actual < ur->length) {
 816                 /* for some reason we did not get everything out */
 817
 818                 dwc3_ep0_stall_and_restart(dwc);
 819         } else {
 820                 dwc3_gadget_giveback(ep0, r, 0);
 821
 822                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 823                                 ur->length && ur->zero) {
 824                         int ret;
 825
 826                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 827
 828                         ret = dwc3_ep0_start_trans(dwc, epnum,
 829                                         dwc->ctrl_req_addr, 0,
 830                                         DWC3_TRBCTL_CONTROL_DATA);
 831                         WARN_ON(ret < 0);
 832                 }
 833         }
 834 }
 835
 836 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 837                 const struct dwc3_event_depevt *event)
 838 {
 839         struct dwc3_request     *r;
 840         struct dwc3_ep          *dep;
 841         struct dwc3_trb         *trb;
 842         u32                     status;
 843
 844         dep = dwc->eps[0];
 845         trb = dwc->ep0_trb;
 846
 847         if (!list_empty(&dep->request_list)) {
 848                 r = next_request(&dep->request_list);
 849
 850                 dwc3_gadget_giveback(dep, r, 0);
 851         }
 852
 853         if (dwc->test_mode) {
 854                 int ret;
 855
 856                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 857                 if (ret < 0) {
 858                         dev_dbg(dwc->dev, "Invalid Test #%d",
 859                                         dwc->test_mode_nr);
 860                         dwc3_ep0_stall_and_restart(dwc);
 861                         return;
 862                 }
 863         }
 864
 865         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 866         if (status == DWC3_TRBSTS_SETUP_PENDING)
 867                 dev_dbg(dwc->dev, "Setup Pending received");
 868
 869         dwc->ep0state = EP0_SETUP_PHASE;
 870         dwc3_ep0_out_start(dwc);
 871 }
 872
 873 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 874                         const struct dwc3_event_depevt *event)
 875 {
 876         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 877
 878         dep->flags &= ~DWC3_EP_BUSY;
 879         dep->resource_index = 0;
 880         dwc->setup_packet_pending = false;
 881
 882         switch (dwc->ep0state) {
 883         case EP0_SETUP_PHASE:
 884                 dev_vdbg(dwc->dev, "Setup Phase");
 885                 dwc3_ep0_inspect_setup(dwc, event);
 886                 break;
 887
 888         case EP0_DATA_PHASE:
 889                 dev_vdbg(dwc->dev, "Data Phase");
 890                 dwc3_ep0_complete_data(dwc, event);
 891                 break;
 892
 893         case EP0_STATUS_PHASE:
 894                 dev_vdbg(dwc->dev, "Status Phase");
 895                 dwc3_ep0_complete_status(dwc, event);
 896                 break;
 897         default:
 898                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 899         }
 900 }
 901
 902 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 903                 struct dwc3_ep *dep, struct dwc3_request *req)
 904 {
 905         int                     ret;
 906
 907         req->direction = !!dep->number;
 908
 909         if (req->request.length == 0) {
 910                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 911                                 dwc->ctrl_req_addr, 0,
 912                                 DWC3_TRBCTL_CONTROL_DATA);
 913         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 914                         && (dep->number == 0)) {
 915                 u32     transfer_size;
 916                 u32     maxpacket;
 917
 918                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 919                                 dep->number);
 920                 if (ret) {
 921                         dev_dbg(dwc->dev, "failed to map request\n");
 922                         return;
 923                 }
 924
 925                 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
 926
 927                 maxpacket = dep->endpoint.maxpacket;
 928                 transfer_size = roundup(req->request.length, maxpacket);
 929
 930                 dwc->ep0_bounced = true;
 931
 932                 /*
 933                  * REVISIT in case request length is bigger than
 934                  * DWC3_EP0_BOUNCE_SIZE we will need two chained
 935                  * TRBs to handle the transfer.
 936                  */
 937                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 938                                 dwc->ep0_bounce_addr, transfer_size,
 939                                 DWC3_TRBCTL_CONTROL_DATA);
 940         } else {
 941                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 942                                 dep->number);
 943                 if (ret) {
 944                         dev_dbg(dwc->dev, "failed to map request\n");
 945                         return;
 946                 }
 947
 948                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
 949                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
 950         }
 951
 952         WARN_ON(ret < 0);
 953 }
 954
 955 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
 956 {
 957         struct dwc3             *dwc = dep->dwc;
 958         u32                     type;
 959
 960         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 961                 : DWC3_TRBCTL_CONTROL_STATUS2;
 962
 963         return dwc3_ep0_start_trans(dwc, dep->number,
 964                         dwc->ctrl_req_addr, 0, type);
 965 }
 966
 967 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
 968 {
 969         if (dwc->resize_fifos) {
 970                 dev_dbg(dwc->dev, "Resizing FIFOs");
 971                 dwc3_gadget_resize_tx_fifos(dwc);
 972                 dwc->resize_fifos = 0;
 973         }
 974
 975         WARN_ON(dwc3_ep0_start_control_status(dep));
 976 }
 977
 978 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 979                 const struct dwc3_event_depevt *event)
 980 {
 981         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 982
 983         __dwc3_ep0_do_control_status(dwc, dep);
 984 }
 985
 986 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
 987 {
 988         struct dwc3_gadget_ep_cmd_params params;
 989         u32                     cmd;
 990         int                     ret;
 991
 992         if (!dep->resource_index)
 993                 return;
 994
 995         cmd = DWC3_DEPCMD_ENDTRANSFER;
 996         cmd |= DWC3_DEPCMD_CMDIOC;
 997         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
 998         memset(&params, 0, sizeof(params));
 999         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1000         WARN_ON_ONCE(ret);
1001         dep->resource_index = 0;
1002 }
1003
1004 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1005                 const struct dwc3_event_depevt *event)
1006 {
1007         dwc->setup_packet_pending = true;
1008
1009         switch (event->status) {
1010         case DEPEVT_STATUS_CONTROL_DATA:
1011                 dev_vdbg(dwc->dev, "Control Data");
1012
1013                 /*
1014                  * We already have a DATA transfer in the controller's cache,
1015                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1016                  * it's for the wrong direction.
1017                  *
1018                  * In that case, we must issue END_TRANSFER command to the Data
1019                  * Phase we already have started and issue SetStall on the
1020                  * control endpoint.
1021                  */
1022                 if (dwc->ep0_expect_in != event->endpoint_number) {
1023                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1024
1025                         dev_vdbg(dwc->dev, "Wrong direction for Data phase");
1026                         dwc3_ep0_end_control_data(dwc, dep);
1027                         dwc3_ep0_stall_and_restart(dwc);
1028                         return;
1029                 }
1030
1031                 break;
1032
1033         case DEPEVT_STATUS_CONTROL_STATUS:
1034                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1035                         return;
1036
1037                 dev_vdbg(dwc->dev, "Control Status");
1038
1039                 dwc->ep0state = EP0_STATUS_PHASE;
1040
1041                 if (dwc->delayed_status) {
1042                         WARN_ON_ONCE(event->endpoint_number != 1);
1043                         dev_vdbg(dwc->dev, "Delayed Status");
1044                         return;
1045                 }
1046
1047                 dwc3_ep0_do_control_status(dwc, event);
1048         }
1049 }
1050
1051 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1052                 const struct dwc3_event_depevt *event)
1053 {
1054         u8                      epnum = event->endpoint_number;
1055
1056         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
1057                         dwc3_ep_event_string(event->endpoint_event),
1058                         epnum >> 1, (epnum & 1) ? "in" : "out",
1059                         dwc3_ep0_state_string(dwc->ep0state));
1060
1061         switch (event->endpoint_event) {
1062         case DWC3_DEPEVT_XFERCOMPLETE:
1063                 dwc3_ep0_xfer_complete(dwc, event);
1064                 break;
1065
1066         case DWC3_DEPEVT_XFERNOTREADY:
1067                 dwc3_ep0_xfernotready(dwc, event);
1068                 break;
1069
1070         case DWC3_DEPEVT_XFERINPROGRESS:
1071         case DWC3_DEPEVT_RXTXFIFOEVT:
1072         case DWC3_DEPEVT_STREAMEVT:
1073         case DWC3_DEPEVT_EPCMDCMPLT:
1074                 break;
1075         }
1076 }