2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
12 * commit c00552ebaf : Merge 3.18-rc7 into usb-next
14 * SPDX-License-Identifier: GPL-2.0
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/interrupt.h>
24 #include <linux/list.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/composite.h>
36 static void __dwc3_ep0_do_control_status(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
37 static void __dwc3_ep0_do_control_data(struct dwc3
*dwc
,
38 struct dwc3_ep
*dep
, struct dwc3_request
*req
);
40 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state
)
49 case EP0_STATUS_PHASE
:
50 return "Status Phase";
56 static int dwc3_ep0_start_trans(struct dwc3
*dwc
, u8 epnum
, dma_addr_t buf_dma
,
59 struct dwc3_gadget_ep_cmd_params params
;
65 dep
= dwc
->eps
[epnum
];
66 if (dep
->flags
& DWC3_EP_BUSY
) {
67 dwc3_trace(trace_dwc3_ep0
, "%s still busy", dep
->name
);
73 trb
->bpl
= lower_32_bits(buf_dma
);
74 trb
->bph
= upper_32_bits(buf_dma
);
78 trb
->ctrl
|= (DWC3_TRB_CTRL_HWO
81 | DWC3_TRB_CTRL_ISP_IMI
);
83 memset(¶ms
, 0, sizeof(params
));
84 params
.param0
= upper_32_bits(dwc
->ep0_trb_addr
);
85 params
.param1
= lower_32_bits(dwc
->ep0_trb_addr
);
87 trace_dwc3_prepare_trb(dep
, trb
);
89 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
90 DWC3_DEPCMD_STARTTRANSFER
, ¶ms
);
92 dwc3_trace(trace_dwc3_ep0
, "%s STARTTRANSFER failed",
97 dep
->flags
|= DWC3_EP_BUSY
;
98 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dwc
,
101 dwc
->ep0_next_event
= DWC3_EP0_COMPLETE
;
106 static int __dwc3_gadget_ep0_queue(struct dwc3_ep
*dep
,
107 struct dwc3_request
*req
)
109 struct dwc3
*dwc
= dep
->dwc
;
111 req
->request
.actual
= 0;
112 req
->request
.status
= -EINPROGRESS
;
113 req
->epnum
= dep
->number
;
115 list_add_tail(&req
->list
, &dep
->request_list
);
118 * Gadget driver might not be quick enough to queue a request
119 * before we get a Transfer Not Ready event on this endpoint.
121 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
122 * flag is set, it's telling us that as soon as Gadget queues the
123 * required request, we should kick the transfer here because the
124 * IRQ we were waiting for is long gone.
126 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
129 direction
= !!(dep
->flags
& DWC3_EP0_DIR_IN
);
131 if (dwc
->ep0state
!= EP0_DATA_PHASE
) {
132 dev_WARN(dwc
->dev
, "Unexpected pending request\n");
136 __dwc3_ep0_do_control_data(dwc
, dwc
->eps
[direction
], req
);
138 dep
->flags
&= ~(DWC3_EP_PENDING_REQUEST
|
145 * In case gadget driver asked us to delay the STATUS phase,
148 if (dwc
->delayed_status
) {
151 direction
= !dwc
->ep0_expect_in
;
152 dwc
->delayed_status
= false;
153 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_CONFIGURED
);
155 if (dwc
->ep0state
== EP0_STATUS_PHASE
)
156 __dwc3_ep0_do_control_status(dwc
, dwc
->eps
[direction
]);
158 dwc3_trace(trace_dwc3_ep0
,
159 "too early for delayed status");
165 * Unfortunately we have uncovered a limitation wrt the Data Phase.
167 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
168 * come before issueing Start Transfer command, but if we do, we will
169 * miss situations where the host starts another SETUP phase instead of
170 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
171 * Layer Compliance Suite.
173 * The problem surfaces due to the fact that in case of back-to-back
174 * SETUP packets there will be no XferNotReady(DATA) generated and we
175 * will be stuck waiting for XferNotReady(DATA) forever.
177 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
178 * it tells us to start Data Phase right away. It also mentions that if
179 * we receive a SETUP phase instead of the DATA phase, core will issue
180 * XferComplete for the DATA phase, before actually initiating it in
181 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
182 * can only be used to print some debugging logs, as the core expects
183 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
184 * just so it completes right away, without transferring anything and,
185 * only then, we can go back to the SETUP phase.
187 * Because of this scenario, SNPS decided to change the programming
188 * model of control transfers and support on-demand transfers only for
189 * the STATUS phase. To fix the issue we have now, we will always wait
190 * for gadget driver to queue the DATA phase's struct usb_request, then
191 * start it right away.
193 * If we're actually in a 2-stage transfer, we will wait for
194 * XferNotReady(STATUS).
196 if (dwc
->three_stage_setup
) {
199 direction
= dwc
->ep0_expect_in
;
200 dwc
->ep0state
= EP0_DATA_PHASE
;
202 __dwc3_ep0_do_control_data(dwc
, dwc
->eps
[direction
], req
);
204 dep
->flags
&= ~DWC3_EP0_DIR_IN
;
210 int dwc3_gadget_ep0_queue(struct usb_ep
*ep
, struct usb_request
*request
,
213 struct dwc3_request
*req
= to_dwc3_request(request
);
214 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
215 struct dwc3
*dwc
= dep
->dwc
;
221 spin_lock_irqsave(&dwc
->lock
, flags
);
222 if (!dep
->endpoint
.desc
) {
223 dwc3_trace(trace_dwc3_ep0
,
224 "trying to queue request %p to disabled %s",
230 /* we share one TRB for ep0/1 */
231 if (!list_empty(&dep
->request_list
)) {
236 dwc3_trace(trace_dwc3_ep0
,
237 "queueing request %p to %s length %d state '%s'",
238 request
, dep
->name
, request
->length
,
239 dwc3_ep0_state_string(dwc
->ep0state
));
241 ret
= __dwc3_gadget_ep0_queue(dep
, req
);
244 spin_unlock_irqrestore(&dwc
->lock
, flags
);
249 static void dwc3_ep0_stall_and_restart(struct dwc3
*dwc
)
253 /* reinitialize physical ep1 */
255 dep
->flags
= DWC3_EP_ENABLED
;
257 /* stall is always issued on EP0 */
259 __dwc3_gadget_ep_set_halt(dep
, 1, false);
260 dep
->flags
= DWC3_EP_ENABLED
;
261 dwc
->delayed_status
= false;
263 if (!list_empty(&dep
->request_list
)) {
264 struct dwc3_request
*req
;
266 req
= next_request(&dep
->request_list
);
267 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
270 dwc
->ep0state
= EP0_SETUP_PHASE
;
271 dwc3_ep0_out_start(dwc
);
274 int __dwc3_gadget_ep0_set_halt(struct usb_ep
*ep
, int value
)
276 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
277 struct dwc3
*dwc
= dep
->dwc
;
279 dwc3_ep0_stall_and_restart(dwc
);
284 int dwc3_gadget_ep0_set_halt(struct usb_ep
*ep
, int value
)
286 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
287 struct dwc3
*dwc
= dep
->dwc
;
291 spin_lock_irqsave(&dwc
->lock
, flags
);
292 ret
= __dwc3_gadget_ep0_set_halt(ep
, value
);
293 spin_unlock_irqrestore(&dwc
->lock
, flags
);
298 void dwc3_ep0_out_start(struct dwc3
*dwc
)
302 ret
= dwc3_ep0_start_trans(dwc
, 0, dwc
->ctrl_req_addr
, 8,
303 DWC3_TRBCTL_CONTROL_SETUP
);
307 static struct dwc3_ep
*dwc3_wIndex_to_dep(struct dwc3
*dwc
, __le16 wIndex_le
)
310 u32 windex
= le16_to_cpu(wIndex_le
);
313 epnum
= (windex
& USB_ENDPOINT_NUMBER_MASK
) << 1;
314 if ((windex
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
)
317 dep
= dwc
->eps
[epnum
];
318 if (dep
->flags
& DWC3_EP_ENABLED
)
324 static void dwc3_ep0_status_cmpl(struct usb_ep
*ep
, struct usb_request
*req
)
330 static int dwc3_ep0_handle_status(struct dwc3
*dwc
,
331 struct usb_ctrlrequest
*ctrl
)
337 __le16
*response_pkt
;
339 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
341 case USB_RECIP_DEVICE
:
343 * LTM will be set once we know how to set this in HW.
345 usb_status
|= dwc
->is_selfpowered
<< USB_DEVICE_SELF_POWERED
;
347 if (dwc
->speed
== DWC3_DSTS_SUPERSPEED
) {
348 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
349 if (reg
& DWC3_DCTL_INITU1ENA
)
350 usb_status
|= 1 << USB_DEV_STAT_U1_ENABLED
;
351 if (reg
& DWC3_DCTL_INITU2ENA
)
352 usb_status
|= 1 << USB_DEV_STAT_U2_ENABLED
;
357 case USB_RECIP_INTERFACE
:
359 * Function Remote Wake Capable D0
360 * Function Remote Wakeup D1
364 case USB_RECIP_ENDPOINT
:
365 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
369 if (dep
->flags
& DWC3_EP_STALL
)
370 usb_status
= 1 << USB_ENDPOINT_HALT
;
376 response_pkt
= (__le16
*) dwc
->setup_buf
;
377 *response_pkt
= cpu_to_le16(usb_status
);
380 dwc
->ep0_usb_req
.dep
= dep
;
381 dwc
->ep0_usb_req
.request
.length
= sizeof(*response_pkt
);
382 dwc
->ep0_usb_req
.request
.buf
= dwc
->setup_buf
;
383 dwc
->ep0_usb_req
.request
.complete
= dwc3_ep0_status_cmpl
;
385 return __dwc3_gadget_ep0_queue(dep
, &dwc
->ep0_usb_req
);
388 static int dwc3_ep0_handle_feature(struct dwc3
*dwc
,
389 struct usb_ctrlrequest
*ctrl
, int set
)
397 enum usb_device_state state
;
399 wValue
= le16_to_cpu(ctrl
->wValue
);
400 wIndex
= le16_to_cpu(ctrl
->wIndex
);
401 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
402 state
= dwc
->gadget
.state
;
405 case USB_RECIP_DEVICE
:
408 case USB_DEVICE_REMOTE_WAKEUP
:
411 * 9.4.1 says only only for SS, in AddressState only for
412 * default control pipe
414 case USB_DEVICE_U1_ENABLE
:
415 if (state
!= USB_STATE_CONFIGURED
)
417 if (dwc
->speed
!= DWC3_DSTS_SUPERSPEED
)
420 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
422 reg
|= DWC3_DCTL_INITU1ENA
;
424 reg
&= ~DWC3_DCTL_INITU1ENA
;
425 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
428 case USB_DEVICE_U2_ENABLE
:
429 if (state
!= USB_STATE_CONFIGURED
)
431 if (dwc
->speed
!= DWC3_DSTS_SUPERSPEED
)
434 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
436 reg
|= DWC3_DCTL_INITU2ENA
;
438 reg
&= ~DWC3_DCTL_INITU2ENA
;
439 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
442 case USB_DEVICE_LTM_ENABLE
:
445 case USB_DEVICE_TEST_MODE
:
446 if ((wIndex
& 0xff) != 0)
451 dwc
->test_mode_nr
= wIndex
>> 8;
452 dwc
->test_mode
= true;
459 case USB_RECIP_INTERFACE
:
461 case USB_INTRF_FUNC_SUSPEND
:
462 if (wIndex
& USB_INTRF_FUNC_SUSPEND_LP
)
463 /* XXX enable Low power suspend */
465 if (wIndex
& USB_INTRF_FUNC_SUSPEND_RW
)
466 /* XXX enable remote wakeup */
474 case USB_RECIP_ENDPOINT
:
476 case USB_ENDPOINT_HALT
:
477 dep
= dwc3_wIndex_to_dep(dwc
, wIndex
);
480 if (set
== 0 && (dep
->flags
& DWC3_EP_WEDGE
))
482 ret
= __dwc3_gadget_ep_set_halt(dep
, set
, true);
498 static int dwc3_ep0_set_address(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
500 enum usb_device_state state
= dwc
->gadget
.state
;
504 addr
= le16_to_cpu(ctrl
->wValue
);
506 dwc3_trace(trace_dwc3_ep0
, "invalid device address %d", addr
);
510 if (state
== USB_STATE_CONFIGURED
) {
511 dwc3_trace(trace_dwc3_ep0
,
512 "trying to set address when configured");
516 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
517 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
518 reg
|= DWC3_DCFG_DEVADDR(addr
);
519 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
522 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_ADDRESS
);
524 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_DEFAULT
);
529 static int dwc3_ep0_delegate_req(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
533 spin_unlock(&dwc
->lock
);
534 ret
= dwc
->gadget_driver
->setup(&dwc
->gadget
, ctrl
);
535 spin_lock(&dwc
->lock
);
539 static int dwc3_ep0_set_config(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
541 enum usb_device_state state
= dwc
->gadget
.state
;
546 dwc
->start_config_issued
= false;
547 cfg
= le16_to_cpu(ctrl
->wValue
);
550 case USB_STATE_DEFAULT
:
553 case USB_STATE_ADDRESS
:
554 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
555 /* if the cfg matches and the cfg is non zero */
556 if (cfg
&& (!ret
|| (ret
== USB_GADGET_DELAYED_STATUS
))) {
559 * only change state if set_config has already
560 * been processed. If gadget driver returns
561 * USB_GADGET_DELAYED_STATUS, we will wait
562 * to change the state on the next usb_ep_queue()
565 usb_gadget_set_state(&dwc
->gadget
,
566 USB_STATE_CONFIGURED
);
569 * Enable transition to U1/U2 state when
570 * nothing is pending from application.
572 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
573 reg
|= (DWC3_DCTL_ACCEPTU1ENA
| DWC3_DCTL_ACCEPTU2ENA
);
574 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
576 dwc
->resize_fifos
= true;
577 dwc3_trace(trace_dwc3_ep0
, "resize FIFOs flag SET");
581 case USB_STATE_CONFIGURED
:
582 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
584 usb_gadget_set_state(&dwc
->gadget
,
593 static void dwc3_ep0_set_sel_cmpl(struct usb_ep
*ep
, struct usb_request
*req
)
595 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
596 struct dwc3
*dwc
= dep
->dwc
;
610 memcpy(&timing
, req
->buf
, sizeof(timing
));
612 dwc
->u1sel
= timing
.u1sel
;
613 dwc
->u1pel
= timing
.u1pel
;
614 dwc
->u2sel
= le16_to_cpu(timing
.u2sel
);
615 dwc
->u2pel
= le16_to_cpu(timing
.u2pel
);
617 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
618 if (reg
& DWC3_DCTL_INITU2ENA
)
620 if (reg
& DWC3_DCTL_INITU1ENA
)
624 * According to Synopsys Databook, if parameter is
625 * greater than 125, a value of zero should be
626 * programmed in the register.
631 /* now that we have the time, issue DGCMD Set Sel */
632 ret
= dwc3_send_gadget_generic_command(dwc
,
633 DWC3_DGCMD_SET_PERIODIC_PAR
, param
);
637 static int dwc3_ep0_set_sel(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
640 enum usb_device_state state
= dwc
->gadget
.state
;
644 if (state
== USB_STATE_DEFAULT
)
647 wValue
= le16_to_cpu(ctrl
->wValue
);
648 wLength
= le16_to_cpu(ctrl
->wLength
);
651 dev_err(dwc
->dev
, "Set SEL should be 6 bytes, got %d\n",
657 * To handle Set SEL we need to receive 6 bytes from Host. So let's
658 * queue a usb_request for 6 bytes.
660 * Remember, though, this controller can't handle non-wMaxPacketSize
661 * aligned transfers on the OUT direction, so we queue a request for
662 * wMaxPacketSize instead.
665 dwc
->ep0_usb_req
.dep
= dep
;
666 dwc
->ep0_usb_req
.request
.length
= dep
->endpoint
.maxpacket
;
667 dwc
->ep0_usb_req
.request
.buf
= dwc
->setup_buf
;
668 dwc
->ep0_usb_req
.request
.complete
= dwc3_ep0_set_sel_cmpl
;
670 return __dwc3_gadget_ep0_queue(dep
, &dwc
->ep0_usb_req
);
673 static int dwc3_ep0_set_isoch_delay(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
679 wValue
= le16_to_cpu(ctrl
->wValue
);
680 wLength
= le16_to_cpu(ctrl
->wLength
);
681 wIndex
= le16_to_cpu(ctrl
->wIndex
);
683 if (wIndex
|| wLength
)
687 * REVISIT It's unclear from Databook what to do with this
688 * value. For now, just cache it.
690 dwc
->isoch_delay
= wValue
;
695 static int dwc3_ep0_std_request(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
699 switch (ctrl
->bRequest
) {
700 case USB_REQ_GET_STATUS
:
701 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_GET_STATUS");
702 ret
= dwc3_ep0_handle_status(dwc
, ctrl
);
704 case USB_REQ_CLEAR_FEATURE
:
705 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_CLEAR_FEATURE");
706 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 0);
708 case USB_REQ_SET_FEATURE
:
709 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_SET_FEATURE");
710 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 1);
712 case USB_REQ_SET_ADDRESS
:
713 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_SET_ADDRESS");
714 ret
= dwc3_ep0_set_address(dwc
, ctrl
);
716 case USB_REQ_SET_CONFIGURATION
:
717 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_SET_CONFIGURATION");
718 ret
= dwc3_ep0_set_config(dwc
, ctrl
);
720 case USB_REQ_SET_SEL
:
721 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_SET_SEL");
722 ret
= dwc3_ep0_set_sel(dwc
, ctrl
);
724 case USB_REQ_SET_ISOCH_DELAY
:
725 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_SET_ISOCH_DELAY");
726 ret
= dwc3_ep0_set_isoch_delay(dwc
, ctrl
);
729 dwc3_trace(trace_dwc3_ep0
, "Forwarding to gadget driver");
730 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
737 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
738 const struct dwc3_event_depevt
*event
)
740 struct usb_ctrlrequest
*ctrl
= dwc
->ctrl_req
;
744 if (!dwc
->gadget_driver
)
747 trace_dwc3_ctrl_req(ctrl
);
749 len
= le16_to_cpu(ctrl
->wLength
);
751 dwc
->three_stage_setup
= false;
752 dwc
->ep0_expect_in
= false;
753 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
755 dwc
->three_stage_setup
= true;
756 dwc
->ep0_expect_in
= !!(ctrl
->bRequestType
& USB_DIR_IN
);
757 dwc
->ep0_next_event
= DWC3_EP0_NRDY_DATA
;
760 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
)
761 ret
= dwc3_ep0_std_request(dwc
, ctrl
);
763 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
765 if (ret
== USB_GADGET_DELAYED_STATUS
)
766 dwc
->delayed_status
= true;
770 dwc3_ep0_stall_and_restart(dwc
);
773 static void dwc3_ep0_complete_data(struct dwc3
*dwc
,
774 const struct dwc3_event_depevt
*event
)
776 struct dwc3_request
*r
= NULL
;
777 struct usb_request
*ur
;
778 struct dwc3_trb
*trb
;
785 epnum
= event
->endpoint_number
;
788 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
792 trace_dwc3_complete_trb(ep0
, trb
);
794 r
= next_request(&ep0
->request_list
);
798 status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
799 if (status
== DWC3_TRBSTS_SETUP_PENDING
) {
800 dwc3_trace(trace_dwc3_ep0
, "Setup Pending received");
803 dwc3_gadget_giveback(ep0
, r
, -ECONNRESET
);
810 length
= trb
->size
& DWC3_TRB_SIZE_MASK
;
812 if (dwc
->ep0_bounced
) {
813 unsigned transfer_size
= ur
->length
;
814 unsigned maxp
= ep0
->endpoint
.maxpacket
;
816 transfer_size
+= (maxp
- (transfer_size
% maxp
));
817 transferred
= min_t(u32
, ur
->length
,
818 transfer_size
- length
);
819 memcpy(ur
->buf
, dwc
->ep0_bounce
, transferred
);
821 transferred
= ur
->length
- length
;
824 ur
->actual
+= transferred
;
826 if ((epnum
& 1) && ur
->actual
< ur
->length
) {
827 /* for some reason we did not get everything out */
829 dwc3_ep0_stall_and_restart(dwc
);
831 dwc3_gadget_giveback(ep0
, r
, 0);
833 if (IS_ALIGNED(ur
->length
, ep0
->endpoint
.maxpacket
) &&
834 ur
->length
&& ur
->zero
) {
837 dwc
->ep0_next_event
= DWC3_EP0_COMPLETE
;
839 ret
= dwc3_ep0_start_trans(dwc
, epnum
,
840 dwc
->ctrl_req_addr
, 0,
841 DWC3_TRBCTL_CONTROL_DATA
);
847 static void dwc3_ep0_complete_status(struct dwc3
*dwc
,
848 const struct dwc3_event_depevt
*event
)
850 struct dwc3_request
*r
;
852 struct dwc3_trb
*trb
;
858 trace_dwc3_complete_trb(dep
, trb
);
860 if (!list_empty(&dep
->request_list
)) {
861 r
= next_request(&dep
->request_list
);
863 dwc3_gadget_giveback(dep
, r
, 0);
866 if (dwc
->test_mode
) {
869 ret
= dwc3_gadget_set_test_mode(dwc
, dwc
->test_mode_nr
);
871 dwc3_trace(trace_dwc3_ep0
, "Invalid Test #%d",
873 dwc3_ep0_stall_and_restart(dwc
);
878 status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
879 if (status
== DWC3_TRBSTS_SETUP_PENDING
)
880 dwc3_trace(trace_dwc3_ep0
, "Setup Pending received");
882 dwc
->ep0state
= EP0_SETUP_PHASE
;
883 dwc3_ep0_out_start(dwc
);
886 static void dwc3_ep0_xfer_complete(struct dwc3
*dwc
,
887 const struct dwc3_event_depevt
*event
)
889 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
891 dep
->flags
&= ~DWC3_EP_BUSY
;
892 dep
->resource_index
= 0;
893 dwc
->setup_packet_pending
= false;
895 switch (dwc
->ep0state
) {
896 case EP0_SETUP_PHASE
:
897 dwc3_trace(trace_dwc3_ep0
, "Setup Phase");
898 dwc3_ep0_inspect_setup(dwc
, event
);
902 dwc3_trace(trace_dwc3_ep0
, "Data Phase");
903 dwc3_ep0_complete_data(dwc
, event
);
906 case EP0_STATUS_PHASE
:
907 dwc3_trace(trace_dwc3_ep0
, "Status Phase");
908 dwc3_ep0_complete_status(dwc
, event
);
911 WARN(true, "UNKNOWN ep0state %d\n", dwc
->ep0state
);
915 static void __dwc3_ep0_do_control_data(struct dwc3
*dwc
,
916 struct dwc3_ep
*dep
, struct dwc3_request
*req
)
920 req
->direction
= !!dep
->number
;
922 if (req
->request
.length
== 0) {
923 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
,
924 dwc
->ctrl_req_addr
, 0,
925 DWC3_TRBCTL_CONTROL_DATA
);
926 } else if (!IS_ALIGNED(req
->request
.length
, dep
->endpoint
.maxpacket
)
927 && (dep
->number
== 0)) {
931 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
934 dev_dbg(dwc
->dev
, "failed to map request\n");
938 WARN_ON(req
->request
.length
> DWC3_EP0_BOUNCE_SIZE
);
940 maxpacket
= dep
->endpoint
.maxpacket
;
941 transfer_size
= roundup(req
->request
.length
, maxpacket
);
943 dwc
->ep0_bounced
= true;
946 * REVISIT in case request length is bigger than
947 * DWC3_EP0_BOUNCE_SIZE we will need two chained
948 * TRBs to handle the transfer.
950 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
,
951 dwc
->ep0_bounce_addr
, transfer_size
,
952 DWC3_TRBCTL_CONTROL_DATA
);
954 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
957 dev_dbg(dwc
->dev
, "failed to map request\n");
961 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
, req
->request
.dma
,
962 req
->request
.length
, DWC3_TRBCTL_CONTROL_DATA
);
968 static int dwc3_ep0_start_control_status(struct dwc3_ep
*dep
)
970 struct dwc3
*dwc
= dep
->dwc
;
973 type
= dwc
->three_stage_setup
? DWC3_TRBCTL_CONTROL_STATUS3
974 : DWC3_TRBCTL_CONTROL_STATUS2
;
976 return dwc3_ep0_start_trans(dwc
, dep
->number
,
977 dwc
->ctrl_req_addr
, 0, type
);
980 static void __dwc3_ep0_do_control_status(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
982 if (dwc
->resize_fifos
) {
983 dwc3_trace(trace_dwc3_ep0
, "Resizing FIFOs");
984 dwc3_gadget_resize_tx_fifos(dwc
);
985 dwc
->resize_fifos
= 0;
988 WARN_ON(dwc3_ep0_start_control_status(dep
));
991 static void dwc3_ep0_do_control_status(struct dwc3
*dwc
,
992 const struct dwc3_event_depevt
*event
)
994 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
996 __dwc3_ep0_do_control_status(dwc
, dep
);
999 static void dwc3_ep0_end_control_data(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1001 struct dwc3_gadget_ep_cmd_params params
;
1005 if (!dep
->resource_index
)
1008 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
1009 cmd
|= DWC3_DEPCMD_CMDIOC
;
1010 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
1011 memset(¶ms
, 0, sizeof(params
));
1012 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
1014 dep
->resource_index
= 0;
1017 static void dwc3_ep0_xfernotready(struct dwc3
*dwc
,
1018 const struct dwc3_event_depevt
*event
)
1020 dwc
->setup_packet_pending
= true;
1022 switch (event
->status
) {
1023 case DEPEVT_STATUS_CONTROL_DATA
:
1024 dwc3_trace(trace_dwc3_ep0
, "Control Data");
1027 * We already have a DATA transfer in the controller's cache,
1028 * if we receive a XferNotReady(DATA) we will ignore it, unless
1029 * it's for the wrong direction.
1031 * In that case, we must issue END_TRANSFER command to the Data
1032 * Phase we already have started and issue SetStall on the
1035 if (dwc
->ep0_expect_in
!= event
->endpoint_number
) {
1036 struct dwc3_ep
*dep
= dwc
->eps
[dwc
->ep0_expect_in
];
1038 dwc3_trace(trace_dwc3_ep0
,
1039 "Wrong direction for Data phase");
1040 dwc3_ep0_end_control_data(dwc
, dep
);
1041 dwc3_ep0_stall_and_restart(dwc
);
1047 case DEPEVT_STATUS_CONTROL_STATUS
:
1048 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_STATUS
)
1051 dwc3_trace(trace_dwc3_ep0
, "Control Status");
1053 dwc
->ep0state
= EP0_STATUS_PHASE
;
1055 if (dwc
->delayed_status
) {
1056 WARN_ON_ONCE(event
->endpoint_number
!= 1);
1057 dwc3_trace(trace_dwc3_ep0
, "Delayed Status");
1061 dwc3_ep0_do_control_status(dwc
, event
);
1065 void dwc3_ep0_interrupt(struct dwc3
*dwc
,
1066 const struct dwc3_event_depevt
*event
)
1068 u8 epnum
= event
->endpoint_number
;
1070 dwc3_trace(trace_dwc3_ep0
, "%s while ep%d%s in state '%s'",
1071 dwc3_ep_event_string(event
->endpoint_event
),
1072 epnum
>> 1, (epnum
& 1) ? "in" : "out",
1073 dwc3_ep0_state_string(dwc
->ep0state
));
1075 switch (event
->endpoint_event
) {
1076 case DWC3_DEPEVT_XFERCOMPLETE
:
1077 dwc3_ep0_xfer_complete(dwc
, event
);
1080 case DWC3_DEPEVT_XFERNOTREADY
:
1081 dwc3_ep0_xfernotready(dwc
, event
);
1084 case DWC3_DEPEVT_XFERINPROGRESS
:
1085 case DWC3_DEPEVT_RXTXFIFOEVT
:
1086 case DWC3_DEPEVT_STREAMEVT
:
1087 case DWC3_DEPEVT_EPCMDCMPLT
: