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Merge git://git.denx.de/u-boot-usb
[people/ms/u-boot.git] / drivers / usb / host / dwc2.c
1 /*
2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <usb.h>
12 #include <malloc.h>
13 #include <memalign.h>
14 #include <phys2bus.h>
15 #include <usbroothubdes.h>
16 #include <wait_bit.h>
17 #include <asm/io.h>
18 #include <power/regulator.h>
19
20 #include "dwc2.h"
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 /* Use only HC channel 0. */
25 #define DWC2_HC_CHANNEL 0
26
27 #define DWC2_STATUS_BUF_SIZE 64
28 #define DWC2_DATA_BUF_SIZE (64 * 1024)
29
30 #define MAX_DEVICE 16
31 #define MAX_ENDPOINT 16
32
33 struct dwc2_priv {
34 #ifdef CONFIG_DM_USB
35 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
36 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
37 #else
38 uint8_t *aligned_buffer;
39 uint8_t *status_buffer;
40 #endif
41 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
42 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
43 struct dwc2_core_regs *regs;
44 int root_hub_devnum;
45 bool ext_vbus;
46 /*
47 * The hnp/srp capability must be disabled if the platform
48 * does't support hnp/srp. Otherwise the force mode can't work.
49 */
50 bool hnp_srp_disable;
51 bool oc_disable;
52 };
53
54 #ifndef CONFIG_DM_USB
55 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
56 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
57 ARCH_DMA_MINALIGN);
58 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
59 ARCH_DMA_MINALIGN);
60
61 static struct dwc2_priv local;
62 #endif
63
64 /*
65 * DWC2 IP interface
66 */
67
68 /*
69 * Initializes the FSLSPClkSel field of the HCFG register
70 * depending on the PHY type.
71 */
72 static void init_fslspclksel(struct dwc2_core_regs *regs)
73 {
74 uint32_t phyclk;
75
76 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
77 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
78 #else
79 /* High speed PHY running at full speed or high speed */
80 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
81 #endif
82
83 #ifdef CONFIG_DWC2_ULPI_FS_LS
84 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
85 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
86 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
87 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
88 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
89
90 if (hval == 2 && fval == 1)
91 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
92 #endif
93
94 clrsetbits_le32(&regs->host_regs.hcfg,
95 DWC2_HCFG_FSLSPCLKSEL_MASK,
96 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
97 }
98
99 /*
100 * Flush a Tx FIFO.
101 *
102 * @param regs Programming view of DWC_otg controller.
103 * @param num Tx FIFO to flush.
104 */
105 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
106 {
107 int ret;
108
109 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
110 &regs->grstctl);
111 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
112 false, 1000, false);
113 if (ret)
114 printf("%s: Timeout!\n", __func__);
115
116 /* Wait for 3 PHY Clocks */
117 udelay(1);
118 }
119
120 /*
121 * Flush Rx FIFO.
122 *
123 * @param regs Programming view of DWC_otg controller.
124 */
125 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
126 {
127 int ret;
128
129 writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
130 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
131 false, 1000, false);
132 if (ret)
133 printf("%s: Timeout!\n", __func__);
134
135 /* Wait for 3 PHY Clocks */
136 udelay(1);
137 }
138
139 /*
140 * Do core a soft reset of the core. Be careful with this because it
141 * resets all the internal state machines of the core.
142 */
143 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
144 {
145 int ret;
146
147 /* Wait for AHB master IDLE state. */
148 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
149 true, 1000, false);
150 if (ret)
151 printf("%s: Timeout!\n", __func__);
152
153 /* Core Soft Reset */
154 writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
155 ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
156 false, 1000, false);
157 if (ret)
158 printf("%s: Timeout!\n", __func__);
159
160 /*
161 * Wait for core to come out of reset.
162 * NOTE: This long sleep is _very_ important, otherwise the core will
163 * not stay in host mode after a connector ID change!
164 */
165 mdelay(100);
166 }
167
168 #if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
169 static int dwc_vbus_supply_init(struct udevice *dev)
170 {
171 struct udevice *vbus_supply;
172 int ret;
173
174 ret = device_get_supply_regulator(dev, "vbus-supply", &vbus_supply);
175 if (ret) {
176 debug("%s: No vbus supply\n", dev->name);
177 return 0;
178 }
179
180 ret = regulator_set_enable(vbus_supply, true);
181 if (ret) {
182 pr_err("Error enabling vbus supply\n");
183 return ret;
184 }
185
186 return 0;
187 }
188 #else
189 static int dwc_vbus_supply_init(struct udevice *dev)
190 {
191 return 0;
192 }
193 #endif
194
195 /*
196 * This function initializes the DWC_otg controller registers for
197 * host mode.
198 *
199 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
200 * request queues. Host channels are reset to ensure that they are ready for
201 * performing transfers.
202 *
203 * @param dev USB Device (NULL if driver model is not being used)
204 * @param regs Programming view of DWC_otg controller
205 *
206 */
207 static void dwc_otg_core_host_init(struct udevice *dev,
208 struct dwc2_core_regs *regs)
209 {
210 uint32_t nptxfifosize = 0;
211 uint32_t ptxfifosize = 0;
212 uint32_t hprt0 = 0;
213 int i, ret, num_channels;
214
215 /* Restart the Phy Clock */
216 writel(0, &regs->pcgcctl);
217
218 /* Initialize Host Configuration Register */
219 init_fslspclksel(regs);
220 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
221 setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
222 #endif
223
224 /* Configure data FIFO sizes */
225 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
226 if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
227 /* Rx FIFO */
228 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
229
230 /* Non-periodic Tx FIFO */
231 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
232 DWC2_FIFOSIZE_DEPTH_OFFSET;
233 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
234 DWC2_FIFOSIZE_STARTADDR_OFFSET;
235 writel(nptxfifosize, &regs->gnptxfsiz);
236
237 /* Periodic Tx FIFO */
238 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
239 DWC2_FIFOSIZE_DEPTH_OFFSET;
240 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
241 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
242 DWC2_FIFOSIZE_STARTADDR_OFFSET;
243 writel(ptxfifosize, &regs->hptxfsiz);
244 }
245 #endif
246
247 /* Clear Host Set HNP Enable in the OTG Control Register */
248 clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
249
250 /* Make sure the FIFOs are flushed. */
251 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
252 dwc_otg_flush_rx_fifo(regs);
253
254 /* Flush out any leftover queued requests. */
255 num_channels = readl(&regs->ghwcfg2);
256 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
257 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
258 num_channels += 1;
259
260 for (i = 0; i < num_channels; i++)
261 clrsetbits_le32(&regs->hc_regs[i].hcchar,
262 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
263 DWC2_HCCHAR_CHDIS);
264
265 /* Halt all channels to put them into a known state. */
266 for (i = 0; i < num_channels; i++) {
267 clrsetbits_le32(&regs->hc_regs[i].hcchar,
268 DWC2_HCCHAR_EPDIR,
269 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
270 ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
271 DWC2_HCCHAR_CHEN, false, 1000, false);
272 if (ret)
273 printf("%s: Timeout!\n", __func__);
274 }
275
276 /* Turn on the vbus power. */
277 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
278 hprt0 = readl(&regs->hprt0);
279 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
280 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
281 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
282 hprt0 |= DWC2_HPRT0_PRTPWR;
283 writel(hprt0, &regs->hprt0);
284 }
285 }
286
287 if (dev)
288 dwc_vbus_supply_init(dev);
289 }
290
291 /*
292 * This function initializes the DWC_otg controller registers and
293 * prepares the core for device mode or host mode operation.
294 *
295 * @param regs Programming view of the DWC_otg controller
296 */
297 static void dwc_otg_core_init(struct dwc2_priv *priv)
298 {
299 struct dwc2_core_regs *regs = priv->regs;
300 uint32_t ahbcfg = 0;
301 uint32_t usbcfg = 0;
302 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
303
304 /* Common Initialization */
305 usbcfg = readl(&regs->gusbcfg);
306
307 /* Program the ULPI External VBUS bit if needed */
308 if (priv->ext_vbus) {
309 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
310 if (!priv->oc_disable) {
311 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
312 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
313 }
314 } else {
315 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
316 }
317
318 /* Set external TS Dline pulsing */
319 #ifdef CONFIG_DWC2_TS_DLINE
320 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
321 #else
322 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
323 #endif
324 writel(usbcfg, &regs->gusbcfg);
325
326 /* Reset the Controller */
327 dwc_otg_core_reset(regs);
328
329 /*
330 * This programming sequence needs to happen in FS mode before
331 * any other programming occurs
332 */
333 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
334 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
335 /* If FS mode with FS PHY */
336 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
337
338 /* Reset after a PHY select */
339 dwc_otg_core_reset(regs);
340
341 /*
342 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
343 * Also do this on HNP Dev/Host mode switches (done in dev_init
344 * and host_init).
345 */
346 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
347 init_fslspclksel(regs);
348
349 #ifdef CONFIG_DWC2_I2C_ENABLE
350 /* Program GUSBCFG.OtgUtmifsSel to I2C */
351 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
352
353 /* Program GI2CCTL.I2CEn */
354 clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
355 DWC2_GI2CCTL_I2CDEVADDR_MASK,
356 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
357 setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
358 #endif
359
360 #else
361 /* High speed PHY. */
362
363 /*
364 * HS PHY parameters. These parameters are preserved during
365 * soft reset so only program the first time. Do a soft reset
366 * immediately after setting phyif.
367 */
368 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
369 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
370
371 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
372 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
373 usbcfg |= DWC2_GUSBCFG_DDRSEL;
374 #else
375 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
376 #endif
377 } else { /* UTMI+ interface */
378 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
379 usbcfg |= DWC2_GUSBCFG_PHYIF;
380 #endif
381 }
382
383 writel(usbcfg, &regs->gusbcfg);
384
385 /* Reset after setting the PHY parameters */
386 dwc_otg_core_reset(regs);
387 #endif
388
389 usbcfg = readl(&regs->gusbcfg);
390 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
391 #ifdef CONFIG_DWC2_ULPI_FS_LS
392 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
393 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
394 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
395 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
396 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
397 if (hval == 2 && fval == 1) {
398 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
399 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
400 }
401 #endif
402 if (priv->hnp_srp_disable)
403 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
404
405 writel(usbcfg, &regs->gusbcfg);
406
407 /* Program the GAHBCFG Register. */
408 switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
409 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
410 break;
411 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
412 while (brst_sz > 1) {
413 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
414 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
415 brst_sz >>= 1;
416 }
417
418 #ifdef CONFIG_DWC2_DMA_ENABLE
419 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
420 #endif
421 break;
422
423 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
424 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
425 #ifdef CONFIG_DWC2_DMA_ENABLE
426 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
427 #endif
428 break;
429 }
430
431 writel(ahbcfg, &regs->gahbcfg);
432
433 /* Program the capabilities in GUSBCFG Register */
434 usbcfg = 0;
435
436 if (!priv->hnp_srp_disable)
437 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
438 #ifdef CONFIG_DWC2_IC_USB_CAP
439 usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
440 #endif
441
442 setbits_le32(&regs->gusbcfg, usbcfg);
443 }
444
445 /*
446 * Prepares a host channel for transferring packets to/from a specific
447 * endpoint. The HCCHARn register is set up with the characteristics specified
448 * in _hc. Host channel interrupts that may need to be serviced while this
449 * transfer is in progress are enabled.
450 *
451 * @param regs Programming view of DWC_otg controller
452 * @param hc Information needed to initialize the host channel
453 */
454 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
455 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
456 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
457 {
458 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
459 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
460 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
461 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
462 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
463 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
464
465 if (dev->speed == USB_SPEED_LOW)
466 hcchar |= DWC2_HCCHAR_LSPDDEV;
467
468 /*
469 * Program the HCCHARn register with the endpoint characteristics
470 * for the current transfer.
471 */
472 writel(hcchar, &hc_regs->hcchar);
473
474 /* Program the HCSPLIT register, default to no SPLIT */
475 writel(0, &hc_regs->hcsplt);
476 }
477
478 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
479 uint8_t hub_devnum, uint8_t hub_port)
480 {
481 uint32_t hcsplt = 0;
482
483 hcsplt = DWC2_HCSPLT_SPLTENA;
484 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
485 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
486
487 /* Program the HCSPLIT register for SPLITs */
488 writel(hcsplt, &hc_regs->hcsplt);
489 }
490
491 /*
492 * DWC2 to USB API interface
493 */
494 /* Direction: In ; Request: Status */
495 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
496 struct usb_device *dev, void *buffer,
497 int txlen, struct devrequest *cmd)
498 {
499 uint32_t hprt0 = 0;
500 uint32_t port_status = 0;
501 uint32_t port_change = 0;
502 int len = 0;
503 int stat = 0;
504
505 switch (cmd->requesttype & ~USB_DIR_IN) {
506 case 0:
507 *(uint16_t *)buffer = cpu_to_le16(1);
508 len = 2;
509 break;
510 case USB_RECIP_INTERFACE:
511 case USB_RECIP_ENDPOINT:
512 *(uint16_t *)buffer = cpu_to_le16(0);
513 len = 2;
514 break;
515 case USB_TYPE_CLASS:
516 *(uint32_t *)buffer = cpu_to_le32(0);
517 len = 4;
518 break;
519 case USB_RECIP_OTHER | USB_TYPE_CLASS:
520 hprt0 = readl(&regs->hprt0);
521 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
522 port_status |= USB_PORT_STAT_CONNECTION;
523 if (hprt0 & DWC2_HPRT0_PRTENA)
524 port_status |= USB_PORT_STAT_ENABLE;
525 if (hprt0 & DWC2_HPRT0_PRTSUSP)
526 port_status |= USB_PORT_STAT_SUSPEND;
527 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
528 port_status |= USB_PORT_STAT_OVERCURRENT;
529 if (hprt0 & DWC2_HPRT0_PRTRST)
530 port_status |= USB_PORT_STAT_RESET;
531 if (hprt0 & DWC2_HPRT0_PRTPWR)
532 port_status |= USB_PORT_STAT_POWER;
533
534 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
535 port_status |= USB_PORT_STAT_LOW_SPEED;
536 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
537 DWC2_HPRT0_PRTSPD_HIGH)
538 port_status |= USB_PORT_STAT_HIGH_SPEED;
539
540 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
541 port_change |= USB_PORT_STAT_C_ENABLE;
542 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
543 port_change |= USB_PORT_STAT_C_CONNECTION;
544 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
545 port_change |= USB_PORT_STAT_C_OVERCURRENT;
546
547 *(uint32_t *)buffer = cpu_to_le32(port_status |
548 (port_change << 16));
549 len = 4;
550 break;
551 default:
552 puts("unsupported root hub command\n");
553 stat = USB_ST_STALLED;
554 }
555
556 dev->act_len = min(len, txlen);
557 dev->status = stat;
558
559 return stat;
560 }
561
562 /* Direction: In ; Request: Descriptor */
563 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
564 void *buffer, int txlen,
565 struct devrequest *cmd)
566 {
567 unsigned char data[32];
568 uint32_t dsc;
569 int len = 0;
570 int stat = 0;
571 uint16_t wValue = cpu_to_le16(cmd->value);
572 uint16_t wLength = cpu_to_le16(cmd->length);
573
574 switch (cmd->requesttype & ~USB_DIR_IN) {
575 case 0:
576 switch (wValue & 0xff00) {
577 case 0x0100: /* device descriptor */
578 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
579 memcpy(buffer, root_hub_dev_des, len);
580 break;
581 case 0x0200: /* configuration descriptor */
582 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
583 memcpy(buffer, root_hub_config_des, len);
584 break;
585 case 0x0300: /* string descriptors */
586 switch (wValue & 0xff) {
587 case 0x00:
588 len = min3(txlen, (int)sizeof(root_hub_str_index0),
589 (int)wLength);
590 memcpy(buffer, root_hub_str_index0, len);
591 break;
592 case 0x01:
593 len = min3(txlen, (int)sizeof(root_hub_str_index1),
594 (int)wLength);
595 memcpy(buffer, root_hub_str_index1, len);
596 break;
597 }
598 break;
599 default:
600 stat = USB_ST_STALLED;
601 }
602 break;
603
604 case USB_TYPE_CLASS:
605 /* Root port config, set 1 port and nothing else. */
606 dsc = 0x00000001;
607
608 data[0] = 9; /* min length; */
609 data[1] = 0x29;
610 data[2] = dsc & RH_A_NDP;
611 data[3] = 0;
612 if (dsc & RH_A_PSM)
613 data[3] |= 0x1;
614 if (dsc & RH_A_NOCP)
615 data[3] |= 0x10;
616 else if (dsc & RH_A_OCPM)
617 data[3] |= 0x8;
618
619 /* corresponds to data[4-7] */
620 data[5] = (dsc & RH_A_POTPGT) >> 24;
621 data[7] = dsc & RH_B_DR;
622 if (data[2] < 7) {
623 data[8] = 0xff;
624 } else {
625 data[0] += 2;
626 data[8] = (dsc & RH_B_DR) >> 8;
627 data[9] = 0xff;
628 data[10] = data[9];
629 }
630
631 len = min3(txlen, (int)data[0], (int)wLength);
632 memcpy(buffer, data, len);
633 break;
634 default:
635 puts("unsupported root hub command\n");
636 stat = USB_ST_STALLED;
637 }
638
639 dev->act_len = min(len, txlen);
640 dev->status = stat;
641
642 return stat;
643 }
644
645 /* Direction: In ; Request: Configuration */
646 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
647 void *buffer, int txlen,
648 struct devrequest *cmd)
649 {
650 int len = 0;
651 int stat = 0;
652
653 switch (cmd->requesttype & ~USB_DIR_IN) {
654 case 0:
655 *(uint8_t *)buffer = 0x01;
656 len = 1;
657 break;
658 default:
659 puts("unsupported root hub command\n");
660 stat = USB_ST_STALLED;
661 }
662
663 dev->act_len = min(len, txlen);
664 dev->status = stat;
665
666 return stat;
667 }
668
669 /* Direction: In */
670 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
671 struct usb_device *dev, void *buffer,
672 int txlen, struct devrequest *cmd)
673 {
674 switch (cmd->request) {
675 case USB_REQ_GET_STATUS:
676 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
677 txlen, cmd);
678 case USB_REQ_GET_DESCRIPTOR:
679 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
680 txlen, cmd);
681 case USB_REQ_GET_CONFIGURATION:
682 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
683 txlen, cmd);
684 default:
685 puts("unsupported root hub command\n");
686 return USB_ST_STALLED;
687 }
688 }
689
690 /* Direction: Out */
691 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
692 struct usb_device *dev,
693 void *buffer, int txlen,
694 struct devrequest *cmd)
695 {
696 struct dwc2_core_regs *regs = priv->regs;
697 int len = 0;
698 int stat = 0;
699 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
700 uint16_t wValue = cpu_to_le16(cmd->value);
701
702 switch (bmrtype_breq & ~USB_DIR_IN) {
703 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
704 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
705 break;
706
707 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
708 switch (wValue) {
709 case USB_PORT_FEAT_C_CONNECTION:
710 setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
711 break;
712 }
713 break;
714
715 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
716 switch (wValue) {
717 case USB_PORT_FEAT_SUSPEND:
718 break;
719
720 case USB_PORT_FEAT_RESET:
721 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
722 DWC2_HPRT0_PRTCONNDET |
723 DWC2_HPRT0_PRTENCHNG |
724 DWC2_HPRT0_PRTOVRCURRCHNG,
725 DWC2_HPRT0_PRTRST);
726 mdelay(50);
727 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
728 break;
729
730 case USB_PORT_FEAT_POWER:
731 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
732 DWC2_HPRT0_PRTCONNDET |
733 DWC2_HPRT0_PRTENCHNG |
734 DWC2_HPRT0_PRTOVRCURRCHNG,
735 DWC2_HPRT0_PRTRST);
736 break;
737
738 case USB_PORT_FEAT_ENABLE:
739 break;
740 }
741 break;
742 case (USB_REQ_SET_ADDRESS << 8):
743 priv->root_hub_devnum = wValue;
744 break;
745 case (USB_REQ_SET_CONFIGURATION << 8):
746 break;
747 default:
748 puts("unsupported root hub command\n");
749 stat = USB_ST_STALLED;
750 }
751
752 len = min(len, txlen);
753
754 dev->act_len = len;
755 dev->status = stat;
756
757 return stat;
758 }
759
760 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
761 unsigned long pipe, void *buffer, int txlen,
762 struct devrequest *cmd)
763 {
764 int stat = 0;
765
766 if (usb_pipeint(pipe)) {
767 puts("Root-Hub submit IRQ: NOT implemented\n");
768 return 0;
769 }
770
771 if (cmd->requesttype & USB_DIR_IN)
772 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
773 else
774 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
775
776 mdelay(1);
777
778 return stat;
779 }
780
781 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
782 {
783 int ret;
784 uint32_t hcint, hctsiz;
785
786 ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
787 1000, false);
788 if (ret)
789 return ret;
790
791 hcint = readl(&hc_regs->hcint);
792 hctsiz = readl(&hc_regs->hctsiz);
793 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
794 DWC2_HCTSIZ_XFERSIZE_OFFSET;
795 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
796
797 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
798 *toggle);
799
800 if (hcint & DWC2_HCINT_XFERCOMP)
801 return 0;
802
803 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
804 return -EAGAIN;
805
806 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
807 return -EINVAL;
808 }
809
810 static int dwc2_eptype[] = {
811 DWC2_HCCHAR_EPTYPE_ISOC,
812 DWC2_HCCHAR_EPTYPE_INTR,
813 DWC2_HCCHAR_EPTYPE_CONTROL,
814 DWC2_HCCHAR_EPTYPE_BULK,
815 };
816
817 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
818 u8 *pid, int in, void *buffer, int num_packets,
819 int xfer_len, int *actual_len, int odd_frame)
820 {
821 int ret = 0;
822 uint32_t sub;
823
824 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
825 *pid, xfer_len, num_packets);
826
827 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
828 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
829 (*pid << DWC2_HCTSIZ_PID_OFFSET),
830 &hc_regs->hctsiz);
831
832 if (xfer_len) {
833 if (in) {
834 invalidate_dcache_range(
835 (uintptr_t)aligned_buffer,
836 (uintptr_t)aligned_buffer +
837 roundup(xfer_len, ARCH_DMA_MINALIGN));
838 } else {
839 memcpy(aligned_buffer, buffer, xfer_len);
840 flush_dcache_range(
841 (uintptr_t)aligned_buffer,
842 (uintptr_t)aligned_buffer +
843 roundup(xfer_len, ARCH_DMA_MINALIGN));
844 }
845 }
846
847 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
848
849 /* Clear old interrupt conditions for this host channel. */
850 writel(0x3fff, &hc_regs->hcint);
851
852 /* Set host channel enable after all other setup is complete. */
853 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
854 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
855 DWC2_HCCHAR_ODDFRM,
856 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
857 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
858 DWC2_HCCHAR_CHEN);
859
860 ret = wait_for_chhltd(hc_regs, &sub, pid);
861 if (ret < 0)
862 return ret;
863
864 if (in) {
865 xfer_len -= sub;
866
867 invalidate_dcache_range((unsigned long)aligned_buffer,
868 (unsigned long)aligned_buffer +
869 roundup(xfer_len, ARCH_DMA_MINALIGN));
870
871 memcpy(buffer, aligned_buffer, xfer_len);
872 }
873 *actual_len = xfer_len;
874
875 return ret;
876 }
877
878 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
879 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
880 {
881 struct dwc2_core_regs *regs = priv->regs;
882 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
883 struct dwc2_host_regs *host_regs = &regs->host_regs;
884 int devnum = usb_pipedevice(pipe);
885 int ep = usb_pipeendpoint(pipe);
886 int max = usb_maxpacket(dev, pipe);
887 int eptype = dwc2_eptype[usb_pipetype(pipe)];
888 int done = 0;
889 int ret = 0;
890 int do_split = 0;
891 int complete_split = 0;
892 uint32_t xfer_len;
893 uint32_t num_packets;
894 int stop_transfer = 0;
895 uint32_t max_xfer_len;
896 int ssplit_frame_num = 0;
897
898 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
899 in, len);
900
901 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
902 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
903 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
904 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
905 max_xfer_len = DWC2_DATA_BUF_SIZE;
906
907 /* Make sure that max_xfer_len is a multiple of max packet size. */
908 num_packets = max_xfer_len / max;
909 max_xfer_len = num_packets * max;
910
911 /* Initialize channel */
912 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
913 eptype, max);
914
915 /* Check if the target is a FS/LS device behind a HS hub */
916 if (dev->speed != USB_SPEED_HIGH) {
917 uint8_t hub_addr;
918 uint8_t hub_port;
919 uint32_t hprt0 = readl(&regs->hprt0);
920 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
921 DWC2_HPRT0_PRTSPD_HIGH) {
922 usb_find_usb2_hub_address_port(dev, &hub_addr,
923 &hub_port);
924 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
925
926 do_split = 1;
927 num_packets = 1;
928 max_xfer_len = max;
929 }
930 }
931
932 do {
933 int actual_len = 0;
934 uint32_t hcint;
935 int odd_frame = 0;
936 xfer_len = len - done;
937
938 if (xfer_len > max_xfer_len)
939 xfer_len = max_xfer_len;
940 else if (xfer_len > max)
941 num_packets = (xfer_len + max - 1) / max;
942 else
943 num_packets = 1;
944
945 if (complete_split)
946 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
947 else if (do_split)
948 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
949
950 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
951 int uframe_num = readl(&host_regs->hfnum);
952 if (!(uframe_num & 0x1))
953 odd_frame = 1;
954 }
955
956 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
957 in, (char *)buffer + done, num_packets,
958 xfer_len, &actual_len, odd_frame);
959
960 hcint = readl(&hc_regs->hcint);
961 if (complete_split) {
962 stop_transfer = 0;
963 if (hcint & DWC2_HCINT_NYET) {
964 ret = 0;
965 int frame_num = DWC2_HFNUM_MAX_FRNUM &
966 readl(&host_regs->hfnum);
967 if (((frame_num - ssplit_frame_num) &
968 DWC2_HFNUM_MAX_FRNUM) > 4)
969 ret = -EAGAIN;
970 } else
971 complete_split = 0;
972 } else if (do_split) {
973 if (hcint & DWC2_HCINT_ACK) {
974 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
975 readl(&host_regs->hfnum);
976 ret = 0;
977 complete_split = 1;
978 }
979 }
980
981 if (ret)
982 break;
983
984 if (actual_len < xfer_len)
985 stop_transfer = 1;
986
987 done += actual_len;
988
989 /* Transactions are done when when either all data is transferred or
990 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
991 * is executed.
992 */
993 } while (((done < len) && !stop_transfer) || complete_split);
994
995 writel(0, &hc_regs->hcintmsk);
996 writel(0xFFFFFFFF, &hc_regs->hcint);
997
998 dev->status = 0;
999 dev->act_len = done;
1000
1001 return ret;
1002 }
1003
1004 /* U-Boot USB transmission interface */
1005 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1006 unsigned long pipe, void *buffer, int len)
1007 {
1008 int devnum = usb_pipedevice(pipe);
1009 int ep = usb_pipeendpoint(pipe);
1010 u8* pid;
1011
1012 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1013 dev->status = 0;
1014 return -EINVAL;
1015 }
1016
1017 if (usb_pipein(pipe))
1018 pid = &priv->in_data_toggle[devnum][ep];
1019 else
1020 pid = &priv->out_data_toggle[devnum][ep];
1021
1022 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1023 }
1024
1025 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1026 unsigned long pipe, void *buffer, int len,
1027 struct devrequest *setup)
1028 {
1029 int devnum = usb_pipedevice(pipe);
1030 int ret, act_len;
1031 u8 pid;
1032 /* For CONTROL endpoint pid should start with DATA1 */
1033 int status_direction;
1034
1035 if (devnum == priv->root_hub_devnum) {
1036 dev->status = 0;
1037 dev->speed = USB_SPEED_HIGH;
1038 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1039 setup);
1040 }
1041
1042 /* SETUP stage */
1043 pid = DWC2_HC_PID_SETUP;
1044 do {
1045 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1046 } while (ret == -EAGAIN);
1047 if (ret)
1048 return ret;
1049
1050 /* DATA stage */
1051 act_len = 0;
1052 if (buffer) {
1053 pid = DWC2_HC_PID_DATA1;
1054 do {
1055 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1056 buffer, len);
1057 act_len += dev->act_len;
1058 buffer += dev->act_len;
1059 len -= dev->act_len;
1060 } while (ret == -EAGAIN);
1061 if (ret)
1062 return ret;
1063 status_direction = usb_pipeout(pipe);
1064 } else {
1065 /* No-data CONTROL always ends with an IN transaction */
1066 status_direction = 1;
1067 }
1068
1069 /* STATUS stage */
1070 pid = DWC2_HC_PID_DATA1;
1071 do {
1072 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1073 priv->status_buffer, 0);
1074 } while (ret == -EAGAIN);
1075 if (ret)
1076 return ret;
1077
1078 dev->act_len = act_len;
1079
1080 return 0;
1081 }
1082
1083 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1084 unsigned long pipe, void *buffer, int len, int interval)
1085 {
1086 unsigned long timeout;
1087 int ret;
1088
1089 /* FIXME: what is interval? */
1090
1091 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1092 for (;;) {
1093 if (get_timer(0) > timeout) {
1094 printf("Timeout poll on interrupt endpoint\n");
1095 return -ETIMEDOUT;
1096 }
1097 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1098 if (ret != -EAGAIN)
1099 return ret;
1100 }
1101 }
1102
1103 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1104 {
1105 struct dwc2_core_regs *regs = priv->regs;
1106 uint32_t snpsid;
1107 int i, j;
1108
1109 snpsid = readl(&regs->gsnpsid);
1110 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
1111
1112 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1113 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1114 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
1115 return -ENODEV;
1116 }
1117
1118 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1119 priv->ext_vbus = 1;
1120 #else
1121 priv->ext_vbus = 0;
1122 #endif
1123
1124 dwc_otg_core_init(priv);
1125 dwc_otg_core_host_init(dev, regs);
1126
1127 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1128 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1129 DWC2_HPRT0_PRTOVRCURRCHNG,
1130 DWC2_HPRT0_PRTRST);
1131 mdelay(50);
1132 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1133 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1134 DWC2_HPRT0_PRTRST);
1135
1136 for (i = 0; i < MAX_DEVICE; i++) {
1137 for (j = 0; j < MAX_ENDPOINT; j++) {
1138 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1139 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1140 }
1141 }
1142
1143 /*
1144 * Add a 1 second delay here. This gives the host controller
1145 * a bit time before the comminucation with the USB devices
1146 * is started (the bus is scanned) and fixes the USB detection
1147 * problems with some problematic USB keys.
1148 */
1149 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1150 mdelay(1000);
1151
1152 return 0;
1153 }
1154
1155 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1156 {
1157 /* Put everything in reset. */
1158 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1159 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1160 DWC2_HPRT0_PRTOVRCURRCHNG,
1161 DWC2_HPRT0_PRTRST);
1162 }
1163
1164 #ifndef CONFIG_DM_USB
1165 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1166 int len, struct devrequest *setup)
1167 {
1168 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1169 }
1170
1171 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1172 int len)
1173 {
1174 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1175 }
1176
1177 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1178 int len, int interval)
1179 {
1180 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1181 }
1182
1183 /* U-Boot USB control interface */
1184 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1185 {
1186 struct dwc2_priv *priv = &local;
1187
1188 memset(priv, '\0', sizeof(*priv));
1189 priv->root_hub_devnum = 0;
1190 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1191 priv->aligned_buffer = aligned_buffer_addr;
1192 priv->status_buffer = status_buffer_addr;
1193
1194 /* board-dependant init */
1195 if (board_usb_init(index, USB_INIT_HOST))
1196 return -1;
1197
1198 return dwc2_init_common(NULL, priv);
1199 }
1200
1201 int usb_lowlevel_stop(int index)
1202 {
1203 dwc2_uninit_common(local.regs);
1204
1205 return 0;
1206 }
1207 #endif
1208
1209 #ifdef CONFIG_DM_USB
1210 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1211 unsigned long pipe, void *buffer, int length,
1212 struct devrequest *setup)
1213 {
1214 struct dwc2_priv *priv = dev_get_priv(dev);
1215
1216 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1217 dev->name, udev, udev->dev->name, udev->portnr);
1218
1219 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1220 }
1221
1222 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1223 unsigned long pipe, void *buffer, int length)
1224 {
1225 struct dwc2_priv *priv = dev_get_priv(dev);
1226
1227 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1228
1229 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1230 }
1231
1232 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1233 unsigned long pipe, void *buffer, int length,
1234 int interval)
1235 {
1236 struct dwc2_priv *priv = dev_get_priv(dev);
1237
1238 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1239
1240 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1241 }
1242
1243 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1244 {
1245 struct dwc2_priv *priv = dev_get_priv(dev);
1246 fdt_addr_t addr;
1247
1248 addr = dev_read_addr(dev);
1249 if (addr == FDT_ADDR_T_NONE)
1250 return -EINVAL;
1251 priv->regs = (struct dwc2_core_regs *)addr;
1252
1253 priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1254 priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1255
1256 return 0;
1257 }
1258
1259 static int dwc2_usb_probe(struct udevice *dev)
1260 {
1261 struct dwc2_priv *priv = dev_get_priv(dev);
1262 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1263
1264 bus_priv->desc_before_addr = true;
1265
1266 return dwc2_init_common(dev, priv);
1267 }
1268
1269 static int dwc2_usb_remove(struct udevice *dev)
1270 {
1271 struct dwc2_priv *priv = dev_get_priv(dev);
1272
1273 dwc2_uninit_common(priv->regs);
1274
1275 return 0;
1276 }
1277
1278 struct dm_usb_ops dwc2_usb_ops = {
1279 .control = dwc2_submit_control_msg,
1280 .bulk = dwc2_submit_bulk_msg,
1281 .interrupt = dwc2_submit_int_msg,
1282 };
1283
1284 static const struct udevice_id dwc2_usb_ids[] = {
1285 { .compatible = "brcm,bcm2835-usb" },
1286 { .compatible = "snps,dwc2" },
1287 { }
1288 };
1289
1290 U_BOOT_DRIVER(usb_dwc2) = {
1291 .name = "dwc2_usb",
1292 .id = UCLASS_USB,
1293 .of_match = dwc2_usb_ids,
1294 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1295 .probe = dwc2_usb_probe,
1296 .remove = dwc2_usb_remove,
1297 .ops = &dwc2_usb_ops,
1298 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1299 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1300 };
1301 #endif
"Das U-Boot" Source Tree