]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/usb/host/ehci-marvell.c
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/cpu.h>
15 #if defined(CONFIG_KIRKWOOD)
16 #include <asm/arch/kirkwood.h>
17 #elif defined(CONFIG_ORION5X)
18 #include <asm/arch/orion5x.h>
21 DECLARE_GLOBAL_DATA_PTR
;
23 #define rdl(off) readl(MVUSB0_BASE + (off))
24 #define wrl(off, val) writel((val), MVUSB0_BASE + (off))
26 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
27 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
28 #define USB_TARGET_DRAM 0x0
31 * USB 2.0 Bridge Address Decoding registers setup
33 static void usb_brg_adrdec_setup(void)
36 u32 size
, base
, attrib
;
38 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++) {
40 /* Enable DRAM bank */
43 attrib
= MVUSB0_CPU_ATTR_DRAM_CS0
;
46 attrib
= MVUSB0_CPU_ATTR_DRAM_CS1
;
49 attrib
= MVUSB0_CPU_ATTR_DRAM_CS2
;
52 attrib
= MVUSB0_CPU_ATTR_DRAM_CS3
;
55 /* invalide bank, disable access */
60 size
= gd
->bd
->bi_dram
[i
].size
;
61 base
= gd
->bd
->bi_dram
[i
].start
;
62 if ((size
) && (attrib
))
63 wrl(USB_WINDOW_CTRL(i
),
64 MVCPU_WIN_CTRL_DATA(size
, USB_TARGET_DRAM
,
65 attrib
, MVCPU_WIN_ENABLE
));
67 wrl(USB_WINDOW_CTRL(i
), MVCPU_WIN_DISABLE
);
69 wrl(USB_WINDOW_BASE(i
), base
);
74 * Create the appropriate control structures to manage
75 * a new EHCI host controller.
77 int ehci_hcd_init(int index
, struct ehci_hccr
**hccr
, struct ehci_hcor
**hcor
)
79 usb_brg_adrdec_setup();
81 *hccr
= (struct ehci_hccr
*)(MVUSB0_BASE
+ 0x100);
82 *hcor
= (struct ehci_hcor
*)((uint32_t) *hccr
83 + HC_LENGTH(ehci_readl(&(*hccr
)->cr_capbase
)));
85 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
86 (uint32_t)*hccr
, (uint32_t)*hcor
,
87 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr
)->cr_capbase
)));
93 * Destroy the appropriate control structures corresponding
94 * the the EHCI host controller.
96 int ehci_hcd_stop(int index
)