drivers/usb/host/ehci-mx6.c

   1 /*
   2  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
   3  * Copyright (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13  * for more details.
  14  */
  15
  16 #include <common.h>
  17 #include <usb.h>
  18 #include <errno.h>
  19 #include <linux/compiler.h>
  20 #include <usb/ehci-fsl.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/imx-regs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/mx6x_pins.h>
  25 #include <asm/arch/iomux-v3.h>
  26
  27 #include "ehci.h"
  28 #include "ehci-core.h"
  29
  30 #define USB_OTGREGS_OFFSET      0x000
  31 #define USB_H1REGS_OFFSET       0x200
  32 #define USB_H2REGS_OFFSET       0x400
  33 #define USB_H3REGS_OFFSET       0x600
  34 #define USB_OTHERREGS_OFFSET    0x800
  35
  36 #define USB_H1_CTRL_OFFSET      0x04
  37
  38 #define USBPHY_CTRL                             0x00000030
  39 #define USBPHY_CTRL_SET                         0x00000034
  40 #define USBPHY_CTRL_CLR                         0x00000038
  41 #define USBPHY_CTRL_TOG                         0x0000003c
  42
  43 #define USBPHY_PWD                              0x00000000
  44 #define USBPHY_CTRL_SFTRST                      0x80000000
  45 #define USBPHY_CTRL_CLKGATE                     0x40000000
  46 #define USBPHY_CTRL_ENUTMILEVEL3                0x00008000
  47 #define USBPHY_CTRL_ENUTMILEVEL2                0x00004000
  48
  49 #define ANADIG_USB2_CHRG_DETECT_EN_B            0x00100000
  50 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B      0x00080000
  51
  52 #define ANADIG_USB2_PLL_480_CTRL_BYPASS         0x00010000
  53 #define ANADIG_USB2_PLL_480_CTRL_ENABLE         0x00002000
  54 #define ANADIG_USB2_PLL_480_CTRL_POWER          0x00001000
  55 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS    0x00000040
  56
  57
  58 #define UCTRL_OVER_CUR_POL      (1 << 8) /* OTG Polarity of Overcurrent */
  59 #define UCTRL_OVER_CUR_DIS      (1 << 7) /* Disable OTG Overcurrent Detection */
  60
  61 /* USBCMD */
  62 #define UH1_USBCMD_OFFSET       0x140
  63 #define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
  64 #define UCMD_RESET              (1 << 1) /* controller reset */
  65
  66 static void usbh1_internal_phy_clock_gate(int on)
  67 {
  68         void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
  69
  70         phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
  71         __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
  72 }
  73
  74 static void usbh1_power_config(void)
  75 {
  76         struct anatop_regs __iomem *anatop =
  77                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  78         /*
  79          * Some phy and power's special controls for host1
  80          * 1. The external charger detector needs to be disabled
  81          * or the signal at DP will be poor
  82          * 2. The PLL's power and output to usb for host 1
  83          * is totally controlled by IC, so the Software only needs
  84          * to enable them at initializtion.
  85          */
  86         __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
  87                      ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
  88                      &anatop->usb2_chrg_detect);
  89
  90         __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
  91                      &anatop->usb2_pll_480_ctrl_clr);
  92
  93         __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
  94                      ANADIG_USB2_PLL_480_CTRL_POWER |
  95                      ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
  96                      &anatop->usb2_pll_480_ctrl_set);
  97 }
  98
  99 static int usbh1_phy_enable(void)
 100 {
 101         void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
 102         void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
 103         void __iomem *usb_cmd = (void __iomem *)(USBOH3_USB_BASE_ADDR +
 104                                                  USB_H1REGS_OFFSET +
 105                                                  UH1_USBCMD_OFFSET);
 106         u32 val;
 107
 108         /* Stop then Reset */
 109         val = __raw_readl(usb_cmd);
 110         val &= ~UCMD_RUN_STOP;
 111         __raw_writel(val, usb_cmd);
 112         while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
 113                 ;
 114
 115         val = __raw_readl(usb_cmd);
 116         val |= UCMD_RESET;
 117         __raw_writel(val, usb_cmd);
 118         while (__raw_readl(usb_cmd) & UCMD_RESET)
 119                 ;
 120
 121         /* Reset USBPHY module */
 122         val = __raw_readl(phy_ctrl);
 123         val |= USBPHY_CTRL_SFTRST;
 124         __raw_writel(val, phy_ctrl);
 125         udelay(10);
 126
 127         /* Remove CLKGATE and SFTRST */
 128         val = __raw_readl(phy_ctrl);
 129         val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
 130         __raw_writel(val, phy_ctrl);
 131         udelay(10);
 132
 133         /* Power up the PHY */
 134         __raw_writel(0, phy_reg + USBPHY_PWD);
 135         /* enable FS/LS device */
 136         val = __raw_readl(phy_reg + USBPHY_CTRL);
 137         val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
 138         __raw_writel(val, phy_reg + USBPHY_CTRL);
 139
 140         return 0;
 141 }
 142
 143 static void usbh1_oc_config(void)
 144 {
 145         void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
 146         void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
 147         u32 val;
 148
 149         val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
 150 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
 151         /* mx6qarm2 seems to required a different setting*/
 152         val &= ~UCTRL_OVER_CUR_POL;
 153 #else
 154         val |= UCTRL_OVER_CUR_POL;
 155 #endif
 156         __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
 157
 158         val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
 159         val |= UCTRL_OVER_CUR_DIS;
 160         __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
 161 }
 162
 163 int ehci_hcd_init(void)
 164 {
 165         struct usb_ehci *ehci;
 166
 167         enable_usboh3_clk(1);
 168         mdelay(1);
 169
 170         /* Do board specific initialization */
 171         board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
 172
 173 #if CONFIG_MXC_USB_PORT == 1
 174         /* USB Host 1 */
 175         usbh1_power_config();
 176         usbh1_oc_config();
 177         usbh1_internal_phy_clock_gate(1);
 178         usbh1_phy_enable();
 179 #else
 180 #error "MXC USB port not yet supported"
 181 #endif
 182
 183         ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
 184                 (0x200 * CONFIG_MXC_USB_PORT));
 185         hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 186         hcor = (struct ehci_hcor *)((uint32_t)hccr +
 187                         HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 188         setbits_le32(&ehci->usbmode, CM_HOST);
 189
 190         __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
 191         setbits_le32(&ehci->portsc, USB_EN);
 192
 193         mdelay(10);
 194
 195         return 0;
 196 }
 197
 198 int ehci_hcd_stop(void)
 199 {
 200         return 0;
 201 }