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[people/ms/u-boot.git] / drivers / usb / musb-new / am35x.c
1 /*
2 * Texas Instruments AM35x "glue layer"
3 *
4 * Copyright (c) 2010, by Texas Instruments
5 *
6 * Based on the DA8xx "glue layer" code.
7 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * SPDX-License-Identifier: GPL-2.0
12 *
13 */
14
15 #ifndef __UBOOT__
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/io.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23
24 #include <plat/usb.h>
25 #else
26 #include <common.h>
27 #include <asm/omap_musb.h>
28 #include "linux-compat.h"
29 #endif
30
31 #include "musb_core.h"
32
33 /*
34 * AM35x specific definitions
35 */
36 /* USB 2.0 OTG module registers */
37 #define USB_REVISION_REG 0x00
38 #define USB_CTRL_REG 0x04
39 #define USB_STAT_REG 0x08
40 #define USB_EMULATION_REG 0x0c
41 /* 0x10 Reserved */
42 #define USB_AUTOREQ_REG 0x14
43 #define USB_SRP_FIX_TIME_REG 0x18
44 #define USB_TEARDOWN_REG 0x1c
45 #define EP_INTR_SRC_REG 0x20
46 #define EP_INTR_SRC_SET_REG 0x24
47 #define EP_INTR_SRC_CLEAR_REG 0x28
48 #define EP_INTR_MASK_REG 0x2c
49 #define EP_INTR_MASK_SET_REG 0x30
50 #define EP_INTR_MASK_CLEAR_REG 0x34
51 #define EP_INTR_SRC_MASKED_REG 0x38
52 #define CORE_INTR_SRC_REG 0x40
53 #define CORE_INTR_SRC_SET_REG 0x44
54 #define CORE_INTR_SRC_CLEAR_REG 0x48
55 #define CORE_INTR_MASK_REG 0x4c
56 #define CORE_INTR_MASK_SET_REG 0x50
57 #define CORE_INTR_MASK_CLEAR_REG 0x54
58 #define CORE_INTR_SRC_MASKED_REG 0x58
59 /* 0x5c Reserved */
60 #define USB_END_OF_INTR_REG 0x60
61
62 /* Control register bits */
63 #define AM35X_SOFT_RESET_MASK 1
64
65 /* USB interrupt register bits */
66 #define AM35X_INTR_USB_SHIFT 16
67 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
68 #define AM35X_INTR_DRVVBUS 0x100
69 #define AM35X_INTR_RX_SHIFT 16
70 #define AM35X_INTR_TX_SHIFT 0
71 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
72 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
73 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
74 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
75
76 #define USB_MENTOR_CORE_OFFSET 0x400
77
78 struct am35x_glue {
79 struct device *dev;
80 struct platform_device *musb;
81 struct clk *phy_clk;
82 struct clk *clk;
83 };
84 #define glue_to_musb(g) platform_get_drvdata(g->musb)
85
86 /*
87 * am35x_musb_enable - enable interrupts
88 */
89 #ifndef __UBOOT__
90 static void am35x_musb_enable(struct musb *musb)
91 #else
92 static int am35x_musb_enable(struct musb *musb)
93 #endif
94 {
95 void __iomem *reg_base = musb->ctrl_base;
96 u32 epmask;
97
98 /* Workaround: setup IRQs through both register sets. */
99 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
100 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
101
102 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
103 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
104
105 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
106 if (is_otg_enabled(musb))
107 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
108 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
109 #ifdef __UBOOT__
110 return 0;
111 #endif
112 }
113
114 /*
115 * am35x_musb_disable - disable HDRC and flush interrupts
116 */
117 static void am35x_musb_disable(struct musb *musb)
118 {
119 void __iomem *reg_base = musb->ctrl_base;
120
121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
123 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
124 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
125 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
126 }
127
128 #ifndef __UBOOT__
129 #define portstate(stmt) stmt
130
131 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
132 {
133 WARN_ON(is_on && is_peripheral_active(musb));
134 }
135
136 #define POLL_SECONDS 2
137
138 static struct timer_list otg_workaround;
139
140 static void otg_timer(unsigned long _musb)
141 {
142 struct musb *musb = (void *)_musb;
143 void __iomem *mregs = musb->mregs;
144 u8 devctl;
145 unsigned long flags;
146
147 /*
148 * We poll because AM35x's won't expose several OTG-critical
149 * status change events (from the transceiver) otherwise.
150 */
151 devctl = musb_readb(mregs, MUSB_DEVCTL);
152 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
153 otg_state_string(musb->xceiv->state));
154
155 spin_lock_irqsave(&musb->lock, flags);
156 switch (musb->xceiv->state) {
157 case OTG_STATE_A_WAIT_BCON:
158 devctl &= ~MUSB_DEVCTL_SESSION;
159 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
160
161 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
162 if (devctl & MUSB_DEVCTL_BDEVICE) {
163 musb->xceiv->state = OTG_STATE_B_IDLE;
164 MUSB_DEV_MODE(musb);
165 } else {
166 musb->xceiv->state = OTG_STATE_A_IDLE;
167 MUSB_HST_MODE(musb);
168 }
169 break;
170 case OTG_STATE_A_WAIT_VFALL:
171 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
172 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
173 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
174 break;
175 case OTG_STATE_B_IDLE:
176 if (!is_peripheral_enabled(musb))
177 break;
178
179 devctl = musb_readb(mregs, MUSB_DEVCTL);
180 if (devctl & MUSB_DEVCTL_BDEVICE)
181 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
182 else
183 musb->xceiv->state = OTG_STATE_A_IDLE;
184 break;
185 default:
186 break;
187 }
188 spin_unlock_irqrestore(&musb->lock, flags);
189 }
190
191 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
192 {
193 static unsigned long last_timer;
194
195 if (!is_otg_enabled(musb))
196 return;
197
198 if (timeout == 0)
199 timeout = jiffies + msecs_to_jiffies(3);
200
201 /* Never idle if active, or when VBUS timeout is not set as host */
202 if (musb->is_active || (musb->a_wait_bcon == 0 &&
203 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
204 dev_dbg(musb->controller, "%s active, deleting timer\n",
205 otg_state_string(musb->xceiv->state));
206 del_timer(&otg_workaround);
207 last_timer = jiffies;
208 return;
209 }
210
211 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
212 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
213 return;
214 }
215 last_timer = timeout;
216
217 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
218 otg_state_string(musb->xceiv->state),
219 jiffies_to_msecs(timeout - jiffies));
220 mod_timer(&otg_workaround, timeout);
221 }
222 #endif
223
224 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
225 {
226 struct musb *musb = hci;
227 void __iomem *reg_base = musb->ctrl_base;
228 #ifndef __UBOOT__
229 struct device *dev = musb->controller;
230 struct musb_hdrc_platform_data *plat = dev->platform_data;
231 struct omap_musb_board_data *data = plat->board_data;
232 struct usb_otg *otg = musb->xceiv->otg;
233 #else
234 struct omap_musb_board_data *data =
235 (struct omap_musb_board_data *)musb->controller;
236 #endif
237 unsigned long flags;
238 irqreturn_t ret = IRQ_NONE;
239 u32 epintr, usbintr;
240
241 #ifdef __UBOOT__
242 /*
243 * It seems that on AM35X interrupt registers can be updated
244 * before core registers. This confuses the code.
245 * As a workaround add a small delay here.
246 */
247 udelay(10);
248 #endif
249 spin_lock_irqsave(&musb->lock, flags);
250
251 /* Get endpoint interrupts */
252 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
253
254 if (epintr) {
255 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
256
257 musb->int_rx =
258 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
259 musb->int_tx =
260 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
261 }
262
263 /* Get usb core interrupts */
264 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
265 if (!usbintr && !epintr)
266 goto eoi;
267
268 if (usbintr) {
269 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
270
271 musb->int_usb =
272 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
273 }
274 #ifndef __UBOOT__
275 /*
276 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
277 * AM35x's missing ID change IRQ. We need an ID change IRQ to
278 * switch appropriately between halves of the OTG state machine.
279 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
280 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
281 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
282 */
283 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
284 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
285 void __iomem *mregs = musb->mregs;
286 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
287 int err;
288
289 err = is_host_enabled(musb) && (musb->int_usb &
290 MUSB_INTR_VBUSERROR);
291 if (err) {
292 /*
293 * The Mentor core doesn't debounce VBUS as needed
294 * to cope with device connect current spikes. This
295 * means it's not uncommon for bus-powered devices
296 * to get VBUS errors during enumeration.
297 *
298 * This is a workaround, but newer RTL from Mentor
299 * seems to allow a better one: "re"-starting sessions
300 * without waiting for VBUS to stop registering in
301 * devctl.
302 */
303 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
304 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
305 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
306 WARNING("VBUS error workaround (delay coming)\n");
307 } else if (is_host_enabled(musb) && drvvbus) {
308 MUSB_HST_MODE(musb);
309 otg->default_a = 1;
310 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
311 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
312 del_timer(&otg_workaround);
313 } else {
314 musb->is_active = 0;
315 MUSB_DEV_MODE(musb);
316 otg->default_a = 0;
317 musb->xceiv->state = OTG_STATE_B_IDLE;
318 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
319 }
320
321 /* NOTE: this must complete power-on within 100 ms. */
322 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
323 drvvbus ? "on" : "off",
324 otg_state_string(musb->xceiv->state),
325 err ? " ERROR" : "",
326 devctl);
327 ret = IRQ_HANDLED;
328 }
329 #endif
330
331 if (musb->int_tx || musb->int_rx || musb->int_usb)
332 ret |= musb_interrupt(musb);
333
334 eoi:
335 /* EOI needs to be written for the IRQ to be re-asserted. */
336 if (ret == IRQ_HANDLED || epintr || usbintr) {
337 /* clear level interrupt */
338 if (data->clear_irq)
339 data->clear_irq();
340 /* write EOI */
341 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
342 }
343
344 #ifndef __UBOOT__
345 /* Poll for ID change */
346 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
347 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
348 #endif
349
350 spin_unlock_irqrestore(&musb->lock, flags);
351
352 return ret;
353 }
354
355 #ifndef __UBOOT__
356 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
357 {
358 struct device *dev = musb->controller;
359 struct musb_hdrc_platform_data *plat = dev->platform_data;
360 struct omap_musb_board_data *data = plat->board_data;
361 int retval = 0;
362
363 if (data->set_mode)
364 data->set_mode(musb_mode);
365 else
366 retval = -EIO;
367
368 return retval;
369 }
370 #endif
371
372 static int am35x_musb_init(struct musb *musb)
373 {
374 #ifndef __UBOOT__
375 struct device *dev = musb->controller;
376 struct musb_hdrc_platform_data *plat = dev->platform_data;
377 struct omap_musb_board_data *data = plat->board_data;
378 #else
379 struct omap_musb_board_data *data =
380 (struct omap_musb_board_data *)musb->controller;
381 #endif
382 void __iomem *reg_base = musb->ctrl_base;
383 u32 rev;
384
385 musb->mregs += USB_MENTOR_CORE_OFFSET;
386
387 /* Returns zero if e.g. not clocked */
388 rev = musb_readl(reg_base, USB_REVISION_REG);
389 if (!rev)
390 return -ENODEV;
391
392 #ifndef __UBOOT__
393 usb_nop_xceiv_register();
394 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
395 if (IS_ERR_OR_NULL(musb->xceiv))
396 return -ENODEV;
397
398 if (is_host_enabled(musb))
399 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
400 #endif
401
402 /* Reset the musb */
403 if (data->reset)
404 data->reset();
405
406 /* Reset the controller */
407 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
408
409 /* Start the on-chip PHY and its PLL. */
410 if (data->set_phy_power)
411 data->set_phy_power(1);
412
413 msleep(5);
414
415 musb->isr = am35x_musb_interrupt;
416
417 /* clear level interrupt */
418 if (data->clear_irq)
419 data->clear_irq();
420
421 return 0;
422 }
423
424 static int am35x_musb_exit(struct musb *musb)
425 {
426 #ifndef __UBOOT__
427 struct device *dev = musb->controller;
428 struct musb_hdrc_platform_data *plat = dev->platform_data;
429 struct omap_musb_board_data *data = plat->board_data;
430 #else
431 struct omap_musb_board_data *data =
432 (struct omap_musb_board_data *)musb->controller;
433 #endif
434
435 #ifndef __UBOOT__
436 if (is_host_enabled(musb))
437 del_timer_sync(&otg_workaround);
438 #endif
439
440 /* Shutdown the on-chip PHY and its PLL. */
441 if (data->set_phy_power)
442 data->set_phy_power(0);
443
444 #ifndef __UBOOT__
445 usb_put_phy(musb->xceiv);
446 usb_nop_xceiv_unregister();
447 #endif
448
449 return 0;
450 }
451
452 /* AM35x supports only 32bit read operation */
453 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
454 {
455 void __iomem *fifo = hw_ep->fifo;
456 u32 val;
457 int i;
458
459 /* Read for 32bit-aligned destination address */
460 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
461 readsl(fifo, dst, len >> 2);
462 dst += len & ~0x03;
463 len &= 0x03;
464 }
465 /*
466 * Now read the remaining 1 to 3 byte or complete length if
467 * unaligned address.
468 */
469 if (len > 4) {
470 for (i = 0; i < (len >> 2); i++) {
471 *(u32 *) dst = musb_readl(fifo, 0);
472 dst += 4;
473 }
474 len &= 0x03;
475 }
476 if (len > 0) {
477 val = musb_readl(fifo, 0);
478 memcpy(dst, &val, len);
479 }
480 }
481
482 #ifndef __UBOOT__
483 static const struct musb_platform_ops am35x_ops = {
484 #else
485 const struct musb_platform_ops am35x_ops = {
486 #endif
487 .init = am35x_musb_init,
488 .exit = am35x_musb_exit,
489
490 .enable = am35x_musb_enable,
491 .disable = am35x_musb_disable,
492
493 #ifndef __UBOOT__
494 .set_mode = am35x_musb_set_mode,
495 .try_idle = am35x_musb_try_idle,
496
497 .set_vbus = am35x_musb_set_vbus,
498 #endif
499 };
500
501 #ifndef __UBOOT__
502 static u64 am35x_dmamask = DMA_BIT_MASK(32);
503
504 static int __devinit am35x_probe(struct platform_device *pdev)
505 {
506 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
507 struct platform_device *musb;
508 struct am35x_glue *glue;
509
510 struct clk *phy_clk;
511 struct clk *clk;
512
513 int ret = -ENOMEM;
514
515 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
516 if (!glue) {
517 dev_err(&pdev->dev, "failed to allocate glue context\n");
518 goto err0;
519 }
520
521 musb = platform_device_alloc("musb-hdrc", -1);
522 if (!musb) {
523 dev_err(&pdev->dev, "failed to allocate musb device\n");
524 goto err1;
525 }
526
527 phy_clk = clk_get(&pdev->dev, "fck");
528 if (IS_ERR(phy_clk)) {
529 dev_err(&pdev->dev, "failed to get PHY clock\n");
530 ret = PTR_ERR(phy_clk);
531 goto err2;
532 }
533
534 clk = clk_get(&pdev->dev, "ick");
535 if (IS_ERR(clk)) {
536 dev_err(&pdev->dev, "failed to get clock\n");
537 ret = PTR_ERR(clk);
538 goto err3;
539 }
540
541 ret = clk_enable(phy_clk);
542 if (ret) {
543 dev_err(&pdev->dev, "failed to enable PHY clock\n");
544 goto err4;
545 }
546
547 ret = clk_enable(clk);
548 if (ret) {
549 dev_err(&pdev->dev, "failed to enable clock\n");
550 goto err5;
551 }
552
553 musb->dev.parent = &pdev->dev;
554 musb->dev.dma_mask = &am35x_dmamask;
555 musb->dev.coherent_dma_mask = am35x_dmamask;
556
557 glue->dev = &pdev->dev;
558 glue->musb = musb;
559 glue->phy_clk = phy_clk;
560 glue->clk = clk;
561
562 pdata->platform_ops = &am35x_ops;
563
564 platform_set_drvdata(pdev, glue);
565
566 ret = platform_device_add_resources(musb, pdev->resource,
567 pdev->num_resources);
568 if (ret) {
569 dev_err(&pdev->dev, "failed to add resources\n");
570 goto err6;
571 }
572
573 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
574 if (ret) {
575 dev_err(&pdev->dev, "failed to add platform_data\n");
576 goto err6;
577 }
578
579 ret = platform_device_add(musb);
580 if (ret) {
581 dev_err(&pdev->dev, "failed to register musb device\n");
582 goto err6;
583 }
584
585 return 0;
586
587 err6:
588 clk_disable(clk);
589
590 err5:
591 clk_disable(phy_clk);
592
593 err4:
594 clk_put(clk);
595
596 err3:
597 clk_put(phy_clk);
598
599 err2:
600 platform_device_put(musb);
601
602 err1:
603 kfree(glue);
604
605 err0:
606 return ret;
607 }
608
609 static int __devexit am35x_remove(struct platform_device *pdev)
610 {
611 struct am35x_glue *glue = platform_get_drvdata(pdev);
612
613 platform_device_del(glue->musb);
614 platform_device_put(glue->musb);
615 clk_disable(glue->clk);
616 clk_disable(glue->phy_clk);
617 clk_put(glue->clk);
618 clk_put(glue->phy_clk);
619 kfree(glue);
620
621 return 0;
622 }
623
624 #ifdef CONFIG_PM
625 static int am35x_suspend(struct device *dev)
626 {
627 struct am35x_glue *glue = dev_get_drvdata(dev);
628 struct musb_hdrc_platform_data *plat = dev->platform_data;
629 struct omap_musb_board_data *data = plat->board_data;
630
631 /* Shutdown the on-chip PHY and its PLL. */
632 if (data->set_phy_power)
633 data->set_phy_power(0);
634
635 clk_disable(glue->phy_clk);
636 clk_disable(glue->clk);
637
638 return 0;
639 }
640
641 static int am35x_resume(struct device *dev)
642 {
643 struct am35x_glue *glue = dev_get_drvdata(dev);
644 struct musb_hdrc_platform_data *plat = dev->platform_data;
645 struct omap_musb_board_data *data = plat->board_data;
646 int ret;
647
648 /* Start the on-chip PHY and its PLL. */
649 if (data->set_phy_power)
650 data->set_phy_power(1);
651
652 ret = clk_enable(glue->phy_clk);
653 if (ret) {
654 dev_err(dev, "failed to enable PHY clock\n");
655 return ret;
656 }
657
658 ret = clk_enable(glue->clk);
659 if (ret) {
660 dev_err(dev, "failed to enable clock\n");
661 return ret;
662 }
663
664 return 0;
665 }
666
667 static struct dev_pm_ops am35x_pm_ops = {
668 .suspend = am35x_suspend,
669 .resume = am35x_resume,
670 };
671
672 #define DEV_PM_OPS &am35x_pm_ops
673 #else
674 #define DEV_PM_OPS NULL
675 #endif
676
677 static struct platform_driver am35x_driver = {
678 .probe = am35x_probe,
679 .remove = __devexit_p(am35x_remove),
680 .driver = {
681 .name = "musb-am35x",
682 .pm = DEV_PM_OPS,
683 },
684 };
685
686 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
687 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
688 MODULE_LICENSE("GPL v2");
689
690 static int __init am35x_init(void)
691 {
692 return platform_driver_register(&am35x_driver);
693 }
694 module_init(am35x_init);
695
696 static void __exit am35x_exit(void)
697 {
698 platform_driver_unregister(&am35x_driver);
699 }
700 module_exit(am35x_exit);
701 #endif
"Das U-Boot" Source Tree