drivers/usb/musb/musb_core.h

   1 /******************************************************************
   2  * Copyright 2008 Mentor Graphics Corporation
   3  * Copyright (C) 2008 by Texas Instruments
   4  *
   5  * This file is part of the Inventra Controller Driver for Linux.
   6  *
   7  * The Inventra Controller Driver for Linux is free software; you
   8  * can redistribute it and/or modify it under the terms of the GNU
   9  * General Public License version 2 as published by the Free Software
  10  * Foundation.
  11  *
  12  * The Inventra Controller Driver for Linux is distributed in
  13  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  14  * without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16  * License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with The Inventra Controller Driver for Linux ; if not,
  20  * write to the Free Software Foundation, Inc., 59 Temple Place,
  21  * Suite 330, Boston, MA  02111-1307  USA
  22  *
  23  * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
  24  * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
  25  * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
  26  * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
  27  * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
  28  * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NON-INFRINGEMENT.  MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
  30  * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
  31  * GRAPHICS SUPPORT CUSTOMER.
  32  ******************************************************************/
  33
  34 #ifndef __MUSB_HDRC_DEFS_H__
  35 #define __MUSB_HDRC_DEFS_H__
  36
  37 #include <usb.h>
  38 #include <usb_defs.h>
  39 #include <asm/io.h>
  40
  41 #define MUSB_EP0_FIFOSIZE       64      /* This is non-configurable */
  42
  43 /* Mentor USB core register overlay structure */
  44 struct musb_regs {
  45         /* common registers */
  46         u8      faddr;
  47         u8      power;
  48         u16     intrtx;
  49         u16     intrrx;
  50         u16     intrtxe;
  51         u16     intrrxe;
  52         u8      intrusb;
  53         u8      intrusbe;
  54         u16     frame;
  55         u8      index;
  56         u8      testmode;
  57         /* indexed registers */
  58         u16     txmaxp;
  59         u16     txcsr;
  60         u16     rxmaxp;
  61         u16     rxcsr;
  62         u16     rxcount;
  63         u8      txtype;
  64         u8      txinterval;
  65         u8      rxtype;
  66         u8      rxinterval;
  67         u8      reserved0;
  68         u8      fifosize;
  69         /* fifo */
  70         u32     fifox[16];
  71         /* OTG, dynamic FIFO, version & vendor registers */
  72         u8      devctl;
  73         u8      reserved1;
  74         u8      txfifosz;
  75         u8      rxfifosz;
  76         u16     txfifoadd;
  77         u16     rxfifoadd;
  78         u32     vcontrol;
  79         u16     hwvers;
  80         u16     reserved2[5];
  81         u8      epinfo;
  82         u8      raminfo;
  83         u8      linkinfo;
  84         u8      vplen;
  85         u8      hseof1;
  86         u8      fseof1;
  87         u8      lseof1;
  88         u8      reserved3;
  89         /* target address registers */
  90         struct musb_tar_regs {
  91                 u8      txfuncaddr;
  92                 u8      reserved0;
  93                 u8      txhubaddr;
  94                 u8      txhubport;
  95                 u8      rxfuncaddr;
  96                 u8      reserved1;
  97                 u8      rxhubaddr;
  98                 u8      rxhubport;
  99         } tar[16];
 100 } __attribute((aligned(32)));
 101
 102 /*
 103  * MUSB Register bits
 104  */
 105
 106 /* POWER */
 107 #define MUSB_POWER_ISOUPDATE    0x80
 108 #define MUSB_POWER_SOFTCONN     0x40
 109 #define MUSB_POWER_HSENAB       0x20
 110 #define MUSB_POWER_HSMODE       0x10
 111 #define MUSB_POWER_RESET        0x08
 112 #define MUSB_POWER_RESUME       0x04
 113 #define MUSB_POWER_SUSPENDM     0x02
 114 #define MUSB_POWER_ENSUSPEND    0x01
 115 #define MUSB_POWER_HSMODE_SHIFT 4
 116
 117 /* INTRUSB */
 118 #define MUSB_INTR_SUSPEND       0x01
 119 #define MUSB_INTR_RESUME        0x02
 120 #define MUSB_INTR_RESET         0x04
 121 #define MUSB_INTR_BABBLE        0x04
 122 #define MUSB_INTR_SOF           0x08
 123 #define MUSB_INTR_CONNECT       0x10
 124 #define MUSB_INTR_DISCONNECT    0x20
 125 #define MUSB_INTR_SESSREQ       0x40
 126 #define MUSB_INTR_VBUSERROR     0x80    /* For SESSION end */
 127
 128 /* DEVCTL */
 129 #define MUSB_DEVCTL_BDEVICE     0x80
 130 #define MUSB_DEVCTL_FSDEV       0x40
 131 #define MUSB_DEVCTL_LSDEV       0x20
 132 #define MUSB_DEVCTL_VBUS        0x18
 133 #define MUSB_DEVCTL_VBUS_SHIFT  3
 134 #define MUSB_DEVCTL_HM          0x04
 135 #define MUSB_DEVCTL_HR          0x02
 136 #define MUSB_DEVCTL_SESSION     0x01
 137
 138 /* TESTMODE */
 139 #define MUSB_TEST_FORCE_HOST    0x80
 140 #define MUSB_TEST_FIFO_ACCESS   0x40
 141 #define MUSB_TEST_FORCE_FS      0x20
 142 #define MUSB_TEST_FORCE_HS      0x10
 143 #define MUSB_TEST_PACKET        0x08
 144 #define MUSB_TEST_K             0x04
 145 #define MUSB_TEST_J             0x02
 146 #define MUSB_TEST_SE0_NAK       0x01
 147
 148 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
 149 #define MUSB_FIFOSZ_DPB         0x10
 150 /* Allocation size (8, 16, 32, ... 4096) */
 151 #define MUSB_FIFOSZ_SIZE        0x0f
 152
 153 /* CSR0 */
 154 #define MUSB_CSR0_FLUSHFIFO     0x0100
 155 #define MUSB_CSR0_TXPKTRDY      0x0002
 156 #define MUSB_CSR0_RXPKTRDY      0x0001
 157
 158 /* CSR0 in Peripheral mode */
 159 #define MUSB_CSR0_P_SVDSETUPEND 0x0080
 160 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
 161 #define MUSB_CSR0_P_SENDSTALL   0x0020
 162 #define MUSB_CSR0_P_SETUPEND    0x0010
 163 #define MUSB_CSR0_P_DATAEND     0x0008
 164 #define MUSB_CSR0_P_SENTSTALL   0x0004
 165
 166 /* CSR0 in Host mode */
 167 #define MUSB_CSR0_H_DIS_PING            0x0800
 168 #define MUSB_CSR0_H_WR_DATATOGGLE       0x0400  /* Set to allow setting: */
 169 #define MUSB_CSR0_H_DATATOGGLE          0x0200  /* Data toggle control */
 170 #define MUSB_CSR0_H_NAKTIMEOUT          0x0080
 171 #define MUSB_CSR0_H_STATUSPKT           0x0040
 172 #define MUSB_CSR0_H_REQPKT              0x0020
 173 #define MUSB_CSR0_H_ERROR               0x0010
 174 #define MUSB_CSR0_H_SETUPPKT            0x0008
 175 #define MUSB_CSR0_H_RXSTALL             0x0004
 176
 177 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
 178 #define MUSB_CSR0_P_WZC_BITS    \
 179         (MUSB_CSR0_P_SENTSTALL)
 180 #define MUSB_CSR0_H_WZC_BITS    \
 181         (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
 182         | MUSB_CSR0_RXPKTRDY)
 183
 184 /* TxType/RxType */
 185 #define MUSB_TYPE_SPEED         0xc0
 186 #define MUSB_TYPE_SPEED_SHIFT   6
 187 #define MUSB_TYPE_SPEED_HIGH    1
 188 #define MUSB_TYPE_SPEED_FULL    2
 189 #define MUSB_TYPE_SPEED_LOW     3
 190 #define MUSB_TYPE_PROTO         0x30    /* Implicitly zero for ep0 */
 191 #define MUSB_TYPE_PROTO_SHIFT   4
 192 #define MUSB_TYPE_REMOTE_END    0xf     /* Implicitly zero for ep0 */
 193 #define MUSB_TYPE_PROTO_BULK    2
 194 #define MUSB_TYPE_PROTO_INTR    3
 195
 196 /* CONFIGDATA */
 197 #define MUSB_CONFIGDATA_MPRXE           0x80    /* Auto bulk pkt combining */
 198 #define MUSB_CONFIGDATA_MPTXE           0x40    /* Auto bulk pkt splitting */
 199 #define MUSB_CONFIGDATA_BIGENDIAN       0x20
 200 #define MUSB_CONFIGDATA_HBRXE           0x10    /* HB-ISO for RX */
 201 #define MUSB_CONFIGDATA_HBTXE           0x08    /* HB-ISO for TX */
 202 #define MUSB_CONFIGDATA_DYNFIFO         0x04    /* Dynamic FIFO sizing */
 203 #define MUSB_CONFIGDATA_SOFTCONE        0x02    /* SoftConnect */
 204 #define MUSB_CONFIGDATA_UTMIDW          0x01    /* Data width 0/1 => 8/16bits */
 205
 206 /* TXCSR in Peripheral and Host mode */
 207 #define MUSB_TXCSR_AUTOSET              0x8000
 208 #define MUSB_TXCSR_MODE                 0x2000
 209 #define MUSB_TXCSR_DMAENAB              0x1000
 210 #define MUSB_TXCSR_FRCDATATOG           0x0800
 211 #define MUSB_TXCSR_DMAMODE              0x0400
 212 #define MUSB_TXCSR_CLRDATATOG           0x0040
 213 #define MUSB_TXCSR_FLUSHFIFO            0x0008
 214 #define MUSB_TXCSR_FIFONOTEMPTY         0x0002
 215 #define MUSB_TXCSR_TXPKTRDY             0x0001
 216
 217 /* TXCSR in Peripheral mode */
 218 #define MUSB_TXCSR_P_ISO                0x4000
 219 #define MUSB_TXCSR_P_INCOMPTX           0x0080
 220 #define MUSB_TXCSR_P_SENTSTALL          0x0020
 221 #define MUSB_TXCSR_P_SENDSTALL          0x0010
 222 #define MUSB_TXCSR_P_UNDERRUN           0x0004
 223
 224 /* TXCSR in Host mode */
 225 #define MUSB_TXCSR_H_WR_DATATOGGLE      0x0200
 226 #define MUSB_TXCSR_H_DATATOGGLE         0x0100
 227 #define MUSB_TXCSR_H_NAKTIMEOUT         0x0080
 228 #define MUSB_TXCSR_H_RXSTALL            0x0020
 229 #define MUSB_TXCSR_H_ERROR              0x0004
 230 #define MUSB_TXCSR_H_DATATOGGLE_SHIFT   8
 231
 232 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 233 #define MUSB_TXCSR_P_WZC_BITS   \
 234         (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
 235         | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
 236 #define MUSB_TXCSR_H_WZC_BITS   \
 237         (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
 238         | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
 239
 240 /* RXCSR in Peripheral and Host mode */
 241 #define MUSB_RXCSR_AUTOCLEAR            0x8000
 242 #define MUSB_RXCSR_DMAENAB              0x2000
 243 #define MUSB_RXCSR_DISNYET              0x1000
 244 #define MUSB_RXCSR_PID_ERR              0x1000
 245 #define MUSB_RXCSR_DMAMODE              0x0800
 246 #define MUSB_RXCSR_INCOMPRX             0x0100
 247 #define MUSB_RXCSR_CLRDATATOG           0x0080
 248 #define MUSB_RXCSR_FLUSHFIFO            0x0010
 249 #define MUSB_RXCSR_DATAERROR            0x0008
 250 #define MUSB_RXCSR_FIFOFULL             0x0002
 251 #define MUSB_RXCSR_RXPKTRDY             0x0001
 252
 253 /* RXCSR in Peripheral mode */
 254 #define MUSB_RXCSR_P_ISO                0x4000
 255 #define MUSB_RXCSR_P_SENTSTALL          0x0040
 256 #define MUSB_RXCSR_P_SENDSTALL          0x0020
 257 #define MUSB_RXCSR_P_OVERRUN            0x0004
 258
 259 /* RXCSR in Host mode */
 260 #define MUSB_RXCSR_H_AUTOREQ            0x4000
 261 #define MUSB_RXCSR_H_WR_DATATOGGLE      0x0400
 262 #define MUSB_RXCSR_H_DATATOGGLE         0x0200
 263 #define MUSB_RXCSR_H_RXSTALL            0x0040
 264 #define MUSB_RXCSR_H_REQPKT             0x0020
 265 #define MUSB_RXCSR_H_ERROR              0x0004
 266 #define MUSB_S_RXCSR_H_DATATOGGLE       9
 267
 268 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 269 #define MUSB_RXCSR_P_WZC_BITS   \
 270         (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
 271         | MUSB_RXCSR_RXPKTRDY)
 272 #define MUSB_RXCSR_H_WZC_BITS   \
 273         (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
 274         | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
 275
 276 /* HUBADDR */
 277 #define MUSB_HUBADDR_MULTI_TT           0x80
 278
 279 /* Endpoint configuration information. Note: The value of endpoint fifo size
 280  * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other
 281  * values are not supported
 282  */
 283 struct musb_epinfo {
 284         u8      epnum;  /* endpoint number      */
 285         u8      epdir;  /* endpoint direction   */
 286         u16     epsize; /* endpoint FIFO size   */
 287 };
 288
 289 /*
 290  * Platform specific MUSB configuration. Any platform using the musb
 291  * functionality should create one instance of this structure in the
 292  * platform specific file.
 293  */
 294 struct musb_config {
 295         struct  musb_regs       *regs;
 296         u32                     timeout;
 297         u8                      musb_speed;
 298 };
 299
 300 /* externally defined data */
 301 extern struct musb_config       musb_cfg;
 302 extern struct musb_regs         *musbr;
 303
 304 /* exported functions */
 305 extern void musb_start(void);
 306 extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt);
 307 extern void write_fifo(u8 ep, u32 length, void *fifo_data);
 308 extern void read_fifo(u8 ep, u32 length, void *fifo_data);
 309
 310 /* extern functions */
 311 extern inline void musb_writew(u32 offset, u16 value);
 312 extern inline void musb_writeb(u32 offset, u8 value);
 313 extern inline u16 musb_readw(u32 offset);
 314 extern inline u8 musb_readb(u32 offset);
 315
 316 #endif  /* __MUSB_HDRC_DEFS_H__ */