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[people/ms/u-boot.git] / drivers / usb / musb / musb_hcd.c
1 /*
2 * Mentor USB OTG Core host controller driver.
3 *
4 * Copyright (c) 2008 Texas Instruments
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
9 */
10
11 #include <common.h>
12 #include <usb.h>
13 #include "musb_hcd.h"
14
15 /* MSC control transfers */
16 #define USB_MSC_BBB_RESET 0xFF
17 #define USB_MSC_BBB_GET_MAX_LUN 0xFE
18
19 /* Endpoint configuration information */
20 static const struct musb_epinfo epinfo[3] = {
21 {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
22 {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
23 {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
24 };
25
26 /* --- Virtual Root Hub ---------------------------------------------------- */
27 #ifdef MUSB_NO_MULTIPOINT
28 static int rh_devnum;
29 static u32 port_status;
30
31 /* Device descriptor */
32 static const u8 root_hub_dev_des[] = {
33 0x12, /* __u8 bLength; */
34 0x01, /* __u8 bDescriptorType; Device */
35 0x00, /* __u16 bcdUSB; v1.1 */
36 0x02,
37 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
38 0x00, /* __u8 bDeviceSubClass; */
39 0x00, /* __u8 bDeviceProtocol; */
40 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
41 0x00, /* __u16 idVendor; */
42 0x00,
43 0x00, /* __u16 idProduct; */
44 0x00,
45 0x00, /* __u16 bcdDevice; */
46 0x00,
47 0x00, /* __u8 iManufacturer; */
48 0x01, /* __u8 iProduct; */
49 0x00, /* __u8 iSerialNumber; */
50 0x01 /* __u8 bNumConfigurations; */
51 };
52
53 /* Configuration descriptor */
54 static const u8 root_hub_config_des[] = {
55 0x09, /* __u8 bLength; */
56 0x02, /* __u8 bDescriptorType; Configuration */
57 0x19, /* __u16 wTotalLength; */
58 0x00,
59 0x01, /* __u8 bNumInterfaces; */
60 0x01, /* __u8 bConfigurationValue; */
61 0x00, /* __u8 iConfiguration; */
62 0x40, /* __u8 bmAttributes;
63 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
64 0x00, /* __u8 MaxPower; */
65
66 /* interface */
67 0x09, /* __u8 if_bLength; */
68 0x04, /* __u8 if_bDescriptorType; Interface */
69 0x00, /* __u8 if_bInterfaceNumber; */
70 0x00, /* __u8 if_bAlternateSetting; */
71 0x01, /* __u8 if_bNumEndpoints; */
72 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
73 0x00, /* __u8 if_bInterfaceSubClass; */
74 0x00, /* __u8 if_bInterfaceProtocol; */
75 0x00, /* __u8 if_iInterface; */
76
77 /* endpoint */
78 0x07, /* __u8 ep_bLength; */
79 0x05, /* __u8 ep_bDescriptorType; Endpoint */
80 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
81 0x03, /* __u8 ep_bmAttributes; Interrupt */
82 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
83 0x02,
84 0xff /* __u8 ep_bInterval; 255 ms */
85 };
86
87 static const unsigned char root_hub_str_index0[] = {
88 0x04, /* __u8 bLength; */
89 0x03, /* __u8 bDescriptorType; String-descriptor */
90 0x09, /* __u8 lang ID */
91 0x04, /* __u8 lang ID */
92 };
93
94 static const unsigned char root_hub_str_index1[] = {
95 0x1c, /* __u8 bLength; */
96 0x03, /* __u8 bDescriptorType; String-descriptor */
97 'M', /* __u8 Unicode */
98 0, /* __u8 Unicode */
99 'U', /* __u8 Unicode */
100 0, /* __u8 Unicode */
101 'S', /* __u8 Unicode */
102 0, /* __u8 Unicode */
103 'B', /* __u8 Unicode */
104 0, /* __u8 Unicode */
105 ' ', /* __u8 Unicode */
106 0, /* __u8 Unicode */
107 'R', /* __u8 Unicode */
108 0, /* __u8 Unicode */
109 'o', /* __u8 Unicode */
110 0, /* __u8 Unicode */
111 'o', /* __u8 Unicode */
112 0, /* __u8 Unicode */
113 't', /* __u8 Unicode */
114 0, /* __u8 Unicode */
115 ' ', /* __u8 Unicode */
116 0, /* __u8 Unicode */
117 'H', /* __u8 Unicode */
118 0, /* __u8 Unicode */
119 'u', /* __u8 Unicode */
120 0, /* __u8 Unicode */
121 'b', /* __u8 Unicode */
122 0, /* __u8 Unicode */
123 };
124 #endif
125
126 /*
127 * This function writes the data toggle value.
128 */
129 static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
130 {
131 u16 toggle = usb_gettoggle(dev, ep, dir_out);
132 u16 csr;
133
134 if (dir_out) {
135 csr = readw(&musbr->txcsr);
136 if (!toggle) {
137 if (csr & MUSB_TXCSR_MODE)
138 csr = MUSB_TXCSR_CLRDATATOG;
139 else
140 csr = 0;
141 writew(csr, &musbr->txcsr);
142 } else {
143 csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
144 writew(csr, &musbr->txcsr);
145 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
146 writew(csr, &musbr->txcsr);
147 }
148 } else {
149 if (!toggle) {
150 csr = readw(&musbr->txcsr);
151 if (csr & MUSB_TXCSR_MODE)
152 csr = MUSB_RXCSR_CLRDATATOG;
153 else
154 csr = 0;
155 writew(csr, &musbr->rxcsr);
156 } else {
157 csr = readw(&musbr->rxcsr);
158 csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
159 writew(csr, &musbr->rxcsr);
160 csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
161 writew(csr, &musbr->rxcsr);
162 }
163 }
164 }
165
166 /*
167 * This function checks if RxStall has occured on the endpoint. If a RxStall
168 * has occured, the RxStall is cleared and 1 is returned. If RxStall has
169 * not occured, 0 is returned.
170 */
171 static u8 check_stall(u8 ep, u8 dir_out)
172 {
173 u16 csr;
174
175 /* For endpoint 0 */
176 if (!ep) {
177 csr = readw(&musbr->txcsr);
178 if (csr & MUSB_CSR0_H_RXSTALL) {
179 csr &= ~MUSB_CSR0_H_RXSTALL;
180 writew(csr, &musbr->txcsr);
181 return 1;
182 }
183 } else { /* For non-ep0 */
184 if (dir_out) { /* is it tx ep */
185 csr = readw(&musbr->txcsr);
186 if (csr & MUSB_TXCSR_H_RXSTALL) {
187 csr &= ~MUSB_TXCSR_H_RXSTALL;
188 writew(csr, &musbr->txcsr);
189 return 1;
190 }
191 } else { /* is it rx ep */
192 csr = readw(&musbr->rxcsr);
193 if (csr & MUSB_RXCSR_H_RXSTALL) {
194 csr &= ~MUSB_RXCSR_H_RXSTALL;
195 writew(csr, &musbr->rxcsr);
196 return 1;
197 }
198 }
199 }
200 return 0;
201 }
202
203 /*
204 * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
205 * error and -2 for stall.
206 */
207 static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
208 {
209 u16 csr;
210 int result = 1;
211 int timeout = CONFIG_MUSB_TIMEOUT;
212
213 while (result > 0) {
214 csr = readw(&musbr->txcsr);
215 if (csr & MUSB_CSR0_H_ERROR) {
216 csr &= ~MUSB_CSR0_H_ERROR;
217 writew(csr, &musbr->txcsr);
218 dev->status = USB_ST_CRC_ERR;
219 result = -1;
220 break;
221 }
222
223 switch (bit_mask) {
224 case MUSB_CSR0_TXPKTRDY:
225 if (!(csr & MUSB_CSR0_TXPKTRDY)) {
226 if (check_stall(MUSB_CONTROL_EP, 0)) {
227 dev->status = USB_ST_STALLED;
228 result = -2;
229 } else
230 result = 0;
231 }
232 break;
233
234 case MUSB_CSR0_RXPKTRDY:
235 if (check_stall(MUSB_CONTROL_EP, 0)) {
236 dev->status = USB_ST_STALLED;
237 result = -2;
238 } else
239 if (csr & MUSB_CSR0_RXPKTRDY)
240 result = 0;
241 break;
242
243 case MUSB_CSR0_H_REQPKT:
244 if (!(csr & MUSB_CSR0_H_REQPKT)) {
245 if (check_stall(MUSB_CONTROL_EP, 0)) {
246 dev->status = USB_ST_STALLED;
247 result = -2;
248 } else
249 result = 0;
250 }
251 break;
252 }
253
254 /* Check the timeout */
255 if (--timeout)
256 udelay(1);
257 else {
258 dev->status = USB_ST_CRC_ERR;
259 result = -1;
260 break;
261 }
262 }
263
264 return result;
265 }
266
267 /*
268 * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
269 */
270 static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
271 {
272 u16 csr;
273 int timeout = CONFIG_MUSB_TIMEOUT;
274
275 do {
276 if (check_stall(ep, 1)) {
277 dev->status = USB_ST_STALLED;
278 return 0;
279 }
280
281 csr = readw(&musbr->txcsr);
282 if (csr & MUSB_TXCSR_H_ERROR) {
283 dev->status = USB_ST_CRC_ERR;
284 return 0;
285 }
286
287 /* Check the timeout */
288 if (--timeout)
289 udelay(1);
290 else {
291 dev->status = USB_ST_CRC_ERR;
292 return -1;
293 }
294
295 } while (csr & MUSB_TXCSR_TXPKTRDY);
296 return 1;
297 }
298
299 /*
300 * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
301 */
302 static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
303 {
304 u16 csr;
305 int timeout = CONFIG_MUSB_TIMEOUT;
306
307 do {
308 if (check_stall(ep, 0)) {
309 dev->status = USB_ST_STALLED;
310 return 0;
311 }
312
313 csr = readw(&musbr->rxcsr);
314 if (csr & MUSB_RXCSR_H_ERROR) {
315 dev->status = USB_ST_CRC_ERR;
316 return 0;
317 }
318
319 /* Check the timeout */
320 if (--timeout)
321 udelay(1);
322 else {
323 dev->status = USB_ST_CRC_ERR;
324 return -1;
325 }
326
327 } while (!(csr & MUSB_RXCSR_RXPKTRDY));
328 return 1;
329 }
330
331 /*
332 * This function performs the setup phase of the control transfer
333 */
334 static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
335 {
336 int result;
337 u16 csr;
338
339 /* write the control request to ep0 fifo */
340 write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
341
342 /* enable transfer of setup packet */
343 csr = readw(&musbr->txcsr);
344 csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
345 writew(csr, &musbr->txcsr);
346
347 /* wait until the setup packet is transmitted */
348 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
349 dev->act_len = 0;
350 return result;
351 }
352
353 /*
354 * This function handles the control transfer in data phase
355 */
356 static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
357 {
358 u16 csr;
359 u32 rxlen = 0;
360 u32 nextlen = 0;
361 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
362 u8 *rxbuff = (u8 *)buffer;
363 u8 rxedlength;
364 int result;
365
366 while (rxlen < len) {
367 /* Determine the next read length */
368 nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
369
370 /* Set the ReqPkt bit */
371 csr = readw(&musbr->txcsr);
372 writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
373 result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
374 if (result < 0)
375 return result;
376
377 /* Actual number of bytes received by usb */
378 rxedlength = readb(&musbr->rxcount);
379
380 /* Read the data from the RxFIFO */
381 read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
382
383 /* Clear the RxPktRdy Bit */
384 csr = readw(&musbr->txcsr);
385 csr &= ~MUSB_CSR0_RXPKTRDY;
386 writew(csr, &musbr->txcsr);
387
388 /* short packet? */
389 if (rxedlength != nextlen) {
390 dev->act_len += rxedlength;
391 break;
392 }
393 rxlen += nextlen;
394 dev->act_len = rxlen;
395 }
396 return 0;
397 }
398
399 /*
400 * This function handles the control transfer out data phase
401 */
402 static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
403 {
404 u16 csr;
405 u32 txlen = 0;
406 u32 nextlen = 0;
407 u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
408 u8 *txbuff = (u8 *)buffer;
409 int result = 0;
410
411 while (txlen < len) {
412 /* Determine the next write length */
413 nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
414
415 /* Load the data to send in FIFO */
416 write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
417
418 /* Set TXPKTRDY bit */
419 csr = readw(&musbr->txcsr);
420 writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY,
421 &musbr->txcsr);
422 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
423 if (result < 0)
424 break;
425
426 txlen += nextlen;
427 dev->act_len = txlen;
428 }
429 return result;
430 }
431
432 /*
433 * This function handles the control transfer out status phase
434 */
435 static int ctrlreq_out_status_phase(struct usb_device *dev)
436 {
437 u16 csr;
438 int result;
439
440 /* Set the StatusPkt bit */
441 csr = readw(&musbr->txcsr);
442 csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY |
443 MUSB_CSR0_H_STATUSPKT);
444 writew(csr, &musbr->txcsr);
445
446 /* Wait until TXPKTRDY bit is cleared */
447 result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
448 return result;
449 }
450
451 /*
452 * This function handles the control transfer in status phase
453 */
454 static int ctrlreq_in_status_phase(struct usb_device *dev)
455 {
456 u16 csr;
457 int result;
458
459 /* Set the StatusPkt bit and ReqPkt bit */
460 csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
461 writew(csr, &musbr->txcsr);
462 result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
463
464 /* clear StatusPkt bit and RxPktRdy bit */
465 csr = readw(&musbr->txcsr);
466 csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
467 writew(csr, &musbr->txcsr);
468 return result;
469 }
470
471 /*
472 * determines the speed of the device (High/Full/Slow)
473 */
474 static u8 get_dev_speed(struct usb_device *dev)
475 {
476 return (dev->speed == USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
477 ((dev->speed == USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
478 MUSB_TYPE_SPEED_FULL);
479 }
480
481 /*
482 * configure the hub address and the port address.
483 */
484 static void config_hub_port(struct usb_device *dev, u8 ep)
485 {
486 u8 chid;
487 u8 hub;
488
489 /* Find out the nearest parent which is high speed */
490 while (dev->parent->parent != NULL)
491 if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH)
492 dev = dev->parent;
493 else
494 break;
495
496 /* determine the port address at that hub */
497 hub = dev->parent->devnum;
498 for (chid = 0; chid < USB_MAXCHILDREN; chid++)
499 if (dev->parent->children[chid] == dev)
500 break;
501
502 #ifndef MUSB_NO_MULTIPOINT
503 /* configure the hub address and the port address */
504 writeb(hub, &musbr->tar[ep].txhubaddr);
505 writeb((chid + 1), &musbr->tar[ep].txhubport);
506 writeb(hub, &musbr->tar[ep].rxhubaddr);
507 writeb((chid + 1), &musbr->tar[ep].rxhubport);
508 #endif
509 }
510
511 #ifdef MUSB_NO_MULTIPOINT
512
513 static void musb_port_reset(int do_reset)
514 {
515 u8 power = readb(&musbr->power);
516
517 if (do_reset) {
518 power &= 0xf0;
519 writeb(power | MUSB_POWER_RESET, &musbr->power);
520 port_status |= USB_PORT_STAT_RESET;
521 port_status &= ~USB_PORT_STAT_ENABLE;
522 udelay(30000);
523 } else {
524 writeb(power & ~MUSB_POWER_RESET, &musbr->power);
525
526 power = readb(&musbr->power);
527 if (power & MUSB_POWER_HSMODE)
528 port_status |= USB_PORT_STAT_HIGH_SPEED;
529
530 port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
531 port_status |= USB_PORT_STAT_ENABLE
532 | (USB_PORT_STAT_C_RESET << 16)
533 | (USB_PORT_STAT_C_ENABLE << 16);
534 }
535 }
536
537 /*
538 * root hub control
539 */
540 static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
541 void *buffer, int transfer_len,
542 struct devrequest *cmd)
543 {
544 int leni = transfer_len;
545 int len = 0;
546 int stat = 0;
547 u32 datab[4];
548 const u8 *data_buf = (u8 *) datab;
549 u16 bmRType_bReq;
550 u16 wValue;
551 u16 wIndex;
552 u16 wLength;
553 u16 int_usb;
554
555 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
556 debug("Root-Hub submit IRQ: NOT implemented\n");
557 return 0;
558 }
559
560 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
561 wValue = swap_16(cmd->value);
562 wIndex = swap_16(cmd->index);
563 wLength = swap_16(cmd->length);
564
565 debug("--- HUB ----------------------------------------\n");
566 debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
567 bmRType_bReq, wValue, wIndex, wLength);
568 debug("------------------------------------------------\n");
569
570 switch (bmRType_bReq) {
571 case RH_GET_STATUS:
572 debug("RH_GET_STATUS\n");
573
574 *(__u16 *) data_buf = swap_16(1);
575 len = 2;
576 break;
577
578 case RH_GET_STATUS | RH_INTERFACE:
579 debug("RH_GET_STATUS | RH_INTERFACE\n");
580
581 *(__u16 *) data_buf = swap_16(0);
582 len = 2;
583 break;
584
585 case RH_GET_STATUS | RH_ENDPOINT:
586 debug("RH_GET_STATUS | RH_ENDPOINT\n");
587
588 *(__u16 *) data_buf = swap_16(0);
589 len = 2;
590 break;
591
592 case RH_GET_STATUS | RH_CLASS:
593 debug("RH_GET_STATUS | RH_CLASS\n");
594
595 *(__u32 *) data_buf = swap_32(0);
596 len = 4;
597 break;
598
599 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
600 debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
601
602 int_usb = readw(&musbr->intrusb);
603 if (int_usb & MUSB_INTR_CONNECT) {
604 port_status |= USB_PORT_STAT_CONNECTION
605 | (USB_PORT_STAT_C_CONNECTION << 16);
606 port_status |= USB_PORT_STAT_HIGH_SPEED
607 | USB_PORT_STAT_ENABLE;
608 }
609
610 if (port_status & USB_PORT_STAT_RESET)
611 musb_port_reset(0);
612
613 *(__u32 *) data_buf = swap_32(port_status);
614 len = 4;
615 break;
616
617 case RH_CLEAR_FEATURE | RH_ENDPOINT:
618 debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
619
620 switch (wValue) {
621 case RH_ENDPOINT_STALL:
622 debug("C_HUB_ENDPOINT_STALL\n");
623 len = 0;
624 break;
625 }
626 port_status &= ~(1 << wValue);
627 break;
628
629 case RH_CLEAR_FEATURE | RH_CLASS:
630 debug("RH_CLEAR_FEATURE | RH_CLASS\n");
631
632 switch (wValue) {
633 case RH_C_HUB_LOCAL_POWER:
634 debug("C_HUB_LOCAL_POWER\n");
635 len = 0;
636 break;
637
638 case RH_C_HUB_OVER_CURRENT:
639 debug("C_HUB_OVER_CURRENT\n");
640 len = 0;
641 break;
642 }
643 port_status &= ~(1 << wValue);
644 break;
645
646 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
647 debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
648
649 switch (wValue) {
650 case RH_PORT_ENABLE:
651 len = 0;
652 break;
653
654 case RH_PORT_SUSPEND:
655 len = 0;
656 break;
657
658 case RH_PORT_POWER:
659 len = 0;
660 break;
661
662 case RH_C_PORT_CONNECTION:
663 len = 0;
664 break;
665
666 case RH_C_PORT_ENABLE:
667 len = 0;
668 break;
669
670 case RH_C_PORT_SUSPEND:
671 len = 0;
672 break;
673
674 case RH_C_PORT_OVER_CURRENT:
675 len = 0;
676 break;
677
678 case RH_C_PORT_RESET:
679 len = 0;
680 break;
681
682 default:
683 debug("invalid wValue\n");
684 stat = USB_ST_STALLED;
685 }
686
687 port_status &= ~(1 << wValue);
688 break;
689
690 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
691 debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
692
693 switch (wValue) {
694 case RH_PORT_SUSPEND:
695 len = 0;
696 break;
697
698 case RH_PORT_RESET:
699 musb_port_reset(1);
700 len = 0;
701 break;
702
703 case RH_PORT_POWER:
704 len = 0;
705 break;
706
707 case RH_PORT_ENABLE:
708 len = 0;
709 break;
710
711 default:
712 debug("invalid wValue\n");
713 stat = USB_ST_STALLED;
714 }
715
716 port_status |= 1 << wValue;
717 break;
718
719 case RH_SET_ADDRESS:
720 debug("RH_SET_ADDRESS\n");
721
722 rh_devnum = wValue;
723 len = 0;
724 break;
725
726 case RH_GET_DESCRIPTOR:
727 debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
728
729 switch (wValue) {
730 case (USB_DT_DEVICE << 8): /* device descriptor */
731 len = min_t(unsigned int,
732 leni, min_t(unsigned int,
733 sizeof(root_hub_dev_des),
734 wLength));
735 data_buf = root_hub_dev_des;
736 break;
737
738 case (USB_DT_CONFIG << 8): /* configuration descriptor */
739 len = min_t(unsigned int,
740 leni, min_t(unsigned int,
741 sizeof(root_hub_config_des),
742 wLength));
743 data_buf = root_hub_config_des;
744 break;
745
746 case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
747 len = min_t(unsigned int,
748 leni, min_t(unsigned int,
749 sizeof(root_hub_str_index0),
750 wLength));
751 data_buf = root_hub_str_index0;
752 break;
753
754 case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
755 len = min_t(unsigned int,
756 leni, min_t(unsigned int,
757 sizeof(root_hub_str_index1),
758 wLength));
759 data_buf = root_hub_str_index1;
760 break;
761
762 default:
763 debug("invalid wValue\n");
764 stat = USB_ST_STALLED;
765 }
766
767 break;
768
769 case RH_GET_DESCRIPTOR | RH_CLASS: {
770 u8 *_data_buf = (u8 *) datab;
771 debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
772
773 _data_buf[0] = 0x09; /* min length; */
774 _data_buf[1] = 0x29;
775 _data_buf[2] = 0x1; /* 1 port */
776 _data_buf[3] = 0x01; /* per-port power switching */
777 _data_buf[3] |= 0x10; /* no overcurrent reporting */
778
779 /* Corresponds to data_buf[4-7] */
780 _data_buf[4] = 0;
781 _data_buf[5] = 5;
782 _data_buf[6] = 0;
783 _data_buf[7] = 0x02;
784 _data_buf[8] = 0xff;
785
786 len = min_t(unsigned int, leni,
787 min_t(unsigned int, data_buf[0], wLength));
788 break;
789 }
790
791 case RH_GET_CONFIGURATION:
792 debug("RH_GET_CONFIGURATION\n");
793
794 *(__u8 *) data_buf = 0x01;
795 len = 1;
796 break;
797
798 case RH_SET_CONFIGURATION:
799 debug("RH_SET_CONFIGURATION\n");
800
801 len = 0;
802 break;
803
804 default:
805 debug("*** *** *** unsupported root hub command *** *** ***\n");
806 stat = USB_ST_STALLED;
807 }
808
809 len = min_t(int, len, leni);
810 if (buffer != data_buf)
811 memcpy(buffer, data_buf, len);
812
813 dev->act_len = len;
814 dev->status = stat;
815 debug("dev act_len %d, status %lu\n", dev->act_len, dev->status);
816
817 return stat;
818 }
819
820 static void musb_rh_init(void)
821 {
822 rh_devnum = 0;
823 port_status = 0;
824 }
825
826 #else
827
828 static void musb_rh_init(void) {}
829
830 #endif
831
832 /*
833 * do a control transfer
834 */
835 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
836 int len, struct devrequest *setup)
837 {
838 int devnum = usb_pipedevice(pipe);
839 u8 devspeed;
840
841 #ifdef MUSB_NO_MULTIPOINT
842 /* Control message is for the HUB? */
843 if (devnum == rh_devnum) {
844 int stat = musb_submit_rh_msg(dev, pipe, buffer, len, setup);
845 if (stat)
846 return stat;
847 }
848 #endif
849
850 /* select control endpoint */
851 writeb(MUSB_CONTROL_EP, &musbr->index);
852 readw(&musbr->txcsr);
853
854 #ifndef MUSB_NO_MULTIPOINT
855 /* target addr and (for multipoint) hub addr/port */
856 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
857 writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
858 #endif
859
860 /* configure the hub address and the port number as required */
861 devspeed = get_dev_speed(dev);
862 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
863 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
864 config_hub_port(dev, MUSB_CONTROL_EP);
865 writeb(devspeed << 6, &musbr->txtype);
866 } else {
867 writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
868 #ifndef MUSB_NO_MULTIPOINT
869 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
870 writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
871 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
872 writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
873 #endif
874 }
875
876 /* Control transfer setup phase */
877 if (ctrlreq_setup_phase(dev, setup) < 0)
878 return 0;
879
880 switch (setup->request) {
881 case USB_REQ_GET_DESCRIPTOR:
882 case USB_REQ_GET_CONFIGURATION:
883 case USB_REQ_GET_INTERFACE:
884 case USB_REQ_GET_STATUS:
885 case USB_MSC_BBB_GET_MAX_LUN:
886 /* control transfer in-data-phase */
887 if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
888 return 0;
889 /* control transfer out-status-phase */
890 if (ctrlreq_out_status_phase(dev) < 0)
891 return 0;
892 break;
893
894 case USB_REQ_SET_ADDRESS:
895 case USB_REQ_SET_CONFIGURATION:
896 case USB_REQ_SET_FEATURE:
897 case USB_REQ_SET_INTERFACE:
898 case USB_REQ_CLEAR_FEATURE:
899 case USB_MSC_BBB_RESET:
900 /* control transfer in status phase */
901 if (ctrlreq_in_status_phase(dev) < 0)
902 return 0;
903 break;
904
905 case USB_REQ_SET_DESCRIPTOR:
906 /* control transfer out data phase */
907 if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
908 return 0;
909 /* control transfer in status phase */
910 if (ctrlreq_in_status_phase(dev) < 0)
911 return 0;
912 break;
913
914 default:
915 /* unhandled control transfer */
916 return -1;
917 }
918
919 dev->status = 0;
920 dev->act_len = len;
921
922 #ifdef MUSB_NO_MULTIPOINT
923 /* Set device address to USB_FADDR register */
924 if (setup->request == USB_REQ_SET_ADDRESS)
925 writeb(dev->devnum, &musbr->faddr);
926 #endif
927
928 return len;
929 }
930
931 /*
932 * do a bulk transfer
933 */
934 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
935 void *buffer, int len)
936 {
937 int dir_out = usb_pipeout(pipe);
938 int ep = usb_pipeendpoint(pipe);
939 #ifndef MUSB_NO_MULTIPOINT
940 int devnum = usb_pipedevice(pipe);
941 #endif
942 u8 type;
943 u16 csr;
944 u32 txlen = 0;
945 u32 nextlen = 0;
946 u8 devspeed;
947
948 /* select bulk endpoint */
949 writeb(MUSB_BULK_EP, &musbr->index);
950
951 #ifndef MUSB_NO_MULTIPOINT
952 /* write the address of the device */
953 if (dir_out)
954 writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
955 else
956 writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
957 #endif
958
959 /* configure the hub address and the port number as required */
960 devspeed = get_dev_speed(dev);
961 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
962 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
963 /*
964 * MUSB is in high speed and the destination device is full
965 * speed device. So configure the hub address and port
966 * address registers.
967 */
968 config_hub_port(dev, MUSB_BULK_EP);
969 } else {
970 #ifndef MUSB_NO_MULTIPOINT
971 if (dir_out) {
972 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
973 writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
974 } else {
975 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
976 writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
977 }
978 #endif
979 devspeed = musb_cfg.musb_speed;
980 }
981
982 /* Write the saved toggle bit value */
983 write_toggle(dev, ep, dir_out);
984
985 if (dir_out) { /* bulk-out transfer */
986 /* Program the TxType register */
987 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
988 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
989 (ep & MUSB_TYPE_REMOTE_END);
990 writeb(type, &musbr->txtype);
991
992 /* Write maximum packet size to the TxMaxp register */
993 writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
994 while (txlen < len) {
995 nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
996 (len-txlen) : dev->epmaxpacketout[ep];
997
998 #ifdef CONFIG_USB_BLACKFIN
999 /* Set the transfer data size */
1000 writew(nextlen, &musbr->txcount);
1001 #endif
1002
1003 /* Write the data to the FIFO */
1004 write_fifo(MUSB_BULK_EP, nextlen,
1005 (void *)(((u8 *)buffer) + txlen));
1006
1007 /* Set the TxPktRdy bit */
1008 csr = readw(&musbr->txcsr);
1009 writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
1010
1011 /* Wait until the TxPktRdy bit is cleared */
1012 if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) {
1013 readw(&musbr->txcsr);
1014 usb_settoggle(dev, ep, dir_out,
1015 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
1016 dev->act_len = txlen;
1017 return 0;
1018 }
1019 txlen += nextlen;
1020 }
1021
1022 /* Keep a copy of the data toggle bit */
1023 csr = readw(&musbr->txcsr);
1024 usb_settoggle(dev, ep, dir_out,
1025 (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
1026 } else { /* bulk-in transfer */
1027 /* Write the saved toggle bit value */
1028 write_toggle(dev, ep, dir_out);
1029
1030 /* Program the RxType register */
1031 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1032 (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
1033 (ep & MUSB_TYPE_REMOTE_END);
1034 writeb(type, &musbr->rxtype);
1035
1036 /* Write the maximum packet size to the RxMaxp register */
1037 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
1038 while (txlen < len) {
1039 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
1040 (len-txlen) : dev->epmaxpacketin[ep];
1041
1042 /* Set the ReqPkt bit */
1043 csr = readw(&musbr->rxcsr);
1044 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
1045
1046 /* Wait until the RxPktRdy bit is set */
1047 if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) {
1048 csr = readw(&musbr->rxcsr);
1049 usb_settoggle(dev, ep, dir_out,
1050 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1051 csr &= ~MUSB_RXCSR_RXPKTRDY;
1052 writew(csr, &musbr->rxcsr);
1053 dev->act_len = txlen;
1054 return 0;
1055 }
1056
1057 /* Read the data from the FIFO */
1058 read_fifo(MUSB_BULK_EP, nextlen,
1059 (void *)(((u8 *)buffer) + txlen));
1060
1061 /* Clear the RxPktRdy bit */
1062 csr = readw(&musbr->rxcsr);
1063 csr &= ~MUSB_RXCSR_RXPKTRDY;
1064 writew(csr, &musbr->rxcsr);
1065 txlen += nextlen;
1066 }
1067
1068 /* Keep a copy of the data toggle bit */
1069 csr = readw(&musbr->rxcsr);
1070 usb_settoggle(dev, ep, dir_out,
1071 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1072 }
1073
1074 /* bulk transfer is complete */
1075 dev->status = 0;
1076 dev->act_len = len;
1077 return 0;
1078 }
1079
1080 /*
1081 * This function initializes the usb controller module.
1082 */
1083 int usb_lowlevel_init(int index, void **controller)
1084 {
1085 u8 power;
1086 u32 timeout;
1087
1088 musb_rh_init();
1089
1090 if (musb_platform_init() == -1)
1091 return -1;
1092
1093 /* Configure all the endpoint FIFO's and start usb controller */
1094 musbr = musb_cfg.regs;
1095 musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
1096 musb_start();
1097
1098 /*
1099 * Wait until musb is enabled in host mode with a timeout. There
1100 * should be a usb device connected.
1101 */
1102 timeout = musb_cfg.timeout;
1103 while (--timeout)
1104 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
1105 break;
1106
1107 /* if musb core is not in host mode, then return */
1108 if (!timeout)
1109 return -1;
1110
1111 /* start usb bus reset */
1112 power = readb(&musbr->power);
1113 writeb(power | MUSB_POWER_RESET, &musbr->power);
1114
1115 /* After initiating a usb reset, wait for about 20ms to 30ms */
1116 udelay(30000);
1117
1118 /* stop usb bus reset */
1119 power = readb(&musbr->power);
1120 power &= ~MUSB_POWER_RESET;
1121 writeb(power, &musbr->power);
1122
1123 /* Determine if the connected device is a high/full/low speed device */
1124 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
1125 MUSB_TYPE_SPEED_HIGH :
1126 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
1127 MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
1128 return 0;
1129 }
1130
1131 /*
1132 * This function stops the operation of the davinci usb module.
1133 */
1134 int usb_lowlevel_stop(int index)
1135 {
1136 /* Reset the USB module */
1137 musb_platform_deinit();
1138 writeb(0, &musbr->devctl);
1139 return 0;
1140 }
1141
1142 /*
1143 * This function supports usb interrupt transfers. Currently, usb interrupt
1144 * transfers are not supported.
1145 */
1146 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1147 void *buffer, int len, int interval)
1148 {
1149 int dir_out = usb_pipeout(pipe);
1150 int ep = usb_pipeendpoint(pipe);
1151 #ifndef MUSB_NO_MULTIPOINT
1152 int devnum = usb_pipedevice(pipe);
1153 #endif
1154 u8 type;
1155 u16 csr;
1156 u32 txlen = 0;
1157 u32 nextlen = 0;
1158 u8 devspeed;
1159
1160 /* select interrupt endpoint */
1161 writeb(MUSB_INTR_EP, &musbr->index);
1162
1163 #ifndef MUSB_NO_MULTIPOINT
1164 /* write the address of the device */
1165 if (dir_out)
1166 writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
1167 else
1168 writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
1169 #endif
1170
1171 /* configure the hub address and the port number as required */
1172 devspeed = get_dev_speed(dev);
1173 if ((musb_ishighspeed()) && (dev->parent != NULL) &&
1174 (devspeed != MUSB_TYPE_SPEED_HIGH)) {
1175 /*
1176 * MUSB is in high speed and the destination device is full
1177 * speed device. So configure the hub address and port
1178 * address registers.
1179 */
1180 config_hub_port(dev, MUSB_INTR_EP);
1181 } else {
1182 #ifndef MUSB_NO_MULTIPOINT
1183 if (dir_out) {
1184 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
1185 writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
1186 } else {
1187 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
1188 writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
1189 }
1190 #endif
1191 devspeed = musb_cfg.musb_speed;
1192 }
1193
1194 /* Write the saved toggle bit value */
1195 write_toggle(dev, ep, dir_out);
1196
1197 if (!dir_out) { /* intrrupt-in transfer */
1198 /* Write the saved toggle bit value */
1199 write_toggle(dev, ep, dir_out);
1200 writeb(interval, &musbr->rxinterval);
1201
1202 /* Program the RxType register */
1203 type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
1204 (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
1205 (ep & MUSB_TYPE_REMOTE_END);
1206 writeb(type, &musbr->rxtype);
1207
1208 /* Write the maximum packet size to the RxMaxp register */
1209 writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
1210
1211 while (txlen < len) {
1212 nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
1213 (len-txlen) : dev->epmaxpacketin[ep];
1214
1215 /* Set the ReqPkt bit */
1216 csr = readw(&musbr->rxcsr);
1217 writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
1218
1219 /* Wait until the RxPktRdy bit is set */
1220 if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) {
1221 csr = readw(&musbr->rxcsr);
1222 usb_settoggle(dev, ep, dir_out,
1223 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1224 csr &= ~MUSB_RXCSR_RXPKTRDY;
1225 writew(csr, &musbr->rxcsr);
1226 dev->act_len = txlen;
1227 return 0;
1228 }
1229
1230 /* Read the data from the FIFO */
1231 read_fifo(MUSB_INTR_EP, nextlen,
1232 (void *)(((u8 *)buffer) + txlen));
1233
1234 /* Clear the RxPktRdy bit */
1235 csr = readw(&musbr->rxcsr);
1236 csr &= ~MUSB_RXCSR_RXPKTRDY;
1237 writew(csr, &musbr->rxcsr);
1238 txlen += nextlen;
1239 }
1240
1241 /* Keep a copy of the data toggle bit */
1242 csr = readw(&musbr->rxcsr);
1243 usb_settoggle(dev, ep, dir_out,
1244 (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
1245 }
1246
1247 /* interrupt transfer is complete */
1248 dev->irq_status = 0;
1249 dev->irq_act_len = len;
1250 dev->irq_handle(dev);
1251 dev->status = 0;
1252 dev->act_len = len;
1253 return 0;
1254 }
"Das U-Boot" Source Tree