2 * From coreboot src/soc/intel/broadwell/igd.c
4 * Copyright (C) 2016 Google, Inc
6 * SPDX-License-Identifier: GPL-2.0
10 #include <bios_emul.h>
15 #include <asm/intel_regs.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/iomap.h>
20 #include <asm/arch/pch.h>
23 struct broadwell_igd_priv
{
27 struct broadwell_igd_plat
{
32 int power_backlight_on_delay
;
34 int power_backlight_off_delay
;
35 int power_cycle_delay
;
39 int pre_graphics_delay
;
43 #define GT_CDCLK_337 0
44 #define GT_CDCLK_450 1
45 #define GT_CDCLK_540 2
46 #define GT_CDCLK_675 3
48 u32
board_map_oprom_vendev(u32 vendev
)
50 return SA_IGD_OPROM_VENDEV
;
53 static int poll32(u8
*addr
, uint mask
, uint value
)
58 debug("%s: addr %p = %x\n", __func__
, addr
, readl(addr
));
59 while ((readl(addr
) & mask
) != value
) {
60 if (get_timer(start
) > GT_RETRY
) {
61 debug("poll32: timeout: %x\n", readl(addr
));
69 static int haswell_early_init(struct udevice
*dev
)
71 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
72 u8
*regs
= priv
->regs
;
75 /* Enable Force Wake */
76 writel(0x00000020, regs
+ 0xa180);
77 writel(0x00010001, regs
+ 0xa188);
78 ret
= poll32(regs
+ 0x130044, 1, 1);
83 setbits_le32(regs
+ 0xa248, 0x00000016);
85 /* GFXPAUSE settings */
86 writel(0x00070020, regs
+ 0xa000);
89 clrsetbits_le32(regs
+ 0xa180, ~0xff3fffff, 0x15000000);
91 /* Enable DOP Clock Gating */
92 writel(0x000003fd, regs
+ 0x9424);
94 /* Enable Unit Level Clock Gating */
95 writel(0x00000080, regs
+ 0x9400);
96 writel(0x40401000, regs
+ 0x9404);
97 writel(0x00000000, regs
+ 0x9408);
98 writel(0x02000001, regs
+ 0x940c);
104 /* Wake Rate Limits */
105 setbits_le32(regs
+ 0xa090, 0x00000000);
106 setbits_le32(regs
+ 0xa098, 0x03e80000);
107 setbits_le32(regs
+ 0xa09c, 0x00280000);
108 setbits_le32(regs
+ 0xa0a8, 0x0001e848);
109 setbits_le32(regs
+ 0xa0ac, 0x00000019);
111 /* Render/Video/Blitter Idle Max Count */
112 writel(0x0000000a, regs
+ 0x02054);
113 writel(0x0000000a, regs
+ 0x12054);
114 writel(0x0000000a, regs
+ 0x22054);
115 writel(0x0000000a, regs
+ 0x1a054);
117 /* RC Sleep / RCx Thresholds */
118 setbits_le32(regs
+ 0xa0b0, 0x00000000);
119 setbits_le32(regs
+ 0xa0b4, 0x000003e8);
120 setbits_le32(regs
+ 0xa0b8, 0x0000c350);
123 setbits_le32(regs
+ 0xa010, 0x000f4240);
124 setbits_le32(regs
+ 0xa014, 0x12060000);
125 setbits_le32(regs
+ 0xa02c, 0x0000e808);
126 setbits_le32(regs
+ 0xa030, 0x0003bd08);
127 setbits_le32(regs
+ 0xa068, 0x000101d0);
128 setbits_le32(regs
+ 0xa06c, 0x00055730);
129 setbits_le32(regs
+ 0xa070, 0x0000000a);
132 writel(0x00000b92, regs
+ 0xa024);
135 writel(0x88040000, regs
+ 0xa090);
137 /* Video Frequency Request */
138 writel(0x08000000, regs
+ 0xa00c);
141 ret
= poll32(regs
+ 0x138124, (1 << 31), 0);
144 writel(0, regs
+ 0x138128);
145 writel(0x80000004, regs
+ 0x138124);
146 ret
= poll32(regs
+ 0x138124, (1 << 31), 0);
150 /* Enable PM Interrupts */
151 writel(0x03000076, regs
+ 0x4402c);
153 /* Enable RC6 in idle */
154 writel(0x00040000, regs
+ 0xa094);
158 debug("%s: ret=%d\n", __func__
, ret
);
162 static int haswell_late_init(struct udevice
*dev
)
164 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
165 u8
*regs
= priv
->regs
;
169 setbits_le32(regs
+ 0x0a248, (1 << 31));
170 setbits_le32(regs
+ 0x0a004, (1 << 4));
171 setbits_le32(regs
+ 0x0a080, (1 << 2));
172 setbits_le32(regs
+ 0x0a180, (1 << 31));
174 /* Disable Force Wake */
175 writel(0x00010000, regs
+ 0xa188);
176 ret
= poll32(regs
+ 0x130044, 1, 0);
179 writel(0x00000001, regs
+ 0xa188);
181 /* Enable power well for DP and Audio */
182 setbits_le32(regs
+ 0x45400, (1 << 31));
183 ret
= poll32(regs
+ 0x45400, 1 << 30, 1 << 30);
189 debug("%s: ret=%d\n", __func__
, ret
);
193 static int broadwell_early_init(struct udevice
*dev
)
195 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
196 u8
*regs
= priv
->regs
;
199 /* Enable Force Wake */
200 writel(0x00010001, regs
+ 0xa188);
201 ret
= poll32(regs
+ 0x130044, 1, 1);
205 /* Enable push bus metric control and shift */
206 writel(0x00000004, regs
+ 0xa248);
207 writel(0x000000ff, regs
+ 0xa250);
208 writel(0x00000010, regs
+ 0xa25c);
210 /* GFXPAUSE settings (set based on stepping) */
213 writel(0x45200000, regs
+ 0xa180);
215 /* Enable DOP Clock Gating */
216 writel(0x000000fd, regs
+ 0x9424);
218 /* Enable Unit Level Clock Gating */
219 writel(0x00000000, regs
+ 0x9400);
220 writel(0x40401000, regs
+ 0x9404);
221 writel(0x00000000, regs
+ 0x9408);
222 writel(0x02000001, regs
+ 0x940c);
223 writel(0x0000000a, regs
+ 0x1a054);
225 /* Video Frequency Request */
226 writel(0x08000000, regs
+ 0xa00c);
228 writel(0x00000009, regs
+ 0x138158);
229 writel(0x0000000d, regs
+ 0x13815c);
235 /* Wake Rate Limits */
236 clrsetbits_le32(regs
+ 0x0a090, ~0, 0);
237 setbits_le32(regs
+ 0x0a098, 0x03e80000);
238 setbits_le32(regs
+ 0x0a09c, 0x00280000);
239 setbits_le32(regs
+ 0x0a0a8, 0x0001e848);
240 setbits_le32(regs
+ 0x0a0ac, 0x00000019);
242 /* Render/Video/Blitter Idle Max Count */
243 writel(0x0000000a, regs
+ 0x02054);
244 writel(0x0000000a, regs
+ 0x12054);
245 writel(0x0000000a, regs
+ 0x22054);
247 /* RC Sleep / RCx Thresholds */
248 setbits_le32(regs
+ 0x0a0b0, 0x00000000);
249 setbits_le32(regs
+ 0x0a0b8, 0x00000271);
252 setbits_le32(regs
+ 0x0a010, 0x000f4240);
253 setbits_le32(regs
+ 0x0a014, 0x12060000);
254 setbits_le32(regs
+ 0x0a02c, 0x0000e808);
255 setbits_le32(regs
+ 0x0a030, 0x0003bd08);
256 setbits_le32(regs
+ 0x0a068, 0x000101d0);
257 setbits_le32(regs
+ 0x0a06c, 0x00055730);
258 setbits_le32(regs
+ 0x0a070, 0x0000000a);
259 setbits_le32(regs
+ 0x0a168, 0x00000006);
262 writel(0x00000b92, regs
+ 0xa024);
265 writel(0x90040000, regs
+ 0xa090);
268 ret
= poll32(regs
+ 0x138124, (1 << 31), 0);
271 writel(0, regs
+ 0x138128);
272 writel(0x80000004, regs
+ 0x138124);
273 ret
= poll32(regs
+ 0x138124, (1 << 31), 0);
277 /* Enable PM Interrupts */
278 writel(0x03000076, regs
+ 0x4402c);
280 /* Enable RC6 in idle */
281 writel(0x00040000, regs
+ 0xa094);
285 debug("%s: ret=%d\n", __func__
, ret
);
289 static int broadwell_late_init(struct udevice
*dev
)
291 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
292 u8
*regs
= priv
->regs
;
296 setbits_le32(regs
+ 0x0a248, 1 << 31);
297 setbits_le32(regs
+ 0x0a000, 1 << 18);
298 setbits_le32(regs
+ 0x0a180, 1 << 31);
300 /* Disable Force Wake */
301 writel(0x00010000, regs
+ 0xa188);
302 ret
= poll32(regs
+ 0x130044, 1, 0);
306 /* Enable power well for DP and Audio */
307 setbits_le32(regs
+ 0x45400, 1 << 31);
308 ret
= poll32(regs
+ 0x45400, 1 << 30, 1 << 30);
314 debug("%s: ret=%d\n", __func__
, ret
);
319 static unsigned long gtt_read(struct broadwell_igd_priv
*priv
,
322 return readl(priv
->regs
+ reg
);
325 static void gtt_write(struct broadwell_igd_priv
*priv
, unsigned long reg
,
328 writel(data
, priv
->regs
+ reg
);
331 static inline void gtt_clrsetbits(struct broadwell_igd_priv
*priv
, u32 reg
,
334 clrsetbits_le32(priv
->regs
+ reg
, bic
, or);
337 static int gtt_poll(struct broadwell_igd_priv
*priv
, u32 reg
, u32 mask
,
340 unsigned try = GT_RETRY
;
344 data
= gtt_read(priv
, reg
);
345 if ((data
& mask
) == value
)
350 debug("GT init timeout\n");
354 static void igd_setup_panel(struct udevice
*dev
)
356 struct broadwell_igd_plat
*plat
= dev_get_platdata(dev
);
357 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
360 /* Setup Digital Port Hotplug */
361 reg32
= (plat
->dp_hotplug
[0] & 0x7) << 2;
362 reg32
|= (plat
->dp_hotplug
[1] & 0x7) << 10;
363 reg32
|= (plat
->dp_hotplug
[2] & 0x7) << 18;
364 gtt_write(priv
, PCH_PORT_HOTPLUG
, reg32
);
366 /* Setup Panel Power On Delays */
367 reg32
= (plat
->port_select
& 0x3) << 30;
368 reg32
|= (plat
->power_up_delay
& 0x1fff) << 16;
369 reg32
|= (plat
->power_backlight_on_delay
& 0x1fff);
370 gtt_write(priv
, PCH_PP_ON_DELAYS
, reg32
);
372 /* Setup Panel Power Off Delays */
373 reg32
= (plat
->power_down_delay
& 0x1fff) << 16;
374 reg32
|= (plat
->power_backlight_off_delay
& 0x1fff);
375 gtt_write(priv
, PCH_PP_OFF_DELAYS
, reg32
);
377 /* Setup Panel Power Cycle Delay */
378 if (plat
->power_cycle_delay
) {
379 reg32
= gtt_read(priv
, PCH_PP_DIVISOR
);
381 reg32
|= plat
->power_cycle_delay
& 0xff;
382 gtt_write(priv
, PCH_PP_DIVISOR
, reg32
);
385 /* Enable Backlight if needed */
386 if (plat
->cpu_backlight
) {
387 gtt_write(priv
, BLC_PWM_CPU_CTL2
, BLC_PWM2_ENABLE
);
388 gtt_write(priv
, BLC_PWM_CPU_CTL
, plat
->cpu_backlight
);
390 if (plat
->pch_backlight
) {
391 gtt_write(priv
, BLC_PWM_PCH_CTL1
, BLM_PCH_PWM_ENABLE
);
392 gtt_write(priv
, BLC_PWM_PCH_CTL2
, plat
->pch_backlight
);
396 static int igd_cdclk_init_haswell(struct udevice
*dev
)
398 struct broadwell_igd_plat
*plat
= dev_get_platdata(dev
);
399 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
400 int cdclk
= plat
->cdclk
;
406 dm_pci_read_config16(dev
, PCI_DEVICE_ID
, &devid
);
408 /* Check for ULX GT1 or GT2 */
409 if (devid
== 0x0a0e || devid
== 0x0a1e)
412 /* 675MHz is not supported on haswell */
413 if (cdclk
== GT_CDCLK_675
)
414 cdclk
= GT_CDCLK_337
;
416 /* If CD clock is fixed or ULT then set to 450MHz */
417 if ((gtt_read(priv
, 0x42014) & 0x1000000) || cpu_is_ult())
418 cdclk
= GT_CDCLK_450
;
420 /* 540MHz is not supported on ULX */
421 if (gpu_is_ulx
&& cdclk
== GT_CDCLK_540
)
422 cdclk
= GT_CDCLK_337
;
424 /* 337.5MHz is not supported on non-ULT/ULX */
425 if (!gpu_is_ulx
&& !cpu_is_ult() && cdclk
== GT_CDCLK_337
)
426 cdclk
= GT_CDCLK_450
;
428 /* Set variables based on CD Clock setting */
447 /* Set LPCLL_CTL CD Clock Frequency Select */
448 gtt_clrsetbits(priv
, 0x130040, ~0xf3ffffff, lpcll
);
450 /* ULX: Inform power controller of selected frequency */
452 if (cdclk
== GT_CDCLK_450
)
453 gtt_write(priv
, 0x138128, 0x00000000); /* 450MHz */
455 gtt_write(priv
, 0x138128, 0x00000001); /* 337.5MHz */
456 gtt_write(priv
, 0x13812c, 0x00000000);
457 gtt_write(priv
, 0x138124, 0x80000017);
460 /* Set CPU DP AUX 2X bit clock dividers */
461 gtt_clrsetbits(priv
, 0x64010, ~0xfffff800, dpdiv
);
462 gtt_clrsetbits(priv
, 0x64810, ~0xfffff800, dpdiv
);
466 debug("%s: ret=%d\n", __func__
, ret
);
470 static int igd_cdclk_init_broadwell(struct udevice
*dev
)
472 struct broadwell_igd_plat
*plat
= dev_get_platdata(dev
);
473 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
474 int cdclk
= plat
->cdclk
;
475 u32 dpdiv
, lpcll
, pwctl
, cdset
;
478 /* Inform power controller of upcoming frequency change */
479 gtt_write(priv
, 0x138128, 0);
480 gtt_write(priv
, 0x13812c, 0);
481 gtt_write(priv
, 0x138124, 0x80000018);
483 /* Poll GT driver mailbox for run/busy clear */
484 if (gtt_poll(priv
, 0x138124, 1 << 31, 0 << 31))
485 cdclk
= GT_CDCLK_450
;
487 if (gtt_read(priv
, 0x42014) & 0x1000000) {
488 /* If CD clock is fixed then set to 450MHz */
489 cdclk
= GT_CDCLK_450
;
491 /* Program CD clock to highest supported freq */
493 cdclk
= GT_CDCLK_540
;
495 cdclk
= GT_CDCLK_675
;
498 /* CD clock frequency 675MHz not supported on ULT */
499 if (cpu_is_ult() && cdclk
== GT_CDCLK_675
)
500 cdclk
= GT_CDCLK_540
;
502 /* Set variables based on CD Clock setting */
524 lpcll
= (1 << 26) | (1 << 27);
532 debug("%s: frequency = %d\n", __func__
, cdclk
);
534 /* Set LPCLL_CTL CD Clock Frequency Select */
535 gtt_clrsetbits(priv
, 0x130040, ~0xf3ffffff, lpcll
);
537 /* Inform power controller of selected frequency */
538 gtt_write(priv
, 0x138128, pwctl
);
539 gtt_write(priv
, 0x13812c, 0);
540 gtt_write(priv
, 0x138124, 0x80000017);
542 /* Program CD Clock Frequency */
543 gtt_clrsetbits(priv
, 0x46200, ~0xfffffc00, cdset
);
545 /* Set CPU DP AUX 2X bit clock dividers */
546 gtt_clrsetbits(priv
, 0x64010, ~0xfffff800, dpdiv
);
547 gtt_clrsetbits(priv
, 0x64810, ~0xfffff800, dpdiv
);
551 debug("%s: ret=%d\n", __func__
, ret
);
555 u8
systemagent_revision(struct udevice
*bus
)
559 pci_bus_read_config(bus
, PCI_BDF(0, 0, 0), PCI_REVISION_ID
, &val
,
565 static int igd_pre_init(struct udevice
*dev
, bool is_broadwell
)
567 struct broadwell_igd_plat
*plat
= dev_get_platdata(dev
);
568 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
572 mdelay(plat
->pre_graphics_delay
);
574 /* Early init steps */
576 ret
= broadwell_early_init(dev
);
580 /* Set GFXPAUSE based on stepping */
581 if (cpu_get_stepping() <= (CPUID_BROADWELL_E0
& 0xf) &&
582 systemagent_revision(pci_get_controller(dev
)) <= 9) {
583 gtt_write(priv
, 0xa000, 0x300ff);
585 gtt_write(priv
, 0xa000, 0x30020);
588 ret
= haswell_early_init(dev
);
593 /* Set RP1 graphics frequency */
594 rp1_gfx_freq
= (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
595 gtt_write(priv
, 0xa008, rp1_gfx_freq
<< 24);
597 /* Post VBIOS panel setup */
598 igd_setup_panel(dev
);
602 debug("%s: ret=%d\n", __func__
, ret
);
606 static int igd_post_init(struct udevice
*dev
, bool is_broadwell
)
610 /* Late init steps */
612 ret
= igd_cdclk_init_broadwell(dev
);
615 ret
= broadwell_late_init(dev
);
619 igd_cdclk_init_haswell(dev
);
620 ret
= haswell_late_init(dev
);
628 static int broadwell_igd_int15_handler(void)
632 debug("%s: INT15 function %04x!\n", __func__
, M
.x86
.R_AX
);
634 switch (M
.x86
.R_AX
) {
637 * Boot Display Device Hook:
648 M
.x86
.R_CX
= 0x0000; /* Use video bios default */
652 debug("Unknown INT15 function %04x!\n", M
.x86
.R_AX
);
659 static int broadwell_igd_probe(struct udevice
*dev
)
661 struct video_uc_platdata
*plat
= dev_get_uclass_platdata(dev
);
662 struct video_priv
*uc_priv
= dev_get_uclass_priv(dev
);
666 if (!ll_boot_init()) {
668 * If we are running from EFI or coreboot, this driver can't
671 printf("Not available (previous bootloader prevents it)\n");
674 is_broadwell
= cpu_get_family_model() == BROADWELL_FAMILY_ULT
;
675 bootstage_start(BOOTSTAGE_ID_ACCUM_LCD
, "vesa display");
676 debug("%s: is_broadwell=%d\n", __func__
, is_broadwell
);
677 ret
= igd_pre_init(dev
, is_broadwell
);
679 ret
= vbe_setup_video(dev
, broadwell_igd_int15_handler
);
681 debug("failed to run video BIOS: %d\n", ret
);
684 ret
= igd_post_init(dev
, is_broadwell
);
685 bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD
);
689 /* Use write-combining for the graphics memory, 256MB */
690 ret
= mtrr_add_request(MTRR_TYPE_WRCOMB
, plat
->base
, 256 << 20);
692 ret
= mtrr_commit(true);
693 if (ret
&& ret
!= -ENOSYS
) {
694 printf("Failed to add MTRR: Display will be slow (err %d)\n",
698 debug("fb=%lx, size %x, display size=%d %d %d\n", plat
->base
,
699 plat
->size
, uc_priv
->xsize
, uc_priv
->ysize
, uc_priv
->bpix
);
704 static int broadwell_igd_ofdata_to_platdata(struct udevice
*dev
)
706 struct broadwell_igd_plat
*plat
= dev_get_platdata(dev
);
707 struct broadwell_igd_priv
*priv
= dev_get_priv(dev
);
708 int node
= dev_of_offset(dev
);
709 const void *blob
= gd
->fdt_blob
;
711 if (fdtdec_get_int_array(blob
, node
, "intel,dp-hotplug",
713 ARRAY_SIZE(plat
->dp_hotplug
)))
715 plat
->port_select
= fdtdec_get_int(blob
, node
, "intel,port-select", 0);
716 plat
->power_cycle_delay
= fdtdec_get_int(blob
, node
,
717 "intel,power-cycle-delay", 0);
718 plat
->power_up_delay
= fdtdec_get_int(blob
, node
,
719 "intel,power-up-delay", 0);
720 plat
->power_down_delay
= fdtdec_get_int(blob
, node
,
721 "intel,power-down-delay", 0);
722 plat
->power_backlight_on_delay
= fdtdec_get_int(blob
, node
,
723 "intel,power-backlight-on-delay", 0);
724 plat
->power_backlight_off_delay
= fdtdec_get_int(blob
, node
,
725 "intel,power-backlight-off-delay", 0);
726 plat
->cpu_backlight
= fdtdec_get_int(blob
, node
,
727 "intel,cpu-backlight", 0);
728 plat
->pch_backlight
= fdtdec_get_int(blob
, node
,
729 "intel,pch-backlight", 0);
730 plat
->pre_graphics_delay
= fdtdec_get_int(blob
, node
,
731 "intel,pre-graphics-delay", 0);
732 priv
->regs
= (u8
*)dm_pci_read_bar32(dev
, 0);
733 debug("%s: regs at %p\n", __func__
, priv
->regs
);
734 debug("dp_hotplug %d %d %d\n", plat
->dp_hotplug
[0], plat
->dp_hotplug
[1],
735 plat
->dp_hotplug
[2]);
736 debug("port_select = %d\n", plat
->port_select
);
737 debug("power_up_delay = %d\n", plat
->power_up_delay
);
738 debug("power_backlight_on_delay = %d\n",
739 plat
->power_backlight_on_delay
);
740 debug("power_down_delay = %d\n", plat
->power_down_delay
);
741 debug("power_backlight_off_delay = %d\n",
742 plat
->power_backlight_off_delay
);
743 debug("power_cycle_delay = %d\n", plat
->power_cycle_delay
);
744 debug("cpu_backlight = %x\n", plat
->cpu_backlight
);
745 debug("pch_backlight = %x\n", plat
->pch_backlight
);
746 debug("cdclk = %d\n", plat
->cdclk
);
747 debug("pre_graphics_delay = %d\n", plat
->pre_graphics_delay
);
752 static const struct video_ops broadwell_igd_ops
= {
755 static const struct udevice_id broadwell_igd_ids
[] = {
756 { .compatible
= "intel,broadwell-igd" },
760 U_BOOT_DRIVER(broadwell_igd
) = {
761 .name
= "broadwell_igd",
763 .of_match
= broadwell_igd_ids
,
764 .ops
= &broadwell_igd_ops
,
765 .ofdata_to_platdata
= broadwell_igd_ofdata_to_platdata
,
766 .probe
= broadwell_igd_probe
,
767 .priv_auto_alloc_size
= sizeof(struct broadwell_igd_priv
),
768 .platdata_auto_alloc_size
= sizeof(struct broadwell_igd_plat
),