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Convert CONFIG_SYS_CONSOLE_BG_COL et al to Kconfig
[people/ms/u-boot.git] / drivers / video / ct69000.c
1 /* ported from ctfb.c (linux kernel):
2 * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
3 *
4 * Ported to U-Boot:
5 * (C) Copyright 2002 Denis Peter, MPL AG Switzerland
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11
12 #ifdef CONFIG_VIDEO
13
14 #include <pci.h>
15 #include <video_fb.h>
16 #include "videomodes.h"
17
18 /* debug */
19 #undef VGA_DEBUG
20 #undef VGA_DUMP_REG
21 #ifdef VGA_DEBUG
22 #undef _DEBUG
23 #define _DEBUG 1
24 #else
25 #undef _DEBUG
26 #define _DEBUG 0
27 #endif
28
29 /* Macros */
30 #ifndef min
31 #define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b )
32 #endif
33 #ifndef max
34 #define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b )
35 #endif
36 #ifdef minmax
37 #error "term minmax already used."
38 #endif
39 #define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) )
40 #define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) )
41
42 /* CT Register Offsets */
43 #define CT_AR_O 0x3c0 /* Index and Data write port of the attribute Registers */
44 #define CT_GR_O 0x3ce /* Index port of the Graphic Controller Registers */
45 #define CT_SR_O 0x3c4 /* Index port of the Sequencer Controller */
46 #define CT_CR_O 0x3d4 /* Index port of the CRT Controller */
47 #define CT_XR_O 0x3d6 /* Extended Register index */
48 #define CT_MSR_W_O 0x3c2 /* Misc. Output Register (write only) */
49 #define CT_LUT_MASK_O 0x3c6 /* Color Palette Mask */
50 #define CT_LUT_START_O 0x3c8 /* Color Palette Write Mode Index */
51 #define CT_LUT_RGB_O 0x3c9 /* Color Palette Data Port */
52 #define CT_STATUS_REG0_O 0x3c2 /* Status Register 0 (read only) */
53 #define CT_STATUS_REG1_O 0x3da /* Input Status Register 1 (read only) */
54
55 #define CT_FP_O 0x3d0 /* Index port of the Flat panel Registers */
56 #define CT_MR_O 0x3d2 /* Index Port of the Multimedia Extension */
57
58 /* defines for the memory mapped registers */
59 #define BR00_o 0x400000 /* Source and Destination Span Register */
60 #define BR01_o 0x400004 /* Pattern/Source Expansion Background Color & Transparency Key Register */
61 #define BR02_o 0x400008 /* Pattern/Source Expansion Foreground Color Register */
62 #define BR03_o 0x40000C /* Monochrome Source Control Register */
63 #define BR04_o 0x400010 /* BitBLT Control Register */
64 #define BR05_o 0x400014 /* Pattern Address Registe */
65 #define BR06_o 0x400018 /* Source Address Register */
66 #define BR07_o 0x40001C /* Destination Address Register */
67 #define BR08_o 0x400020 /* Destination Width & Height Register */
68 #define BR09_o 0x400024 /* Source Expansion Background Color & Transparency Key Register */
69 #define BR0A_o 0x400028 /* Source Expansion Foreground Color Register */
70
71 #define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */
72 #define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */
73 #define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */
74 #define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */
75
76 /* Some Mode definitions */
77 #define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
78 #define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
79 #define FB_SYNC_EXT 4 /* external sync */
80 #define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
81 #define FB_SYNC_BROADCAST 16 /* broadcast video timings */
82 /* vtotal = 144d/288n/576i => PAL */
83 /* vtotal = 121d/242n/484i => NTSC */
84 #define FB_SYNC_ON_GREEN 32 /* sync on green */
85
86 #define FB_VMODE_NONINTERLACED 0 /* non interlaced */
87 #define FB_VMODE_INTERLACED 1 /* interlaced */
88 #define FB_VMODE_DOUBLE 2 /* double scan */
89 #define FB_VMODE_MASK 255
90
91 #define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
92 #define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
93 #define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
94
95 #define text 0
96 #define fntwidth 8
97
98 /* table for VGA Initialization */
99 typedef struct {
100 const unsigned char reg;
101 const unsigned char val;
102 } CT_CFG_TABLE;
103
104 /* this table provides some basic initialisations such as Memory Clock etc */
105 static CT_CFG_TABLE xreg[] = {
106 {0x09, 0x01}, /* CRT Controller Extensions Enable */
107 {0x0A, 0x02}, /* Frame Buffer Mapping */
108 {0x0B, 0x01}, /* PCI Write Burst support */
109 {0x20, 0x00}, /* BitBLT Configuration */
110 {0x40, 0x03}, /* Memory Access Control */
111 {0x60, 0x00}, /* Video Pin Control */
112 {0x61, 0x00}, /* DPMS Synch control */
113 {0x62, 0x00}, /* GPIO Pin Control */
114 {0x63, 0xBD}, /* GPIO Pin Data */
115 {0x67, 0x00}, /* Pin Tri-State */
116 {0x80, 0x80}, /* Pixel Pipeline Config 0 register */
117 {0xA0, 0x00}, /* Cursor 1 Control Reg */
118 {0xA1, 0x00}, /* Cursor 1 Vertical Extension Reg */
119 {0xA2, 0x00}, /* Cursor 1 Base Address Low */
120 {0xA3, 0x00}, /* Cursor 1 Base Address High */
121 {0xA4, 0x00}, /* Cursor 1 X-Position Low */
122 {0xA5, 0x00}, /* Cursor 1 X-Position High */
123 {0xA6, 0x00}, /* Cursor 1 Y-Position Low */
124 {0xA7, 0x00}, /* Cursor 1 Y-Position High */
125 {0xA8, 0x00}, /* Cursor 2 Control Reg */
126 {0xA9, 0x00}, /* Cursor 2 Vertical Extension Reg */
127 {0xAA, 0x00}, /* Cursor 2 Base Address Low */
128 {0xAB, 0x00}, /* Cursor 2 Base Address High */
129 {0xAC, 0x00}, /* Cursor 2 X-Position Low */
130 {0xAD, 0x00}, /* Cursor 2 X-Position High */
131 {0xAE, 0x00}, /* Cursor 2 Y-Position Low */
132 {0xAF, 0x00}, /* Cursor 2 Y-Position High */
133 {0xC0, 0x7D}, /* Dot Clock 0 VCO M-Divisor */
134 {0xC1, 0x07}, /* Dot Clock 0 VCO N-Divisor */
135 {0xC3, 0x34}, /* Dot Clock 0 Divisor select */
136 {0xC4, 0x55}, /* Dot Clock 1 VCO M-Divisor */
137 {0xC5, 0x09}, /* Dot Clock 1 VCO N-Divisor */
138 {0xC7, 0x24}, /* Dot Clock 1 Divisor select */
139 {0xC8, 0x7D}, /* Dot Clock 2 VCO M-Divisor */
140 {0xC9, 0x07}, /* Dot Clock 2 VCO N-Divisor */
141 {0xCB, 0x34}, /* Dot Clock 2 Divisor select */
142 {0xCC, 0x38}, /* Memory Clock 0 VCO M-Divisor */
143 {0xCD, 0x03}, /* Memory Clock 0 VCO N-Divisor */
144 {0xCE, 0x90}, /* Memory Clock 0 Divisor select */
145 {0xCF, 0x06}, /* Clock Config */
146 {0xD0, 0x0F}, /* Power Down */
147 {0xD1, 0x01}, /* Power Down BitBLT */
148 {0xFF, 0xFF} /* end of table */
149 };
150 /* Clock Config:
151 * =============
152 *
153 * PD Registers:
154 * -------------
155 * Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor.
156 * They are encoded as follows:
157 *
158 * +---+--------------+
159 * | 2 | Loop Divisor |
160 * +---+--------------+
161 * | 1 | 1 |
162 * +---+--------------+
163 * | 0 | 4 |
164 * +---+--------------+
165 * Note: The Memory Clock does not have a Loop Divisor.
166 * +---+---+---+--------------+
167 * | 6 | 5 | 4 | Post Divisor |
168 * +---+---+---+--------------+
169 * | 0 | 0 | 0 | 1 |
170 * +---+---+---+--------------+
171 * | 0 | 0 | 1 | 2 |
172 * +---+---+---+--------------+
173 * | 0 | 1 | 0 | 4 |
174 * +---+---+---+--------------+
175 * | 0 | 1 | 1 | 8 |
176 * +---+---+---+--------------+
177 * | 1 | 0 | 0 | 16 |
178 * +---+---+---+--------------+
179 * | 1 | 0 | 1 | 32 |
180 * +---+---+---+--------------+
181 * | 1 | 1 | X | reserved |
182 * +---+---+---+--------------+
183 *
184 * All other bits are reserved in these registers.
185 *
186 * Clock VCO M Registers:
187 * ----------------------
188 * These Registers contain the M Value -2.
189 *
190 * Clock VCO N Registers:
191 * ----------------------
192 * These Registers contain the N Value -2.
193 *
194 * Formulas:
195 * ---------
196 * Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz
197 * Fout = Fvco / Post Divisor
198 *
199 * Dot Clk0 (default 25MHz):
200 * -------------------------
201 * Fvco = 14.318 * 127 / 9 = 202.045MHz
202 * Fout = 202.045MHz / 8 = 25.25MHz
203 * Post Divisor = 8
204 * Loop Divisor = 1
205 * XRC0 = (M - 2) = 125 = 0x7D
206 * XRC1 = (N - 2) = 7 = 0x07
207 * XRC3 = 0x34
208 *
209 * Dot Clk1 (default 28MHz):
210 * -------------------------
211 * Fvco = 14.318 * 87 / 11 = 113.24MHz
212 * Fout = 113.24MHz / 4 = 28.31MHz
213 * Post Divisor = 4
214 * Loop Divisor = 1
215 * XRC4 = (M - 2) = 85 = 0x55
216 * XRC5 = (N - 2) = 9 = 0x09
217 * XRC7 = 0x24
218 *
219 * Dot Clk2 (variable for extended modes set to 25MHz):
220 * ----------------------------------------------------
221 * Fvco = 14.318 * 127 / 9 = 202.045MHz
222 * Fout = 202.045MHz / 8 = 25.25MHz
223 * Post Divisor = 8
224 * Loop Divisor = 1
225 * XRC8 = (M - 2) = 125 = 0x7D
226 * XRC9 = (N - 2) = 7 = 0x07
227 * XRCB = 0x34
228 *
229 * Memory Clk for most modes >50MHz:
230 * ----------------------------------
231 * Fvco = 14.318 * 58 / 5 = 166MHz
232 * Fout = 166MHz / 2 = 83MHz
233 * Post Divisor = 2
234 * XRCC = (M - 2) = 57 = 0x38
235 * XRCD = (N - 2) = 3 = 0x03
236 * XRCE = 0x90
237 *
238 * Note Bit7 enables the clock source from the VCO
239 *
240 */
241
242 /*******************************************************************
243 * Chips struct
244 *******************************************************************/
245 struct ctfb_chips_properties {
246 int device_id; /* PCI Device ID */
247 unsigned long max_mem; /* memory for frame buffer */
248 int vld_set; /* value of VLD if bit2 in clock control is set */
249 int vld_not_set; /* value of VLD if bit2 in clock control is set */
250 int mn_diff; /* difference between M/N Value + mn_diff = M/N Register */
251 int mn_min; /* min value of M/N Value */
252 int mn_max; /* max value of M/N Value */
253 int vco_min; /* VCO Min in MHz */
254 int vco_max; /* VCO Max in MHz */
255 };
256
257 static const struct ctfb_chips_properties chips[] = {
258 {PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
259 {PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */
260 {0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */
261 };
262
263 /*
264 * The Graphic Device
265 */
266 GraphicDevice ctfb;
267
268 /*******************************************************************************
269 *
270 * Low Level Routines
271 */
272
273 /*******************************************************************************
274 *
275 * Read CT ISA register
276 */
277 #ifdef VGA_DEBUG
278 static unsigned char
279 ctRead (unsigned short index)
280 {
281 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
282 if (index == CT_AR_O)
283 /* synch the Flip Flop */
284 in8 (pGD->isaBase + CT_STATUS_REG1_O);
285
286 return (in8 (pGD->isaBase + index));
287 }
288 #endif
289 /*******************************************************************************
290 *
291 * Write CT ISA register
292 */
293 static void
294 ctWrite (unsigned short index, unsigned char val)
295 {
296 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
297
298 out8 ((pGD->isaBase + index), val);
299 }
300
301 /*******************************************************************************
302 *
303 * Read CT ISA register indexed
304 */
305 static unsigned char
306 ctRead_i (unsigned short index, char reg)
307 {
308 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
309 if (index == CT_AR_O)
310 /* synch the Flip Flop */
311 in8 (pGD->isaBase + CT_STATUS_REG1_O);
312 out8 ((pGD->isaBase + index), reg);
313 return (in8 (pGD->isaBase + index + 1));
314 }
315
316 /*******************************************************************************
317 *
318 * Write CT ISA register indexed
319 */
320 static void
321 ctWrite_i (unsigned short index, char reg, char val)
322 {
323 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
324 if (index == CT_AR_O) {
325 /* synch the Flip Flop */
326 in8 (pGD->isaBase + CT_STATUS_REG1_O);
327 out8 ((pGD->isaBase + index), reg);
328 out8 ((pGD->isaBase + index), val);
329 } else {
330 out8 ((pGD->isaBase + index), reg);
331 out8 ((pGD->isaBase + index + 1), val);
332 }
333 }
334
335 /*******************************************************************************
336 *
337 * Write a table of CT ISA register
338 */
339 static void
340 ctLoadRegs (unsigned short index, CT_CFG_TABLE * regTab)
341 {
342 while (regTab->reg != 0xFF) {
343 ctWrite_i (index, regTab->reg, regTab->val);
344 regTab++;
345 }
346 }
347
348 /*****************************************************************************/
349 static void
350 SetArRegs (void)
351 {
352 int i, tmp;
353
354 for (i = 0; i < 0x10; i++)
355 ctWrite_i (CT_AR_O, i, i);
356 if (text)
357 tmp = 0x04;
358 else
359 tmp = 0x41;
360
361 ctWrite_i (CT_AR_O, 0x10, tmp); /* Mode Control Register */
362 ctWrite_i (CT_AR_O, 0x11, 0x00); /* Overscan Color Register */
363 ctWrite_i (CT_AR_O, 0x12, 0x0f); /* Memory Plane Enable Register */
364 if (fntwidth == 9)
365 tmp = 0x08;
366 else
367 tmp = 0x00;
368 ctWrite_i (CT_AR_O, 0x13, tmp); /* Horizontal Pixel Panning */
369 ctWrite_i (CT_AR_O, 0x14, 0x00); /* Color Select Register */
370 ctWrite (CT_AR_O, 0x20); /* enable video */
371 }
372
373 /*****************************************************************************/
374 static void
375 SetGrRegs (void)
376 { /* Set Graphics Mode */
377 int i;
378
379 for (i = 0; i < 0x05; i++)
380 ctWrite_i (CT_GR_O, i, 0);
381 if (text) {
382 ctWrite_i (CT_GR_O, 0x05, 0x10);
383 ctWrite_i (CT_GR_O, 0x06, 0x02);
384 } else {
385 ctWrite_i (CT_GR_O, 0x05, 0x40);
386 ctWrite_i (CT_GR_O, 0x06, 0x05);
387 }
388 ctWrite_i (CT_GR_O, 0x07, 0x0f);
389 ctWrite_i (CT_GR_O, 0x08, 0xff);
390 }
391
392 /*****************************************************************************/
393 static void
394 SetSrRegs (void)
395 {
396 int tmp = 0;
397
398 ctWrite_i (CT_SR_O, 0x00, 0x00); /* reset */
399 /*rr( sr, 0x01, tmp );
400 if( fntwidth == 8 ) tmp |= 0x01; else tmp &= ~0x01;
401 wr( sr, 0x01, tmp ); */
402 if (fntwidth == 8)
403 ctWrite_i (CT_SR_O, 0x01, 0x01); /* Clocking Mode Register */
404 else
405 ctWrite_i (CT_SR_O, 0x01, 0x00); /* Clocking Mode Register */
406 ctWrite_i (CT_SR_O, 0x02, 0x0f); /* Enable CPU wr access to given memory plane */
407 ctWrite_i (CT_SR_O, 0x03, 0x00); /* Character Map Select Register */
408 if (text)
409 tmp = 0x02;
410 else
411 tmp = 0x0e;
412 ctWrite_i (CT_SR_O, 0x04, tmp); /* Enable CPU accesses to the rest of the 256KB
413 total VGA memory beyond the first 64KB and set
414 fb mapping mode. */
415 ctWrite_i (CT_SR_O, 0x00, 0x03); /* enable */
416 }
417
418 /*****************************************************************************/
419 static void
420 SetBitsPerPixelIntoXrRegs (int bpp)
421 {
422 unsigned int n = (bpp >> 3), tmp; /* only for 15, 8, 16, 24 bpp */
423 static char md[4] = { 0x04, 0x02, 0x05, 0x06 }; /* DisplayColorMode */
424 static char off[4] = { ~0x20, ~0x30, ~0x20, ~0x10 }; /* mask */
425 static char on[4] = { 0x10, 0x00, 0x10, 0x20 }; /* mask */
426 if (bpp == 15)
427 n = 0;
428 tmp = ctRead_i (CT_XR_O, 0x20);
429 tmp &= off[n];
430 tmp |= on[n];
431 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
432 ctWrite_i (CT_XR_O, 0x81, md[n]);
433 }
434
435 /*****************************************************************************/
436 static void
437 SetCrRegs (struct ctfb_res_modes *var, int bits_per_pixel)
438 { /* he -le- ht|0 hd -ri- hs -h- he */
439 unsigned char cr[0x7a];
440 int i, tmp;
441 unsigned int hd, hs, he, ht, hbe; /* Horizontal. */
442 unsigned int vd, vs, ve, vt; /* vertical */
443 unsigned int bpp, wd, dblscan, interlaced, bcast, CrtHalfLine;
444 unsigned int CompSyncCharClkDelay, CompSyncPixelClkDelay;
445 unsigned int NTSC_PAL_HorizontalPulseWidth, BlDelayCtrl;
446 unsigned int HorizontalEqualizationPulses;
447 unsigned int HorizontalSerration1Start, HorizontalSerration2Start;
448
449 const int LineCompare = 0x3ff;
450 unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */
451 unsigned int RAMDAC_BlankPedestalEnable = 0; /* 1=en-, 0=disable, see XR82 */
452
453 hd = (var->xres) / 8; /* HDisp. */
454 hs = (var->xres + var->right_margin) / 8; /* HsStrt */
455 he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */
456 ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */
457 hbe = ht - 1; /* HBlankEnable todo docu wants ht here, but it does not work */
458 /* ve -up- vt|0 vd -lo- vs -v- ve */
459 vd = var->yres; /* VDisplay */
460 vs = var->yres + var->lower_margin; /* VSyncStart */
461 ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */
462 vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */
463 bpp = bits_per_pixel;
464 dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0;
465 interlaced = var->vmode & FB_VMODE_INTERLACED;
466 bcast = var->sync & FB_SYNC_BROADCAST;
467 CrtHalfLine = bcast ? (hd >> 1) : 0;
468 BlDelayCtrl = bcast ? 1 : 0;
469 CompSyncCharClkDelay = 0; /* 2 bit */
470 CompSyncPixelClkDelay = 0; /* 3 bit */
471 if (bcast) {
472 NTSC_PAL_HorizontalPulseWidth = 7; /*( var->hsync_len >> 1 ) + 1 */
473 HorizontalEqualizationPulses = 0; /* inverse value */
474 HorizontalSerration1Start = 31; /* ( ht >> 1 ) */
475 HorizontalSerration2Start = 89; /* ( ht >> 1 ) */
476 } else {
477 NTSC_PAL_HorizontalPulseWidth = 0;
478 /* 4 bit: hsync pulse width = ( ( CR74[4:0] - CR74[5] )
479 * / 2 ) + 1 --> CR74[4:0] = 2*(hs-1) + CR74[5] */
480 HorizontalEqualizationPulses = 1; /* inverse value */
481 HorizontalSerration1Start = 0; /* ( ht >> 1 ) */
482 HorizontalSerration2Start = 0; /* ( ht >> 1 ) */
483 }
484
485 if (bpp == 15)
486 bpp = 16;
487 wd = var->xres * bpp / 64; /* double words per line */
488 if (interlaced) { /* we divide all vertical timings, exept vd */
489 vs >>= 1;
490 ve >>= 1;
491 vt >>= 1;
492 }
493 memset (cr, 0, sizeof (cr));
494 cr[0x00] = 0xff & (ht - 5);
495 cr[0x01] = hd - 1; /* soll:4f ist 59 */
496 cr[0x02] = hd;
497 cr[0x03] = (hbe & 0x1F) | 0x80; /* hd + ht - hd */
498 cr[0x04] = hs;
499 cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
500 cr[0x06] = (vt - 2) & 0xFF;
501 cr[0x30] = (vt - 2) >> 8;
502 cr[0x07] = ((vt & 0x100) >> 8)
503 | ((vd & 0x100) >> 7)
504 | ((vs & 0x100) >> 6)
505 | ((vs & 0x100) >> 5)
506 | ((LineCompare & 0x100) >> 4)
507 | ((vt & 0x200) >> 4)
508 | ((vd & 0x200) >> 3)
509 | ((vs & 0x200) >> 2);
510 cr[0x08] = 0x00;
511 cr[0x09] = (dblscan << 7)
512 | ((LineCompare & 0x200) >> 3)
513 | ((vs & 0x200) >> 4)
514 | (TextScanLines - 1);
515 cr[0x10] = vs & 0xff; /* VSyncPulseStart */
516 cr[0x32] = (vs & 0xf00) >> 8; /* VSyncPulseStart */
517 cr[0x11] = (ve & 0x0f); /* | 0x20; */
518 cr[0x12] = (vd - 1) & 0xff; /* LineCount */
519 cr[0x31] = ((vd - 1) & 0xf00) >> 8; /* LineCount */
520 cr[0x13] = wd & 0xff;
521 cr[0x41] = (wd & 0xf00) >> 8;
522 cr[0x15] = vs & 0xff;
523 cr[0x33] = (vs & 0xf00) >> 8;
524 cr[0x38] = (0x100 & (ht - 5)) >> 8;
525 cr[0x3C] = 0xc0 & hbe;
526 cr[0x16] = (vt - 1) & 0xff; /* vbe - docu wants vt here, */
527 cr[0x17] = 0xe3; /* but it does not work */
528 cr[0x18] = 0xff & LineCompare;
529 cr[0x22] = 0xff; /* todo? */
530 cr[0x70] = interlaced ? (0x80 | CrtHalfLine) : 0x00; /* check:0xa6 */
531 cr[0x71] = 0x80 | (RAMDAC_BlankPedestalEnable << 6)
532 | (BlDelayCtrl << 5)
533 | ((0x03 & CompSyncCharClkDelay) << 3)
534 | (0x07 & CompSyncPixelClkDelay); /* todo: see XR82 */
535 cr[0x72] = HorizontalSerration1Start;
536 cr[0x73] = HorizontalSerration2Start;
537 cr[0x74] = (HorizontalEqualizationPulses << 5)
538 | NTSC_PAL_HorizontalPulseWidth;
539 /* todo: ct69000 has also 0x75-79 */
540 /* now set the registers */
541 for (i = 0; i <= 0x0d; i++) { /*CR00 .. CR0D */
542 ctWrite_i (CT_CR_O, i, cr[i]);
543 }
544 for (i = 0x10; i <= 0x18; i++) { /*CR10 .. CR18 */
545 ctWrite_i (CT_CR_O, i, cr[i]);
546 }
547 i = 0x22; /*CR22 */
548 ctWrite_i (CT_CR_O, i, cr[i]);
549 for (i = 0x30; i <= 0x33; i++) { /*CR30 .. CR33 */
550 ctWrite_i (CT_CR_O, i, cr[i]);
551 }
552 i = 0x38; /*CR38 */
553 ctWrite_i (CT_CR_O, i, cr[i]);
554 i = 0x3C; /*CR3C */
555 ctWrite_i (CT_CR_O, i, cr[i]);
556 for (i = 0x40; i <= 0x41; i++) { /*CR40 .. CR41 */
557 ctWrite_i (CT_CR_O, i, cr[i]);
558 }
559 for (i = 0x70; i <= 0x74; i++) { /*CR70 .. CR74 */
560 ctWrite_i (CT_CR_O, i, cr[i]);
561 }
562 tmp = ctRead_i (CT_CR_O, 0x40);
563 tmp &= 0x0f;
564 tmp |= 0x80;
565 ctWrite_i (CT_CR_O, 0x40, tmp); /* StartAddressEnable */
566 }
567
568 /* pixelclock control */
569
570 /*****************************************************************************
571 We have a rational number p/q and need an m/n which is very close to p/q
572 but has m and n within mnmin and mnmax. We have no floating point in the
573 kernel. We can use long long without divide. And we have time to compute...
574 ******************************************************************************/
575 static unsigned int
576 FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin,
577 unsigned int mnmax, unsigned int *pm, unsigned int *pn)
578 {
579 /* this code is not for general purpose usable but good for our number ranges */
580 unsigned int n = mnmin, m = 0;
581 long long int L = 0, P = p, Q = q, H = P >> 1;
582 long long int D = 0x7ffffffffffffffLL;
583 for (n = mnmin; n <= mnmax; n++) {
584 m = mnmin; /* p/q ~ m/n -> p*n ~ m*q -> p*n-x*q ~ 0 */
585 L = P * n - m * Q; /* n * vco - m * fref should be near 0 */
586 while (L > 0 && m < mnmax) {
587 L -= q; /* difference is greater as 0 subtract fref */
588 m++; /* and increment m */
589 }
590 /* difference is less or equal than 0 or m > maximum */
591 if (m > mnmax)
592 break; /* no solution: if we increase n we get the same situation */
593 /* L is <= 0 now */
594 if (-L > H && m > mnmin) { /* if difference > the half fref */
595 L += q; /* we take the situation before */
596 m--; /* because its closer to 0 */
597 }
598 L = (L < 0) ? -L : +L; /* absolute value */
599 if (D < L) /* if last difference was better take next n */
600 continue;
601 D = L;
602 *pm = m;
603 *pn = n; /* keep improved data */
604 if (D == 0)
605 break; /* best result we can get */
606 }
607 return (unsigned int) (0xffffffff & D);
608 }
609
610 /* that is the hardware < 69000 we have to manage
611 +---------+ +-------------------+ +----------------------+ +--+
612 | REFCLK |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
613 | 14.3MHz | |(NTSCDS) (÷1, ÷5) | |Select (RDS) (÷1, ÷4) | | | |
614 +---------+ +-------------------+ +----------------------+ +--+ |
615 ___________________________________________________________________|
616 |
617 | fvco fout
618 | +--------+ +------------+ +-----+ +-------------------+ +----+
619 +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
620 +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
621 | +--------+ +------------+ +-----+ | +-------------------+ +----+
622 | |
623 | +--+ +---------------+ |
624 |____|÷M|___|VCO Loop Divide|__________|
625 | | |(VLD)(÷4, ÷16) |
626 +--+ +---------------+
627 ****************************************************************************
628 that is the hardware >= 69000 we have to manage
629 +---------+ +--+
630 | REFCLK |__|÷N|__
631 | 14.3MHz | | | |
632 +---------+ +--+ |
633 __________________|
634 |
635 | fvco fout
636 | +--------+ +------------+ +-----+ +-------------------+ +----+
637 +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
638 +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
639 | +--------+ +------------+ +-----+ | +-------------------+ +----+
640 | |
641 | +--+ +---------------+ |
642 |____|÷M|___|VCO Loop Divide|__________|
643 | | |(VLD)(÷1, ÷4) |
644 +--+ +---------------+
645
646
647 */
648
649 #define VIDEO_FREF 14318180; /* Hz */
650 /*****************************************************************************/
651 static int
652 ReadPixClckFromXrRegsBack (struct ctfb_chips_properties *param)
653 {
654 unsigned int m, n, vld, pd, PD, fref, xr_cb, i, pixclock;
655 i = 0;
656 pixclock = -1;
657 fref = VIDEO_FREF;
658 m = ctRead_i (CT_XR_O, 0xc8);
659 n = ctRead_i (CT_XR_O, 0xc9);
660 m -= param->mn_diff;
661 n -= param->mn_diff;
662 xr_cb = ctRead_i (CT_XR_O, 0xcb);
663 PD = (0x70 & xr_cb) >> 4;
664 pd = 1;
665 for (i = 0; i < PD; i++) {
666 pd *= 2;
667 }
668 vld = (0x04 & xr_cb) ? param->vld_set : param->vld_not_set;
669 if (n * vld * m) {
670 unsigned long long p = 1000000000000LL * pd * n;
671 unsigned long long q = (long long) fref * vld * m;
672 while ((p > 0xffffffffLL) || (q > 0xffffffffLL)) {
673 p >>= 1; /* can't divide with long long so we scale down */
674 q >>= 1;
675 }
676 pixclock = (unsigned) p / (unsigned) q;
677 } else
678 printf ("Invalid data in xr regs.\n");
679 return pixclock;
680 }
681
682 /*****************************************************************************/
683 static void
684 FindAndSetPllParamIntoXrRegs (unsigned int pixelclock,
685 struct ctfb_chips_properties *param)
686 {
687 unsigned int m, n, vld, pd, PD, fref, xr_cb;
688 unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk;
689 unsigned int pfreq, fvco, new_pixclock;
690 unsigned int D,nback,mback;
691
692 fref = VIDEO_FREF;
693 pd = 1;
694 PD = 0;
695 fvcomin = param->vco_min;
696 fvcomax = param->vco_max; /* MHz */
697 pclckmin = 1000000 / fvcomax + 1; /* 4546 */
698 pclckmax = 32000000 / fvcomin - 1; /* 666665 */
699 pclk = minmax (pclckmin, pixelclock, pclckmax); /* ps pp */
700 pfreq = 250 * (4000000000U / pclk);
701 fvco = pfreq; /* Hz */
702 new_pixclock = 0;
703 while (fvco < fvcomin * 1000000) {
704 /* double VCO starting with the pixelclock frequency
705 * as long as it is lower than the minimal VCO frequency */
706 fvco *= 2;
707 pd *= 2;
708 PD++;
709 }
710 /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */
711 /* first try */
712 vld = param->vld_set;
713 D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */
714 mback=m;
715 nback=n;
716 /* second try */
717 vld = param->vld_not_set;
718 if(D<FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n)) { /* rds = 1 */
719 /* first try was better */
720 m=mback;
721 n=nback;
722 vld = param->vld_set;
723 }
724 m += param->mn_diff;
725 n += param->mn_diff;
726 debug("VCO %d, pd %d, m %d n %d vld %d\n", fvco, pd, m, n, vld);
727 xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0);
728 /* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be
729 * written, and in order from XRC8 to XRCB, before the hardware will
730 * update the synthesizer s settings.
731 */
732 ctWrite_i (CT_XR_O, 0xc8, m);
733 ctWrite_i (CT_XR_O, 0xc9, n); /* xrca does not exist in CT69000 and CT69030 */
734 ctWrite_i (CT_XR_O, 0xca, 0); /* because of a hw bug I guess, but we write */
735 ctWrite_i (CT_XR_O, 0xcb, xr_cb); /* 0 to it for savety */
736 new_pixclock = ReadPixClckFromXrRegsBack (param);
737 debug("pixelclock.set = %d, pixelclock.real = %d\n",
738 pixelclock, new_pixclock);
739 }
740
741 /*****************************************************************************/
742 static void
743 SetMsrRegs (struct ctfb_res_modes *mode)
744 {
745 unsigned char h_synch_high, v_synch_high;
746
747 h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */
748 v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */
749 ctWrite (CT_MSR_W_O, (h_synch_high | v_synch_high | 0x29));
750 /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01
751 * Selects the upper 64KB page.Bit5=1
752 * CLK2 (left reserved in standard VGA) Bit3|2=1|0
753 * Disables CPU access to frame buffer. Bit1=0
754 * Sets the I/O address decode for ST01, FCR, and all CR registers
755 * to the 3Dx I/O address range (CGA emulation). Bit0=1
756 */
757 }
758
759 /************************************************************************************/
760 #ifdef VGA_DUMP_REG
761
762 static void
763 ctDispRegs (unsigned short index, int from, int to)
764 {
765 unsigned char status;
766 int i;
767
768 for (i = from; i < to; i++) {
769 status = ctRead_i (index, i);
770 printf ("%02X: is %02X\n", i, status);
771 }
772 }
773
774 void
775 video_dump_reg (void)
776 {
777 int i;
778
779 printf ("Extended Regs:\n");
780 ctDispRegs (CT_XR_O, 0, 0xC);
781 ctDispRegs (CT_XR_O, 0xe, 0xf);
782 ctDispRegs (CT_XR_O, 0x20, 0x21);
783 ctDispRegs (CT_XR_O, 0x40, 0x50);
784 ctDispRegs (CT_XR_O, 0x60, 0x64);
785 ctDispRegs (CT_XR_O, 0x67, 0x68);
786 ctDispRegs (CT_XR_O, 0x70, 0x72);
787 ctDispRegs (CT_XR_O, 0x80, 0x83);
788 ctDispRegs (CT_XR_O, 0xA0, 0xB0);
789 ctDispRegs (CT_XR_O, 0xC0, 0xD3);
790 printf ("Sequencer Regs:\n");
791 ctDispRegs (CT_SR_O, 0, 0x8);
792 printf ("Graphic Regs:\n");
793 ctDispRegs (CT_GR_O, 0, 0x9);
794 printf ("CRT Regs:\n");
795 ctDispRegs (CT_CR_O, 0, 0x19);
796 ctDispRegs (CT_CR_O, 0x22, 0x23);
797 ctDispRegs (CT_CR_O, 0x30, 0x34);
798 ctDispRegs (CT_CR_O, 0x38, 0x39);
799 ctDispRegs (CT_CR_O, 0x3C, 0x3D);
800 ctDispRegs (CT_CR_O, 0x40, 0x42);
801 ctDispRegs (CT_CR_O, 0x70, 0x80);
802 /* don't display the attributes */
803 }
804
805 #endif
806
807 #ifdef CONFIG_VIDEO_HW_CURSOR
808 /***************************************************************
809 * Set Hardware Cursor in Pixel
810 */
811 void
812 video_set_hw_cursor (int x, int y)
813 {
814 int sig_x = 0, sig_y = 0;
815 if (x < 0) {
816 x *= -1;
817 sig_x = 1;
818 }
819 if (y < 0) {
820 y *= -1;
821 sig_y = 1;
822 }
823 ctWrite_i (CT_XR_O, 0xa4, x & 0xff);
824 ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7);
825 ctWrite_i (CT_XR_O, 0xa6, y & 0xff);
826 ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7);
827 }
828
829 /***************************************************************
830 * Init Hardware Cursor. To know the size of the Cursor,
831 * we have to know the Font size.
832 */
833 void
834 video_init_hw_cursor (int font_width, int font_height)
835 {
836 unsigned char xr_80;
837 unsigned long *curs, pattern;
838 int i;
839 int cursor_start;
840 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
841
842 cursor_start = pGD->dprBase;
843 xr_80 = ctRead_i (CT_XR_O, 0x80);
844 /* set start address */
845 ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0);
846 ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f);
847 /* set cursor shape */
848 curs = (unsigned long *) cursor_start;
849 i = 0;
850 while (i < 0x400) {
851 curs[i++] = 0xffffffff; /* AND mask */
852 curs[i++] = 0xffffffff; /* AND mask */
853 curs[i++] = 0; /* XOR mask */
854 curs[i++] = 0; /* XOR mask */
855 /* Transparent */
856 }
857 pattern = 0xffffffff >> font_width;
858 i = 0;
859 while (i < (font_height * 2)) {
860 curs[i++] = pattern; /* AND mask */
861 curs[i++] = pattern; /* AND mask */
862 curs[i++] = 0; /* XOR mask */
863 curs[i++] = 0; /* XOR mask */
864 /* Cursor Color 0 */
865 }
866 /* set blink rate */
867 ctWrite_i (CT_FP_O, 0x19, 0xf);
868
869 /* set cursors colors */
870 xr_80 = ctRead_i (CT_XR_O, 0x80);
871 xr_80 |= 0x1; /* alternate palette select */
872 ctWrite_i (CT_XR_O, 0x80, xr_80);
873 video_set_lut(4, CONFIG_SYS_CONSOLE_FG_COL, CONFIG_SYS_CONSOLE_FG_COL,
874 CONFIG_SYS_CONSOLE_FG_COL);
875 /* position 4 is color 0 cursor 0 */
876 xr_80 &= 0xfe; /* normal palette select */
877 ctWrite_i (CT_XR_O, 0x80, xr_80);
878 /* cursor enable */
879 ctWrite_i (CT_XR_O, 0xa0, 0x91);
880 xr_80 |= 0x10; /* enable hwcursor */
881 ctWrite_i (CT_XR_O, 0x80, xr_80);
882 video_set_hw_cursor (0, 0);
883 }
884 #endif /* CONFIG_VIDEO_HW_CURSOR */
885
886 /***************************************************************
887 * Wait for BitBlt ready
888 */
889 static int
890 video_wait_bitblt (unsigned long addr)
891 {
892 unsigned long br04;
893 int i = 0;
894 br04 = in32r (addr);
895 while (br04 & 0x80000000) {
896 udelay (1);
897 br04 = in32r (addr);
898 if (i++ > 1000000) {
899 printf ("ERROR Timeout %lx\n", br04);
900 return 1;
901 }
902 }
903 return 0;
904 }
905
906 /***************************************************************
907 * Set up BitBlt Registrs
908 */
909 static void
910 SetDrawingEngine (int bits_per_pixel)
911 {
912 unsigned long br04, br00;
913 unsigned char tmp;
914
915 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
916
917 tmp = ctRead_i (CT_XR_O, 0x20); /* BitBLT Configuration */
918 tmp |= 0x02; /* reset BitBLT */
919 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
920 udelay (10);
921 tmp &= 0xfd; /* release reset BitBLT */
922 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
923 video_wait_bitblt (pGD->pciBase + BR04_o);
924
925 /* set pattern Address */
926 out32r (pGD->pciBase + BR05_o, PATTERN_ADR & 0x003ffff8);
927 br04 = 0;
928 if (bits_per_pixel == 1) {
929 br04 |= 0x00040000; /* monochome Pattern */
930 br04 |= 0x00001000; /* monochome source */
931 }
932 br00 = ((pGD->winSizeX * pGD->gdfBytesPP) << 16) + (pGD->winSizeX * pGD->gdfBytesPP); /* bytes per scanline */
933 out32r (pGD->pciBase + BR00_o, br00); /* */
934 out32r (pGD->pciBase + BR08_o, (10 << 16) + 10); /* dummy */
935 out32r (pGD->pciBase + BR04_o, br04); /* write all 0 */
936 out32r (pGD->pciBase + BR07_o, 0); /* destination */
937 video_wait_bitblt (pGD->pciBase + BR04_o);
938 }
939
940 /****************************************************************************
941 * supported Video Chips
942 */
943 static struct pci_device_id supported[] = {
944 {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
945 {}
946 };
947
948 /*******************************************************************************
949 *
950 * Init video chip
951 */
952 void *
953 video_hw_init (void)
954 {
955 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
956 unsigned short device_id;
957 pci_dev_t devbusfn;
958 int videomode;
959 unsigned long t1, hsynch, vsynch;
960 unsigned int pci_mem_base, *vm;
961 int tmp, i, bits_per_pixel;
962 char *penv;
963 struct ctfb_res_modes *res_mode;
964 struct ctfb_res_modes var_mode;
965 struct ctfb_chips_properties *chips_param;
966 /* Search for video chip */
967
968 if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
969 #ifdef CONFIG_VIDEO_ONBOARD
970 printf ("Video: Controller not found !\n");
971 #endif
972 return (NULL);
973 }
974
975 /* PCI setup */
976 pci_write_config_dword (devbusfn, PCI_COMMAND,
977 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
978 pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
979 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
980 pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base);
981
982 /* get chips params */
983 for (chips_param = (struct ctfb_chips_properties *) &chips[0];
984 chips_param->device_id != 0; chips_param++) {
985 if (chips_param->device_id == device_id)
986 break;
987 }
988 if (chips_param->device_id == 0) {
989 #ifdef CONFIG_VIDEO_ONBOARD
990 printf ("Video: controller 0x%X not supported\n", device_id);
991 #endif
992 return NULL;
993 }
994 /* supported Video controller found */
995 printf ("Video: ");
996
997 tmp = 0;
998 videomode = 0x301;
999 /* get video mode via environment */
1000 if ((penv = getenv ("videomode")) != NULL) {
1001 /* deceide if it is a string */
1002 if (penv[0] <= '9') {
1003 videomode = (int) simple_strtoul (penv, NULL, 16);
1004 tmp = 1;
1005 }
1006 } else {
1007 tmp = 1;
1008 }
1009 if (tmp) {
1010 /* parameter are vesa modes */
1011 /* search params */
1012 for (i = 0; i < VESA_MODES_COUNT; i++) {
1013 if (vesa_modes[i].vesanr == videomode)
1014 break;
1015 }
1016 if (i == VESA_MODES_COUNT) {
1017 printf ("no VESA Mode found, switching to mode 0x301 ");
1018 i = 0;
1019 }
1020 res_mode =
1021 (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].
1022 resindex];
1023 bits_per_pixel = vesa_modes[i].bits_per_pixel;
1024 } else {
1025
1026 res_mode = (struct ctfb_res_modes *) &var_mode;
1027 bits_per_pixel = video_get_params (res_mode, penv);
1028 }
1029
1030 /* calculate available color depth for controller memory */
1031 if (bits_per_pixel == 15)
1032 tmp = 2;
1033 else
1034 tmp = bits_per_pixel >> 3; /* /8 */
1035 if (((chips_param->max_mem -
1036 ACCELMEMORY) / (res_mode->xres * res_mode->yres)) < tmp) {
1037 tmp =
1038 ((chips_param->max_mem -
1039 ACCELMEMORY) / (res_mode->xres * res_mode->yres));
1040 if (tmp == 0) {
1041 printf
1042 ("No matching videomode found .-> reduce resolution\n");
1043 return NULL;
1044 } else {
1045 printf ("Switching back to %d Bits per Pixel ",
1046 tmp << 3);
1047 bits_per_pixel = tmp << 3;
1048 }
1049 }
1050
1051 /* calculate hsynch and vsynch freq (info only) */
1052 t1 = (res_mode->left_margin + res_mode->xres +
1053 res_mode->right_margin + res_mode->hsync_len) / 8;
1054 t1 *= 8;
1055 t1 *= res_mode->pixclock;
1056 t1 /= 1000;
1057 hsynch = 1000000000L / t1;
1058 t1 *=
1059 (res_mode->upper_margin + res_mode->yres +
1060 res_mode->lower_margin + res_mode->vsync_len);
1061 t1 /= 1000;
1062 vsynch = 1000000000L / t1;
1063
1064 /* fill in Graphic device struct */
1065 sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
1066 res_mode->yres, bits_per_pixel, (hsynch / 1000),
1067 (vsynch / 1000));
1068 printf ("%s\n", pGD->modeIdent);
1069 pGD->winSizeX = res_mode->xres;
1070 pGD->winSizeY = res_mode->yres;
1071 pGD->plnSizeX = res_mode->xres;
1072 pGD->plnSizeY = res_mode->yres;
1073 switch (bits_per_pixel) {
1074 case 8:
1075 pGD->gdfBytesPP = 1;
1076 pGD->gdfIndex = GDF__8BIT_INDEX;
1077 break;
1078 case 15:
1079 pGD->gdfBytesPP = 2;
1080 pGD->gdfIndex = GDF_15BIT_555RGB;
1081 break;
1082 case 16:
1083 pGD->gdfBytesPP = 2;
1084 pGD->gdfIndex = GDF_16BIT_565RGB;
1085 break;
1086 case 24:
1087 pGD->gdfBytesPP = 3;
1088 pGD->gdfIndex = GDF_24BIT_888RGB;
1089 break;
1090 }
1091 pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
1092 pGD->pciBase = pci_mem_base;
1093 pGD->frameAdrs = pci_mem_base;
1094 pGD->memSize = chips_param->max_mem;
1095 /* Cursor Start Address */
1096 pGD->dprBase =
1097 (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + pci_mem_base;
1098 if ((pGD->dprBase & 0x0fff) != 0) {
1099 /* allign it */
1100 pGD->dprBase &= 0xfffff000;
1101 pGD->dprBase += 0x00001000;
1102 }
1103 debug("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
1104 PATTERN_ADR);
1105 pGD->vprBase = pci_mem_base; /* Dummy */
1106 pGD->cprBase = pci_mem_base; /* Dummy */
1107 /* set up Hardware */
1108
1109 ctWrite (CT_MSR_W_O, 0x01);
1110
1111 /* set the extended Registers */
1112 ctLoadRegs (CT_XR_O, xreg);
1113 /* set atribute registers */
1114 SetArRegs ();
1115 /* set Graphics register */
1116 SetGrRegs ();
1117 /* set sequencer */
1118 SetSrRegs ();
1119
1120 /* set msr */
1121 SetMsrRegs (res_mode);
1122
1123 /* set CRT Registers */
1124 SetCrRegs (res_mode, bits_per_pixel);
1125 /* set color mode */
1126 SetBitsPerPixelIntoXrRegs (bits_per_pixel);
1127
1128 /* set PLL */
1129 FindAndSetPllParamIntoXrRegs (res_mode->pixclock, chips_param);
1130
1131 ctWrite_i (CT_SR_O, 0, 0x03); /* clear synchronous reset */
1132 /* Clear video memory */
1133 i = pGD->memSize / 4;
1134 vm = (unsigned int *) pGD->pciBase;
1135 while (i--)
1136 *vm++ = 0;
1137 SetDrawingEngine (bits_per_pixel);
1138 #ifdef VGA_DUMP_REG
1139 video_dump_reg ();
1140 #endif
1141
1142 return ((void *) &ctfb);
1143 }
1144
1145 /*******************************************************************************
1146 *
1147 * Set a RGB color in the LUT (8 bit index)
1148 */
1149 void
1150 video_set_lut (unsigned int index, /* color number */
1151 unsigned char r, /* red */
1152 unsigned char g, /* green */
1153 unsigned char b /* blue */
1154 )
1155 {
1156
1157 ctWrite (CT_LUT_MASK_O, 0xff);
1158
1159 ctWrite (CT_LUT_START_O, (char) index);
1160
1161 ctWrite (CT_LUT_RGB_O, r); /* red */
1162 ctWrite (CT_LUT_RGB_O, g); /* green */
1163 ctWrite (CT_LUT_RGB_O, b); /* blue */
1164 udelay (1);
1165 ctWrite (CT_LUT_MASK_O, 0xff);
1166 }
1167
1168 /*******************************************************************************
1169 *
1170 * Drawing engine fill on screen region
1171 */
1172 void
1173 video_hw_rectfill (unsigned int bpp, /* bytes per pixel */
1174 unsigned int dst_x, /* dest pos x */
1175 unsigned int dst_y, /* dest pos y */
1176 unsigned int dim_x, /* frame width */
1177 unsigned int dim_y, /* frame height */
1178 unsigned int color /* fill color */
1179 )
1180 {
1181 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
1182 unsigned long *p, br04;
1183
1184 video_wait_bitblt (pGD->pciBase + BR04_o);
1185
1186 p = (unsigned long *) PATTERN_ADR;
1187 dim_x *= bpp;
1188 if (bpp == 3)
1189 bpp++; /* 24Bit needs a 32bit pattern */
1190 memset (p, color, (bpp * sizeof (unsigned char) * 8 * 8)); /* 8 x 8 pattern data */
1191 out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */
1192 br04 = in32r (pGD->pciBase + BR04_o) & 0xffffff00;
1193 br04 |= 0xF0; /* write Pattern P -> D */
1194 out32r (pGD->pciBase + BR04_o, br04); /* */
1195 out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* starts the BITBlt */
1196 video_wait_bitblt (pGD->pciBase + BR04_o);
1197 }
1198
1199 /*******************************************************************************
1200 *
1201 * Drawing engine bitblt with screen region
1202 */
1203 void
1204 video_hw_bitblt (unsigned int bpp, /* bytes per pixel */
1205 unsigned int src_x, /* source pos x */
1206 unsigned int src_y, /* source pos y */
1207 unsigned int dst_x, /* dest pos x */
1208 unsigned int dst_y, /* dest pos y */
1209 unsigned int dim_x, /* frame width */
1210 unsigned int dim_y /* frame height */
1211 )
1212 {
1213 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
1214 unsigned long br04;
1215
1216 br04 = in32r (pGD->pciBase + BR04_o);
1217
1218 /* to prevent data corruption due to overlap, we have to
1219 * find out if, and how the frames overlaps */
1220 if (src_x < dst_x) {
1221 /* src is more left than dest
1222 * the frame may overlap -> start from right to left */
1223 br04 |= 0x00000100; /* set bit 8 */
1224 src_x += dim_x;
1225 dst_x += dim_x;
1226 } else {
1227 br04 &= 0xfffffeff; /* clear bit 8 left to right */
1228 }
1229 if (src_y < dst_y) {
1230 /* src is higher than dst
1231 * the frame may overlap => start from bottom */
1232 br04 |= 0x00000200; /* set bit 9 */
1233 src_y += dim_y;
1234 dst_y += dim_y;
1235 } else {
1236 br04 &= 0xfffffdff; /* clear bit 9 top to bottom */
1237 }
1238 dim_x *= bpp;
1239 out32r (pGD->pciBase + BR06_o, ((pGD->winSizeX * src_y) + src_x) * pGD->gdfBytesPP); /* source */
1240 out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */
1241 br04 &= 0xffffff00;
1242 br04 |= 0x000000CC; /* S -> D */
1243 out32r (pGD->pciBase + BR04_o, br04); /* */
1244 out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* start the BITBlt */
1245 video_wait_bitblt (pGD->pciBase + BR04_o);
1246 }
1247 #endif /* CONFIG_VIDEO */
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