5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
7 * Linux IPU driver for MX51:
9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/types.h>
17 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/crm_regs.h>
22 #include <asm/arch/sys_proto.h>
27 extern struct mxc_ccm_reg
*mxc_ccm
;
28 extern u32
*ipu_cpmem_base
;
30 struct ipu_ch_param_word
{
36 struct ipu_ch_param_word word
[2];
39 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
41 #define _param_word(base, w) \
42 (((struct ipu_ch_param *)(base))->word[(w)].data)
44 #define ipu_ch_param_set_field(base, w, bit, size, v) { \
46 int off = (bit) % 32; \
47 _param_word(base, w)[i] |= (v) << off; \
48 if (((bit) + (size) - 1) / 32 > i) { \
49 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
53 #define ipu_ch_param_mod_field(base, w, bit, size, v) { \
55 int off = (bit) % 32; \
56 u32 mask = (1UL << size) - 1; \
57 u32 temp = _param_word(base, w)[i]; \
58 temp &= ~(mask << off); \
59 _param_word(base, w)[i] = temp | (v) << off; \
60 if (((bit) + (size) - 1) / 32 > i) { \
61 temp = _param_word(base, w)[i + 1]; \
62 temp &= ~(mask >> (32 - off)); \
63 _param_word(base, w)[i + 1] = \
64 temp | ((v) >> (off ? (32 - off) : 0)); \
68 #define ipu_ch_param_read_field(base, w, bit, size) ({ \
71 int off = (bit) % 32; \
72 u32 mask = (1UL << size) - 1; \
73 u32 temp1 = _param_word(base, w)[i]; \
74 temp1 = mask & (temp1 >> off); \
75 if (((bit)+(size) - 1) / 32 > i) { \
76 temp2 = _param_word(base, w)[i + 1]; \
77 temp2 &= mask >> (off ? (32 - off) : 0); \
78 temp1 |= temp2 << (off ? (32 - off) : 0); \
83 #define IPU_SW_RST_TOUT_USEC (10000)
85 #define IPUV3_CLK_MX51 133000000
86 #define IPUV3_CLK_MX53 200000000
87 #define IPUV3_CLK_MX6Q 264000000
88 #define IPUV3_CLK_MX6DL 198000000
90 void clk_enable(struct clk
*clk
)
93 if (clk
->usecount
++ == 0) {
99 void clk_disable(struct clk
*clk
)
102 if (!(--clk
->usecount
)) {
109 int clk_get_usecount(struct clk
*clk
)
114 return clk
->usecount
;
117 u32
clk_get_rate(struct clk
*clk
)
125 struct clk
*clk_get_parent(struct clk
*clk
)
133 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
135 if (clk
&& clk
->set_rate
)
136 clk
->set_rate(clk
, rate
);
140 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
142 if (clk
== NULL
|| !clk
->round_rate
)
145 return clk
->round_rate(clk
, rate
);
148 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
150 clk
->parent
= parent
;
152 return clk
->set_parent(clk
, parent
);
156 static int clk_ipu_enable(struct clk
*clk
)
160 reg
= __raw_readl(clk
->enable_reg
);
161 reg
|= MXC_CCM_CCGR_CG_MASK
<< clk
->enable_shift
;
162 __raw_writel(reg
, clk
->enable_reg
);
164 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
165 /* Handshake with IPU when certain clock rates are changed. */
166 reg
= __raw_readl(&mxc_ccm
->ccdr
);
167 reg
&= ~MXC_CCM_CCDR_IPU_HS_MASK
;
168 __raw_writel(reg
, &mxc_ccm
->ccdr
);
170 /* Handshake with IPU when LPM is entered as its enabled. */
171 reg
= __raw_readl(&mxc_ccm
->clpcr
);
172 reg
&= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS
;
173 __raw_writel(reg
, &mxc_ccm
->clpcr
);
178 static void clk_ipu_disable(struct clk
*clk
)
182 reg
= __raw_readl(clk
->enable_reg
);
183 reg
&= ~(MXC_CCM_CCGR_CG_MASK
<< clk
->enable_shift
);
184 __raw_writel(reg
, clk
->enable_reg
);
186 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
188 * No handshake with IPU whe dividers are changed
189 * as its not enabled.
191 reg
= __raw_readl(&mxc_ccm
->ccdr
);
192 reg
|= MXC_CCM_CCDR_IPU_HS_MASK
;
193 __raw_writel(reg
, &mxc_ccm
->ccdr
);
195 /* No handshake with IPU when LPM is entered as its not enabled. */
196 reg
= __raw_readl(&mxc_ccm
->clpcr
);
197 reg
|= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS
;
198 __raw_writel(reg
, &mxc_ccm
->clpcr
);
203 static struct clk ipu_clk
= {
205 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
206 .enable_reg
= (u32
*)(CCM_BASE_ADDR
+
207 offsetof(struct mxc_ccm_reg
, CCGR5
)),
208 .enable_shift
= MXC_CCM_CCGR5_IPU_OFFSET
,
210 .enable_reg
= (u32
*)(CCM_BASE_ADDR
+
211 offsetof(struct mxc_ccm_reg
, CCGR3
)),
212 .enable_shift
= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
,
214 .enable
= clk_ipu_enable
,
215 .disable
= clk_ipu_disable
,
219 #if !defined CONFIG_SYS_LDB_CLOCK
220 #define CONFIG_SYS_LDB_CLOCK 65000000
223 static struct clk ldb_clk
= {
225 .rate
= CONFIG_SYS_LDB_CLOCK
,
230 struct clk
*g_ipu_clk
;
231 struct clk
*g_ldb_clk
;
232 unsigned char g_ipu_clk_enabled
;
233 struct clk
*g_di_clk
[2];
234 struct clk
*g_pixel_clk
[2];
235 unsigned char g_dc_di_assignment
[10];
236 uint32_t g_channel_init_mask
;
237 uint32_t g_channel_enable_mask
;
239 static int ipu_dc_use_count
;
240 static int ipu_dp_use_count
;
241 static int ipu_dmfc_use_count
;
242 static int ipu_di_use_count
[2];
245 u32
*ipu_dc_tmpl_reg
;
247 /* Static functions */
249 static inline void ipu_ch_param_set_high_priority(uint32_t ch
)
251 ipu_ch_param_mod_field(ipu_ch_param_addr(ch
), 1, 93, 2, 1);
254 static inline uint32_t channel_2_dma(ipu_channel_t ch
, ipu_buffer_t type
)
256 return ((uint32_t) ch
>> (6 * type
)) & 0x3F;
259 /* Either DP BG or DP FG can be graphic window */
260 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan
)
262 return (dma_chan
== 23 || dma_chan
== 27);
265 static inline int ipu_is_dmfc_chan(uint32_t dma_chan
)
267 return ((dma_chan
>= 23) && (dma_chan
<= 29));
271 static inline void ipu_ch_param_set_buffer(uint32_t ch
, int bufNum
,
274 ipu_ch_param_mod_field(ipu_ch_param_addr(ch
), 1, 29 * bufNum
, 29,
278 #define idma_is_valid(ch) (ch != NO_DMA)
279 #define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
280 #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
282 static void ipu_pixel_clk_recalc(struct clk
*clk
)
285 u64 final_rate
= (unsigned long long)clk
->parent
->rate
* 16;
287 div
= __raw_readl(DI_BS_CLKGEN0(clk
->id
));
288 debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
289 div
, final_rate
, clk
->parent
->rate
);
293 do_div(final_rate
, div
);
294 clk
->rate
= final_rate
;
298 static unsigned long ipu_pixel_clk_round_rate(struct clk
*clk
,
303 u64 parent_rate
= (unsigned long long)clk
->parent
->rate
* 16;
307 * Fractional part is 4 bits,
308 * so simply multiply by 2^4 to get fractional part.
311 remainder
= do_div(div
, rate
);
312 /* Round the divider value */
313 if (remainder
> (rate
/ 2))
315 if (div
< 0x10) /* Min DI disp clock divider is 1 */
320 /* Round up divider if it gets us closer to desired pix clk */
321 if ((div
& 0xC) == 0xC) {
326 final_rate
= parent_rate
;
327 do_div(final_rate
, div
);
332 static int ipu_pixel_clk_set_rate(struct clk
*clk
, unsigned long rate
)
334 u64 div
, parent_rate
;
337 parent_rate
= (unsigned long long)clk
->parent
->rate
* 16;
339 remainder
= do_div(div
, rate
);
340 /* Round the divider value */
341 if (remainder
> (rate
/ 2))
344 /* Round up divider if it gets us closer to desired pix clk */
345 if ((div
& 0xC) == 0xC) {
350 debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32
)div
);
352 __raw_writel(div
, DI_BS_CLKGEN0(clk
->id
));
355 * Setup pixel clock timing
356 * Down time is half of period
358 __raw_writel((div
/ 16) << 16, DI_BS_CLKGEN1(clk
->id
));
360 do_div(parent_rate
, div
);
362 clk
->rate
= parent_rate
;
367 static int ipu_pixel_clk_enable(struct clk
*clk
)
369 u32 disp_gen
= __raw_readl(IPU_DISP_GEN
);
370 disp_gen
|= clk
->id
? DI1_COUNTER_RELEASE
: DI0_COUNTER_RELEASE
;
371 __raw_writel(disp_gen
, IPU_DISP_GEN
);
376 static void ipu_pixel_clk_disable(struct clk
*clk
)
378 u32 disp_gen
= __raw_readl(IPU_DISP_GEN
);
379 disp_gen
&= clk
->id
? ~DI1_COUNTER_RELEASE
: ~DI0_COUNTER_RELEASE
;
380 __raw_writel(disp_gen
, IPU_DISP_GEN
);
384 static int ipu_pixel_clk_set_parent(struct clk
*clk
, struct clk
*parent
)
386 u32 di_gen
= __raw_readl(DI_GENERAL(clk
->id
));
388 if (parent
== g_ipu_clk
)
389 di_gen
&= ~DI_GEN_DI_CLK_EXT
;
390 else if (!IS_ERR(g_di_clk
[clk
->id
]) && parent
== g_ldb_clk
)
391 di_gen
|= DI_GEN_DI_CLK_EXT
;
395 __raw_writel(di_gen
, DI_GENERAL(clk
->id
));
396 ipu_pixel_clk_recalc(clk
);
400 static struct clk pixel_clk
[] = {
404 .recalc
= ipu_pixel_clk_recalc
,
405 .set_rate
= ipu_pixel_clk_set_rate
,
406 .round_rate
= ipu_pixel_clk_round_rate
,
407 .set_parent
= ipu_pixel_clk_set_parent
,
408 .enable
= ipu_pixel_clk_enable
,
409 .disable
= ipu_pixel_clk_disable
,
415 .recalc
= ipu_pixel_clk_recalc
,
416 .set_rate
= ipu_pixel_clk_set_rate
,
417 .round_rate
= ipu_pixel_clk_round_rate
,
418 .set_parent
= ipu_pixel_clk_set_parent
,
419 .enable
= ipu_pixel_clk_enable
,
420 .disable
= ipu_pixel_clk_disable
,
426 * This function resets IPU
428 static void ipu_reset(void)
432 int timeout
= IPU_SW_RST_TOUT_USEC
;
434 reg
= (u32
*)SRC_BASE_ADDR
;
435 value
= __raw_readl(reg
);
436 value
= value
| SW_IPU_RST
;
437 __raw_writel(value
, reg
);
439 while (__raw_readl(reg
) & SW_IPU_RST
) {
442 printf("ipu software reset timeout\n");
449 * This function is called by the driver framework to initialize the IPU
452 * @param dev The device structure for the IPU passed in by the
455 * @return Returns 0 on success or negative error code on error
459 unsigned long ipu_base
;
460 #if defined CONFIG_MX51
463 u32
*reg_hsc_mcd
= (u32
*)MIPI_HSC_BASE_ADDR
;
464 u32
*reg_hsc_mxt_conf
= (u32
*)(MIPI_HSC_BASE_ADDR
+ 0x800);
466 __raw_writel(0xF00, reg_hsc_mcd
);
468 /* CSI mode reserved*/
469 temp
= __raw_readl(reg_hsc_mxt_conf
);
470 __raw_writel(temp
| 0x0FF, reg_hsc_mxt_conf
);
472 temp
= __raw_readl(reg_hsc_mxt_conf
);
473 __raw_writel(temp
| 0x10000, reg_hsc_mxt_conf
);
476 ipu_base
= IPU_CTRL_BASE_ADDR
;
477 ipu_cpmem_base
= (u32
*)(ipu_base
+ IPU_CPMEM_REG_BASE
);
478 ipu_dc_tmpl_reg
= (u32
*)(ipu_base
+ IPU_DC_TMPL_REG_BASE
);
480 g_pixel_clk
[0] = &pixel_clk
[0];
481 g_pixel_clk
[1] = &pixel_clk
[1];
483 g_ipu_clk
= &ipu_clk
;
484 #if defined(CONFIG_MX51)
485 g_ipu_clk
->rate
= IPUV3_CLK_MX51
;
486 #elif defined(CONFIG_MX53)
487 g_ipu_clk
->rate
= IPUV3_CLK_MX53
;
489 g_ipu_clk
->rate
= is_mx6sdl() ? IPUV3_CLK_MX6DL
: IPUV3_CLK_MX6Q
;
491 debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk
));
492 g_ldb_clk
= &ldb_clk
;
493 debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk
));
496 clk_set_parent(g_pixel_clk
[0], g_ipu_clk
);
497 clk_set_parent(g_pixel_clk
[1], g_ipu_clk
);
498 clk_enable(g_ipu_clk
);
503 __raw_writel(0x807FFFFF, IPU_MEM_RST
);
504 while (__raw_readl(IPU_MEM_RST
) & 0x80000000)
507 ipu_init_dc_mappings();
509 __raw_writel(0, IPU_INT_CTRL(5));
510 __raw_writel(0, IPU_INT_CTRL(6));
511 __raw_writel(0, IPU_INT_CTRL(9));
512 __raw_writel(0, IPU_INT_CTRL(10));
515 ipu_dmfc_init(DMFC_NORMAL
, 1);
517 /* Set sync refresh channels as high priority */
518 __raw_writel(0x18800000L
, IDMAC_CHA_PRI(0));
520 /* Set MCU_T to divide MCU access window into 2 */
521 __raw_writel(0x00400000L
| (IPU_MCU_T_DEFAULT
<< 18), IPU_DISP_GEN
);
523 clk_disable(g_ipu_clk
);
528 void ipu_dump_registers(void)
530 debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF
));
531 debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF
));
532 debug("IDMAC_CHA_EN1 = \t0x%08X\n",
533 __raw_readl(IDMAC_CHA_EN(0)));
534 debug("IDMAC_CHA_EN2 = \t0x%08X\n",
535 __raw_readl(IDMAC_CHA_EN(32)));
536 debug("IDMAC_CHA_PRI1 = \t0x%08X\n",
537 __raw_readl(IDMAC_CHA_PRI(0)));
538 debug("IDMAC_CHA_PRI2 = \t0x%08X\n",
539 __raw_readl(IDMAC_CHA_PRI(32)));
540 debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
541 __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
542 debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
543 __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
544 debug("DMFC_WR_CHAN = \t0x%08X\n",
545 __raw_readl(DMFC_WR_CHAN
));
546 debug("DMFC_WR_CHAN_DEF = \t0x%08X\n",
547 __raw_readl(DMFC_WR_CHAN_DEF
));
548 debug("DMFC_DP_CHAN = \t0x%08X\n",
549 __raw_readl(DMFC_DP_CHAN
));
550 debug("DMFC_DP_CHAN_DEF = \t0x%08X\n",
551 __raw_readl(DMFC_DP_CHAN_DEF
));
552 debug("DMFC_IC_CTRL = \t0x%08X\n",
553 __raw_readl(DMFC_IC_CTRL
));
554 debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n",
555 __raw_readl(IPU_FS_PROC_FLOW1
));
556 debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n",
557 __raw_readl(IPU_FS_PROC_FLOW2
));
558 debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n",
559 __raw_readl(IPU_FS_PROC_FLOW3
));
560 debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n",
561 __raw_readl(IPU_FS_DISP_FLOW1
));
565 * This function is called to initialize a logical IPU channel.
567 * @param channel Input parameter for the logical channel ID to init.
569 * @param params Input parameter containing union of channel
570 * initialization parameters.
572 * @return Returns 0 on success or negative error code on fail
574 int32_t ipu_init_channel(ipu_channel_t channel
, ipu_channel_params_t
*params
)
579 debug("init channel = %d\n", IPU_CHAN_ID(channel
));
581 if (g_ipu_clk_enabled
== 0) {
582 g_ipu_clk_enabled
= 1;
583 clk_enable(g_ipu_clk
);
587 if (g_channel_init_mask
& (1L << IPU_CHAN_ID(channel
))) {
588 printf("Warning: channel already initialized %d\n",
589 IPU_CHAN_ID(channel
));
592 ipu_conf
= __raw_readl(IPU_CONF
);
596 if (params
->mem_dc_sync
.di
> 1) {
601 g_dc_di_assignment
[1] = params
->mem_dc_sync
.di
;
602 ipu_dc_init(1, params
->mem_dc_sync
.di
,
603 params
->mem_dc_sync
.interlaced
);
604 ipu_di_use_count
[params
->mem_dc_sync
.di
]++;
606 ipu_dmfc_use_count
++;
609 if (params
->mem_dp_bg_sync
.di
> 1) {
614 g_dc_di_assignment
[5] = params
->mem_dp_bg_sync
.di
;
615 ipu_dp_init(channel
, params
->mem_dp_bg_sync
.in_pixel_fmt
,
616 params
->mem_dp_bg_sync
.out_pixel_fmt
);
617 ipu_dc_init(5, params
->mem_dp_bg_sync
.di
,
618 params
->mem_dp_bg_sync
.interlaced
);
619 ipu_di_use_count
[params
->mem_dp_bg_sync
.di
]++;
622 ipu_dmfc_use_count
++;
625 ipu_dp_init(channel
, params
->mem_dp_fg_sync
.in_pixel_fmt
,
626 params
->mem_dp_fg_sync
.out_pixel_fmt
);
630 ipu_dmfc_use_count
++;
633 printf("Missing channel initialization\n");
637 /* Enable IPU sub module */
638 g_channel_init_mask
|= 1L << IPU_CHAN_ID(channel
);
639 if (ipu_dc_use_count
== 1)
640 ipu_conf
|= IPU_CONF_DC_EN
;
641 if (ipu_dp_use_count
== 1)
642 ipu_conf
|= IPU_CONF_DP_EN
;
643 if (ipu_dmfc_use_count
== 1)
644 ipu_conf
|= IPU_CONF_DMFC_EN
;
645 if (ipu_di_use_count
[0] == 1) {
646 ipu_conf
|= IPU_CONF_DI0_EN
;
648 if (ipu_di_use_count
[1] == 1) {
649 ipu_conf
|= IPU_CONF_DI1_EN
;
652 __raw_writel(ipu_conf
, IPU_CONF
);
659 * This function is called to uninitialize a logical IPU channel.
661 * @param channel Input parameter for the logical channel ID to uninit.
663 void ipu_uninit_channel(ipu_channel_t channel
)
666 uint32_t in_dma
, out_dma
= 0;
669 if ((g_channel_init_mask
& (1L << IPU_CHAN_ID(channel
))) == 0) {
670 debug("Channel already uninitialized %d\n",
671 IPU_CHAN_ID(channel
));
676 * Make sure channel is disabled
677 * Get input and output dma channels
679 in_dma
= channel_2_dma(channel
, IPU_OUTPUT_BUFFER
);
680 out_dma
= channel_2_dma(channel
, IPU_VIDEO_IN_BUFFER
);
682 if (idma_is_set(IDMAC_CHA_EN
, in_dma
) ||
683 idma_is_set(IDMAC_CHA_EN
, out_dma
)) {
685 "Channel %d is not disabled, disable first\n",
686 IPU_CHAN_ID(channel
));
690 ipu_conf
= __raw_readl(IPU_CONF
);
692 /* Reset the double buffer */
693 reg
= __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma
));
694 __raw_writel(reg
& ~idma_mask(in_dma
), IPU_CHA_DB_MODE_SEL(in_dma
));
695 reg
= __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma
));
696 __raw_writel(reg
& ~idma_mask(out_dma
), IPU_CHA_DB_MODE_SEL(out_dma
));
701 ipu_di_use_count
[g_dc_di_assignment
[1]]--;
703 ipu_dmfc_use_count
--;
706 ipu_dp_uninit(channel
);
708 ipu_di_use_count
[g_dc_di_assignment
[5]]--;
711 ipu_dmfc_use_count
--;
714 ipu_dp_uninit(channel
);
717 ipu_dmfc_use_count
--;
723 g_channel_init_mask
&= ~(1L << IPU_CHAN_ID(channel
));
725 if (ipu_dc_use_count
== 0)
726 ipu_conf
&= ~IPU_CONF_DC_EN
;
727 if (ipu_dp_use_count
== 0)
728 ipu_conf
&= ~IPU_CONF_DP_EN
;
729 if (ipu_dmfc_use_count
== 0)
730 ipu_conf
&= ~IPU_CONF_DMFC_EN
;
731 if (ipu_di_use_count
[0] == 0) {
732 ipu_conf
&= ~IPU_CONF_DI0_EN
;
734 if (ipu_di_use_count
[1] == 0) {
735 ipu_conf
&= ~IPU_CONF_DI1_EN
;
738 __raw_writel(ipu_conf
, IPU_CONF
);
741 clk_disable(g_ipu_clk
);
742 g_ipu_clk_enabled
= 0;
747 static inline void ipu_ch_param_dump(int ch
)
750 struct ipu_ch_param
*p
= ipu_ch_param_addr(ch
);
751 debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch
,
752 p
->word
[0].data
[0], p
->word
[0].data
[1], p
->word
[0].data
[2],
753 p
->word
[0].data
[3], p
->word
[0].data
[4]);
754 debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch
,
755 p
->word
[1].data
[0], p
->word
[1].data
[1], p
->word
[1].data
[2],
756 p
->word
[1].data
[3], p
->word
[1].data
[4]);
758 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 85, 4));
760 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 0, 107, 3));
762 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 78, 7));
765 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 0, 125, 13));
767 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 0, 138, 12));
769 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 102, 14));
771 debug("Width0 %d+1, ",
772 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 116, 3));
773 debug("Width1 %d+1, ",
774 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 119, 3));
775 debug("Width2 %d+1, ",
776 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 122, 3));
777 debug("Width3 %d+1, ",
778 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 125, 3));
779 debug("Offset0 %d, ",
780 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 128, 5));
781 debug("Offset1 %d, ",
782 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 133, 5));
783 debug("Offset2 %d, ",
784 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 138, 5));
785 debug("Offset3 %d\n",
786 ipu_ch_param_read_field(ipu_ch_param_addr(ch
), 1, 143, 5));
790 static inline void ipu_ch_params_set_packing(struct ipu_ch_param
*p
,
791 int red_width
, int red_offset
,
792 int green_width
, int green_offset
,
793 int blue_width
, int blue_offset
,
794 int alpha_width
, int alpha_offset
)
796 /* Setup red width and offset */
797 ipu_ch_param_set_field(p
, 1, 116, 3, red_width
- 1);
798 ipu_ch_param_set_field(p
, 1, 128, 5, red_offset
);
799 /* Setup green width and offset */
800 ipu_ch_param_set_field(p
, 1, 119, 3, green_width
- 1);
801 ipu_ch_param_set_field(p
, 1, 133, 5, green_offset
);
802 /* Setup blue width and offset */
803 ipu_ch_param_set_field(p
, 1, 122, 3, blue_width
- 1);
804 ipu_ch_param_set_field(p
, 1, 138, 5, blue_offset
);
805 /* Setup alpha width and offset */
806 ipu_ch_param_set_field(p
, 1, 125, 3, alpha_width
- 1);
807 ipu_ch_param_set_field(p
, 1, 143, 5, alpha_offset
);
810 static void ipu_ch_param_init(int ch
,
811 uint32_t pixel_fmt
, uint32_t width
,
812 uint32_t height
, uint32_t stride
,
813 uint32_t u
, uint32_t v
,
814 uint32_t uv_stride
, dma_addr_t addr0
,
817 uint32_t u_offset
= 0;
818 uint32_t v_offset
= 0;
819 struct ipu_ch_param params
;
821 memset(¶ms
, 0, sizeof(params
));
823 ipu_ch_param_set_field(¶ms
, 0, 125, 13, width
- 1);
825 if ((ch
== 8) || (ch
== 9) || (ch
== 10)) {
826 ipu_ch_param_set_field(¶ms
, 0, 138, 12, (height
/ 2) - 1);
827 ipu_ch_param_set_field(¶ms
, 1, 102, 14, (stride
* 2) - 1);
829 ipu_ch_param_set_field(¶ms
, 0, 138, 12, height
- 1);
830 ipu_ch_param_set_field(¶ms
, 1, 102, 14, stride
- 1);
833 ipu_ch_param_set_field(¶ms
, 1, 0, 29, addr0
>> 3);
834 ipu_ch_param_set_field(¶ms
, 1, 29, 29, addr1
>> 3);
837 case IPU_PIX_FMT_GENERIC
:
838 /*Represents 8-bit Generic data */
839 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 5); /* bits/pixel */
840 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 6); /* pix format */
841 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 63); /* burst size */
844 case IPU_PIX_FMT_GENERIC_32
:
845 /*Represents 32-bit Generic data */
847 case IPU_PIX_FMT_RGB565
:
848 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 3); /* bits/pixel */
849 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
850 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 15); /* burst size */
852 ipu_ch_params_set_packing(¶ms
, 5, 0, 6, 5, 5, 11, 8, 16);
854 case IPU_PIX_FMT_BGR24
:
855 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 1); /* bits/pixel */
856 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
857 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 19); /* burst size */
859 ipu_ch_params_set_packing(¶ms
, 8, 0, 8, 8, 8, 16, 8, 24);
861 case IPU_PIX_FMT_RGB24
:
862 case IPU_PIX_FMT_YUV444
:
863 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 1); /* bits/pixel */
864 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
865 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 19); /* burst size */
867 ipu_ch_params_set_packing(¶ms
, 8, 16, 8, 8, 8, 0, 8, 24);
869 case IPU_PIX_FMT_BGRA32
:
870 case IPU_PIX_FMT_BGR32
:
871 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 0); /* bits/pixel */
872 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
873 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 15); /* burst size */
875 ipu_ch_params_set_packing(¶ms
, 8, 8, 8, 16, 8, 24, 8, 0);
877 case IPU_PIX_FMT_RGBA32
:
878 case IPU_PIX_FMT_RGB32
:
879 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 0); /* bits/pixel */
880 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
881 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 15); /* burst size */
883 ipu_ch_params_set_packing(¶ms
, 8, 24, 8, 16, 8, 8, 8, 0);
885 case IPU_PIX_FMT_ABGR32
:
886 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 0); /* bits/pixel */
887 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 7); /* pix format */
889 ipu_ch_params_set_packing(¶ms
, 8, 0, 8, 8, 8, 16, 8, 24);
891 case IPU_PIX_FMT_UYVY
:
892 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 3); /* bits/pixel */
893 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 0xA); /* pix format */
894 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 15); /* burst size */
896 case IPU_PIX_FMT_YUYV
:
897 ipu_ch_param_set_field(¶ms
, 0, 107, 3, 3); /* bits/pixel */
898 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 0x8); /* pix format */
899 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 31); /* burst size */
901 case IPU_PIX_FMT_YUV420P2
:
902 case IPU_PIX_FMT_YUV420P
:
903 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 2); /* pix format */
905 if (uv_stride
< stride
/ 2)
906 uv_stride
= stride
/ 2;
908 u_offset
= stride
* height
;
909 v_offset
= u_offset
+ (uv_stride
* height
/ 2);
911 if ((ch
== 8) || (ch
== 9) || (ch
== 10)) {
912 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 15);
913 uv_stride
= uv_stride
*2;
915 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 31);
918 case IPU_PIX_FMT_YVU422P
:
919 /* BPP & pixel format */
920 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 1); /* pix format */
921 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 31); /* burst size */
923 if (uv_stride
< stride
/ 2)
924 uv_stride
= stride
/ 2;
926 v_offset
= (v
== 0) ? stride
* height
: v
;
927 u_offset
= (u
== 0) ? v_offset
+ v_offset
/ 2 : u
;
929 case IPU_PIX_FMT_YUV422P
:
930 /* BPP & pixel format */
931 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 1); /* pix format */
932 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 31); /* burst size */
934 if (uv_stride
< stride
/ 2)
935 uv_stride
= stride
/ 2;
937 u_offset
= (u
== 0) ? stride
* height
: u
;
938 v_offset
= (v
== 0) ? u_offset
+ u_offset
/ 2 : v
;
940 case IPU_PIX_FMT_NV12
:
941 /* BPP & pixel format */
942 ipu_ch_param_set_field(¶ms
, 1, 85, 4, 4); /* pix format */
943 ipu_ch_param_set_field(¶ms
, 1, 78, 7, 31); /* burst size */
945 u_offset
= (u
== 0) ? stride
* height
: u
;
948 puts("mxc ipu: unimplemented pixel format\n");
954 ipu_ch_param_set_field(¶ms
, 1, 128, 14, uv_stride
- 1);
956 /* Get the uv offset from user when need cropping */
962 /* UBO and VBO are 22-bit */
963 if (u_offset
/8 > 0x3fffff)
964 puts("The value of U offset exceeds IPU limitation\n");
965 if (v_offset
/8 > 0x3fffff)
966 puts("The value of V offset exceeds IPU limitation\n");
968 ipu_ch_param_set_field(¶ms
, 0, 46, 22, u_offset
/ 8);
969 ipu_ch_param_set_field(¶ms
, 0, 68, 22, v_offset
/ 8);
971 debug("initializing idma ch %d @ %p\n", ch
, ipu_ch_param_addr(ch
));
972 memcpy(ipu_ch_param_addr(ch
), ¶ms
, sizeof(params
));
976 * This function is called to initialize a buffer for logical IPU channel.
978 * @param channel Input parameter for the logical channel ID.
980 * @param type Input parameter which buffer to initialize.
982 * @param pixel_fmt Input parameter for pixel format of buffer.
983 * Pixel format is a FOURCC ASCII code.
985 * @param width Input parameter for width of buffer in pixels.
987 * @param height Input parameter for height of buffer in pixels.
989 * @param stride Input parameter for stride length of buffer
992 * @param phyaddr_0 Input parameter buffer 0 physical address.
994 * @param phyaddr_1 Input parameter buffer 1 physical address.
995 * Setting this to a value other than NULL enables
996 * double buffering mode.
998 * @param u private u offset for additional cropping,
1001 * @param v private v offset for additional cropping,
1004 * @return Returns 0 on success or negative error code on fail
1006 int32_t ipu_init_channel_buffer(ipu_channel_t channel
, ipu_buffer_t type
,
1008 uint16_t width
, uint16_t height
,
1010 dma_addr_t phyaddr_0
, dma_addr_t phyaddr_1
,
1011 uint32_t u
, uint32_t v
)
1016 dma_chan
= channel_2_dma(channel
, type
);
1017 if (!idma_is_valid(dma_chan
))
1020 if (stride
< width
* bytes_per_pixel(pixel_fmt
))
1021 stride
= width
* bytes_per_pixel(pixel_fmt
);
1025 "Stride not 32-bit aligned, stride = %d\n", stride
);
1028 /* Build parameter memory data for DMA channel */
1029 ipu_ch_param_init(dma_chan
, pixel_fmt
, width
, height
, stride
, u
, v
, 0,
1030 phyaddr_0
, phyaddr_1
);
1032 if (ipu_is_dmfc_chan(dma_chan
)) {
1033 ipu_dmfc_set_wait4eot(dma_chan
, width
);
1036 if (idma_is_set(IDMAC_CHA_PRI
, dma_chan
))
1037 ipu_ch_param_set_high_priority(dma_chan
);
1039 ipu_ch_param_dump(dma_chan
);
1041 reg
= __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan
));
1043 reg
|= idma_mask(dma_chan
);
1045 reg
&= ~idma_mask(dma_chan
);
1046 __raw_writel(reg
, IPU_CHA_DB_MODE_SEL(dma_chan
));
1048 /* Reset to buffer 0 */
1049 __raw_writel(idma_mask(dma_chan
), IPU_CHA_CUR_BUF(dma_chan
));
1055 * This function enables a logical channel.
1057 * @param channel Input parameter for the logical channel ID.
1059 * @return This function returns 0 on success or negative error code on
1062 int32_t ipu_enable_channel(ipu_channel_t channel
)
1068 if (g_channel_enable_mask
& (1L << IPU_CHAN_ID(channel
))) {
1069 printf("Warning: channel already enabled %d\n",
1070 IPU_CHAN_ID(channel
));
1073 /* Get input and output dma channels */
1074 out_dma
= channel_2_dma(channel
, IPU_OUTPUT_BUFFER
);
1075 in_dma
= channel_2_dma(channel
, IPU_VIDEO_IN_BUFFER
);
1077 if (idma_is_valid(in_dma
)) {
1078 reg
= __raw_readl(IDMAC_CHA_EN(in_dma
));
1079 __raw_writel(reg
| idma_mask(in_dma
), IDMAC_CHA_EN(in_dma
));
1081 if (idma_is_valid(out_dma
)) {
1082 reg
= __raw_readl(IDMAC_CHA_EN(out_dma
));
1083 __raw_writel(reg
| idma_mask(out_dma
), IDMAC_CHA_EN(out_dma
));
1086 if ((channel
== MEM_DC_SYNC
) || (channel
== MEM_BG_SYNC
) ||
1087 (channel
== MEM_FG_SYNC
))
1088 ipu_dp_dc_enable(channel
);
1090 g_channel_enable_mask
|= 1L << IPU_CHAN_ID(channel
);
1096 * This function clear buffer ready for a logical channel.
1098 * @param channel Input parameter for the logical channel ID.
1100 * @param type Input parameter which buffer to clear.
1102 * @param bufNum Input parameter for which buffer number clear
1106 void ipu_clear_buffer_ready(ipu_channel_t channel
, ipu_buffer_t type
,
1109 uint32_t dma_ch
= channel_2_dma(channel
, type
);
1111 if (!idma_is_valid(dma_ch
))
1114 __raw_writel(0xF0000000, IPU_GPR
); /* write one to clear */
1116 if (idma_is_set(IPU_CHA_BUF0_RDY
, dma_ch
)) {
1117 __raw_writel(idma_mask(dma_ch
),
1118 IPU_CHA_BUF0_RDY(dma_ch
));
1121 if (idma_is_set(IPU_CHA_BUF1_RDY
, dma_ch
)) {
1122 __raw_writel(idma_mask(dma_ch
),
1123 IPU_CHA_BUF1_RDY(dma_ch
));
1126 __raw_writel(0x0, IPU_GPR
); /* write one to set */
1130 * This function disables a logical channel.
1132 * @param channel Input parameter for the logical channel ID.
1134 * @param wait_for_stop Flag to set whether to wait for channel end
1135 * of frame or return immediately.
1137 * @return This function returns 0 on success or negative error code on
1140 int32_t ipu_disable_channel(ipu_channel_t channel
)
1146 if ((g_channel_enable_mask
& (1L << IPU_CHAN_ID(channel
))) == 0) {
1147 debug("Channel already disabled %d\n",
1148 IPU_CHAN_ID(channel
));
1152 /* Get input and output dma channels */
1153 out_dma
= channel_2_dma(channel
, IPU_OUTPUT_BUFFER
);
1154 in_dma
= channel_2_dma(channel
, IPU_VIDEO_IN_BUFFER
);
1156 if ((idma_is_valid(in_dma
) &&
1157 !idma_is_set(IDMAC_CHA_EN
, in_dma
))
1158 && (idma_is_valid(out_dma
) &&
1159 !idma_is_set(IDMAC_CHA_EN
, out_dma
)))
1162 if ((channel
== MEM_BG_SYNC
) || (channel
== MEM_FG_SYNC
) ||
1163 (channel
== MEM_DC_SYNC
)) {
1164 ipu_dp_dc_disable(channel
, 0);
1167 /* Disable DMA channel(s) */
1168 if (idma_is_valid(in_dma
)) {
1169 reg
= __raw_readl(IDMAC_CHA_EN(in_dma
));
1170 __raw_writel(reg
& ~idma_mask(in_dma
), IDMAC_CHA_EN(in_dma
));
1171 __raw_writel(idma_mask(in_dma
), IPU_CHA_CUR_BUF(in_dma
));
1173 if (idma_is_valid(out_dma
)) {
1174 reg
= __raw_readl(IDMAC_CHA_EN(out_dma
));
1175 __raw_writel(reg
& ~idma_mask(out_dma
), IDMAC_CHA_EN(out_dma
));
1176 __raw_writel(idma_mask(out_dma
), IPU_CHA_CUR_BUF(out_dma
));
1179 g_channel_enable_mask
&= ~(1L << IPU_CHAN_ID(channel
));
1181 /* Set channel buffers NOT to be ready */
1182 if (idma_is_valid(in_dma
)) {
1183 ipu_clear_buffer_ready(channel
, IPU_VIDEO_IN_BUFFER
, 0);
1184 ipu_clear_buffer_ready(channel
, IPU_VIDEO_IN_BUFFER
, 1);
1186 if (idma_is_valid(out_dma
)) {
1187 ipu_clear_buffer_ready(channel
, IPU_OUTPUT_BUFFER
, 0);
1188 ipu_clear_buffer_ready(channel
, IPU_OUTPUT_BUFFER
, 1);
1194 uint32_t bytes_per_pixel(uint32_t fmt
)
1197 case IPU_PIX_FMT_GENERIC
: /*generic data */
1198 case IPU_PIX_FMT_RGB332
:
1199 case IPU_PIX_FMT_YUV420P
:
1200 case IPU_PIX_FMT_YUV422P
:
1203 case IPU_PIX_FMT_RGB565
:
1204 case IPU_PIX_FMT_YUYV
:
1205 case IPU_PIX_FMT_UYVY
:
1208 case IPU_PIX_FMT_BGR24
:
1209 case IPU_PIX_FMT_RGB24
:
1212 case IPU_PIX_FMT_GENERIC_32
: /*generic data */
1213 case IPU_PIX_FMT_BGR32
:
1214 case IPU_PIX_FMT_BGRA32
:
1215 case IPU_PIX_FMT_RGB32
:
1216 case IPU_PIX_FMT_RGBA32
:
1217 case IPU_PIX_FMT_ABGR32
:
1227 ipu_color_space_t
format_to_colorspace(uint32_t fmt
)
1230 case IPU_PIX_FMT_RGB666
:
1231 case IPU_PIX_FMT_RGB565
:
1232 case IPU_PIX_FMT_BGR24
:
1233 case IPU_PIX_FMT_RGB24
:
1234 case IPU_PIX_FMT_BGR32
:
1235 case IPU_PIX_FMT_BGRA32
:
1236 case IPU_PIX_FMT_RGB32
:
1237 case IPU_PIX_FMT_RGBA32
:
1238 case IPU_PIX_FMT_ABGR32
:
1239 case IPU_PIX_FMT_LVDS666
:
1240 case IPU_PIX_FMT_LVDS888
:
1251 /* should be removed when clk framework is availiable */
1252 int ipu_set_ldb_clock(int rate
)
1254 ldb_clk
.rate
= rate
;
1259 bool ipu_clk_enabled(void)
1261 return g_ipu_clk_enabled
;