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Merge branch 'master' of git://git.denx.de/u-boot-ti
[people/ms/u-boot.git] / drivers / video / ipu_disp.c
1 /*
2 * Porting to u-boot:
3 *
4 * (C) Copyright 2010
5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
6 *
7 * Linux IPU driver for MX51:
8 *
9 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14 /* #define DEBUG */
15
16 #include <common.h>
17 #include <linux/types.h>
18 #include <asm/errno.h>
19 #include <asm/io.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/sys_proto.h>
22 #include "ipu.h"
23 #include "ipu_regs.h"
24
25 enum csc_type_t {
26 RGB2YUV = 0,
27 YUV2RGB,
28 RGB2RGB,
29 YUV2YUV,
30 CSC_NONE,
31 CSC_NUM
32 };
33
34 struct dp_csc_param_t {
35 int mode;
36 const int (*coeff)[5][3];
37 };
38
39 #define SYNC_WAVE 0
40
41 /* DC display ID assignments */
42 #define DC_DISP_ID_SYNC(di) (di)
43 #define DC_DISP_ID_SERIAL 2
44 #define DC_DISP_ID_ASYNC 3
45
46 int dmfc_type_setup;
47 static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
48 int g_di1_tvout;
49
50 extern struct clk *g_ipu_clk;
51 extern struct clk *g_ldb_clk;
52 extern struct clk *g_di_clk[2];
53 extern struct clk *g_pixel_clk[2];
54
55 extern unsigned char g_ipu_clk_enabled;
56 extern unsigned char g_dc_di_assignment[];
57
58 void ipu_dmfc_init(int dmfc_type, int first)
59 {
60 u32 dmfc_wr_chan, dmfc_dp_chan;
61
62 if (first) {
63 if (dmfc_type_setup > dmfc_type)
64 dmfc_type = dmfc_type_setup;
65 else
66 dmfc_type_setup = dmfc_type;
67
68 /* disable DMFC-IC channel*/
69 __raw_writel(0x2, DMFC_IC_CTRL);
70 } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
71 printf("DMFC high resolution has set, will not change\n");
72 return;
73 } else
74 dmfc_type_setup = dmfc_type;
75
76 if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
77 /* 1 - segment 0~3;
78 * 5B - segement 4, 5;
79 * 5F - segement 6, 7;
80 * 1C, 2C and 6B, 6F unused;
81 */
82 debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n");
83 dmfc_wr_chan = 0x00000088;
84 dmfc_dp_chan = 0x00009694;
85 dmfc_size_28 = 256 * 4;
86 dmfc_size_29 = 0;
87 dmfc_size_24 = 0;
88 dmfc_size_27 = 128 * 4;
89 dmfc_size_23 = 128 * 4;
90 } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
91 /* 1 - segment 0, 1;
92 * 5B - segement 2~5;
93 * 5F - segement 6,7;
94 * 1C, 2C and 6B, 6F unused;
95 */
96 debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n");
97 dmfc_wr_chan = 0x00000090;
98 dmfc_dp_chan = 0x0000968a;
99 dmfc_size_28 = 128 * 4;
100 dmfc_size_29 = 0;
101 dmfc_size_24 = 0;
102 dmfc_size_27 = 128 * 4;
103 dmfc_size_23 = 256 * 4;
104 } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
105 /* 5B - segement 0~3;
106 * 5F - segement 4~7;
107 * 1, 1C, 2C and 6B, 6F unused;
108 */
109 debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n");
110 dmfc_wr_chan = 0x00000000;
111 dmfc_dp_chan = 0x00008c88;
112 dmfc_size_28 = 0;
113 dmfc_size_29 = 0;
114 dmfc_size_24 = 0;
115 dmfc_size_27 = 256 * 4;
116 dmfc_size_23 = 256 * 4;
117 } else {
118 /* 1 - segment 0, 1;
119 * 5B - segement 4, 5;
120 * 5F - segement 6, 7;
121 * 1C, 2C and 6B, 6F unused;
122 */
123 debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
124 dmfc_wr_chan = 0x00000090;
125 dmfc_dp_chan = 0x00009694;
126 dmfc_size_28 = 128 * 4;
127 dmfc_size_29 = 0;
128 dmfc_size_24 = 0;
129 dmfc_size_27 = 128 * 4;
130 dmfc_size_23 = 128 * 4;
131 }
132 __raw_writel(dmfc_wr_chan, DMFC_WR_CHAN);
133 __raw_writel(0x202020F6, DMFC_WR_CHAN_DEF);
134 __raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
135 /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
136 __raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF);
137 }
138
139 void ipu_dmfc_set_wait4eot(int dma_chan, int width)
140 {
141 u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1);
142
143 if (width >= HIGH_RESOLUTION_WIDTH) {
144 if (dma_chan == 23)
145 ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0);
146 else if (dma_chan == 28)
147 ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0);
148 }
149
150 if (dma_chan == 23) { /*5B*/
151 if (dmfc_size_23 / width > 3)
152 dmfc_gen1 |= 1UL << 20;
153 else
154 dmfc_gen1 &= ~(1UL << 20);
155 } else if (dma_chan == 24) { /*6B*/
156 if (dmfc_size_24 / width > 1)
157 dmfc_gen1 |= 1UL << 22;
158 else
159 dmfc_gen1 &= ~(1UL << 22);
160 } else if (dma_chan == 27) { /*5F*/
161 if (dmfc_size_27 / width > 2)
162 dmfc_gen1 |= 1UL << 21;
163 else
164 dmfc_gen1 &= ~(1UL << 21);
165 } else if (dma_chan == 28) { /*1*/
166 if (dmfc_size_28 / width > 2)
167 dmfc_gen1 |= 1UL << 16;
168 else
169 dmfc_gen1 &= ~(1UL << 16);
170 } else if (dma_chan == 29) { /*6F*/
171 if (dmfc_size_29 / width > 1)
172 dmfc_gen1 |= 1UL << 23;
173 else
174 dmfc_gen1 &= ~(1UL << 23);
175 }
176
177 __raw_writel(dmfc_gen1, DMFC_GENERAL1);
178 }
179
180 static void ipu_di_data_wave_config(int di,
181 int wave_gen,
182 int access_size, int component_size)
183 {
184 u32 reg;
185 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
186 (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
187 __raw_writel(reg, DI_DW_GEN(di, wave_gen));
188 }
189
190 static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,
191 int up, int down)
192 {
193 u32 reg;
194
195 reg = __raw_readl(DI_DW_GEN(di, wave_gen));
196 reg &= ~(0x3 << (di_pin * 2));
197 reg |= set << (di_pin * 2);
198 __raw_writel(reg, DI_DW_GEN(di, wave_gen));
199
200 __raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set));
201 }
202
203 static void ipu_di_sync_config(int di, int wave_gen,
204 int run_count, int run_src,
205 int offset_count, int offset_src,
206 int repeat_count, int cnt_clr_src,
207 int cnt_polarity_gen_en,
208 int cnt_polarity_clr_src,
209 int cnt_polarity_trigger_src,
210 int cnt_up, int cnt_down)
211 {
212 u32 reg;
213
214 if ((run_count >= 0x1000) || (offset_count >= 0x1000) ||
215 (repeat_count >= 0x1000) ||
216 (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
217 printf("DI%d counters out of range.\n", di);
218 return;
219 }
220
221 reg = (run_count << 19) | (++run_src << 16) |
222 (offset_count << 3) | ++offset_src;
223 __raw_writel(reg, DI_SW_GEN0(di, wave_gen));
224 reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
225 (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
226 reg |= (cnt_down << 16) | cnt_up;
227 if (repeat_count == 0) {
228 /* Enable auto reload */
229 reg |= 0x10000000;
230 }
231 __raw_writel(reg, DI_SW_GEN1(di, wave_gen));
232 reg = __raw_readl(DI_STP_REP(di, wave_gen));
233 reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
234 reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
235 __raw_writel(reg, DI_STP_REP(di, wave_gen));
236 }
237
238 static void ipu_dc_map_config(int map, int byte_num, int offset, int mask)
239 {
240 int ptr = map * 3 + byte_num;
241 u32 reg;
242
243 reg = __raw_readl(DC_MAP_CONF_VAL(ptr));
244 reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
245 reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
246 __raw_writel(reg, DC_MAP_CONF_VAL(ptr));
247
248 reg = __raw_readl(DC_MAP_CONF_PTR(map));
249 reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
250 reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
251 __raw_writel(reg, DC_MAP_CONF_PTR(map));
252 }
253
254 static void ipu_dc_map_clear(int map)
255 {
256 u32 reg = __raw_readl(DC_MAP_CONF_PTR(map));
257 __raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))),
258 DC_MAP_CONF_PTR(map));
259 }
260
261 static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,
262 int wave, int glue, int sync)
263 {
264 u32 reg;
265 int stop = 1;
266
267 reg = sync;
268 reg |= (glue << 4);
269 reg |= (++wave << 11);
270 reg |= (++map << 15);
271 reg |= (operand << 20) & 0xFFF00000;
272 __raw_writel(reg, ipu_dc_tmpl_reg + word * 2);
273
274 reg = (operand >> 12);
275 reg |= opcode << 4;
276 reg |= (stop << 9);
277 __raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1);
278 }
279
280 static void ipu_dc_link_event(int chan, int event, int addr, int priority)
281 {
282 u32 reg;
283
284 reg = __raw_readl(DC_RL_CH(chan, event));
285 reg &= ~(0xFFFF << (16 * (event & 0x1)));
286 reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
287 __raw_writel(reg, DC_RL_CH(chan, event));
288 }
289
290 /* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250;
291 * U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.;
292 * V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;
293 */
294 static const int rgb2ycbcr_coeff[5][3] = {
295 {0x4D, 0x96, 0x1D},
296 {0x3D5, 0x3AB, 0x80},
297 {0x80, 0x395, 0x3EB},
298 {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */
299 {0x2, 0x2, 0x2}, /* S0, S1, S2 */
300 };
301
302 /* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
303 * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
304 * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
305 */
306 static const int ycbcr2rgb_coeff[5][3] = {
307 {0x095, 0x000, 0x0CC},
308 {0x095, 0x3CE, 0x398},
309 {0x095, 0x0FF, 0x000},
310 {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */
311 {0x1, 0x1, 0x1}, /*S0,S1,S2 */
312 };
313
314 #define mask_a(a) ((u32)(a) & 0x3FF)
315 #define mask_b(b) ((u32)(b) & 0x3FFF)
316
317 /* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
318 static int rgb_to_yuv(int n, int red, int green, int blue)
319 {
320 int c;
321 c = red * rgb2ycbcr_coeff[n][0];
322 c += green * rgb2ycbcr_coeff[n][1];
323 c += blue * rgb2ycbcr_coeff[n][2];
324 c /= 16;
325 c += rgb2ycbcr_coeff[3][n] * 4;
326 c += 8;
327 c /= 16;
328 if (c < 0)
329 c = 0;
330 if (c > 255)
331 c = 255;
332 return c;
333 }
334
335 /*
336 * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
337 * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
338 */
339 static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
340 {
341 {DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff},
342 {0, 0},
343 {0, 0},
344 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff},
345 {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}
346 },
347 {
348 {0, 0},
349 {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff},
350 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff},
351 {0, 0},
352 {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}
353 },
354 {
355 {0, 0},
356 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
357 {0, 0},
358 {0, 0},
359 {0, 0}
360 },
361 {
362 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
363 {0, 0},
364 {0, 0},
365 {0, 0},
366 {0, 0}
367 },
368 {
369 {DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
370 {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
371 {0, 0},
372 {0, 0},
373 {0, 0}
374 }
375 };
376
377 static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
378 static int color_key_4rgb = 1;
379
380 static void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
381 unsigned char srm_mode_update)
382 {
383 u32 reg;
384 const int (*coeff)[5][3];
385
386 if (dp_csc_param.mode >= 0) {
387 reg = __raw_readl(DP_COM_CONF());
388 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
389 reg |= dp_csc_param.mode;
390 __raw_writel(reg, DP_COM_CONF());
391 }
392
393 coeff = dp_csc_param.coeff;
394
395 if (coeff) {
396 __raw_writel(mask_a((*coeff)[0][0]) |
397 (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0());
398 __raw_writel(mask_a((*coeff)[0][2]) |
399 (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1());
400 __raw_writel(mask_a((*coeff)[1][1]) |
401 (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2());
402 __raw_writel(mask_a((*coeff)[2][0]) |
403 (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3());
404 __raw_writel(mask_a((*coeff)[2][2]) |
405 (mask_b((*coeff)[3][0]) << 16) |
406 ((*coeff)[4][0] << 30), DP_CSC_0());
407 __raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
408 (mask_b((*coeff)[3][2]) << 16) |
409 ((*coeff)[4][2] << 30), DP_CSC_1());
410 }
411
412 if (srm_mode_update) {
413 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
414 __raw_writel(reg, IPU_SRM_PRI2);
415 }
416 }
417
418 int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
419 uint32_t out_pixel_fmt)
420 {
421 int in_fmt, out_fmt;
422 int dp;
423 int partial = 0;
424 uint32_t reg;
425
426 if (channel == MEM_FG_SYNC) {
427 dp = DP_SYNC;
428 partial = 1;
429 } else if (channel == MEM_BG_SYNC) {
430 dp = DP_SYNC;
431 partial = 0;
432 } else if (channel == MEM_BG_ASYNC0) {
433 dp = DP_ASYNC0;
434 partial = 0;
435 } else {
436 return -EINVAL;
437 }
438
439 in_fmt = format_to_colorspace(in_pixel_fmt);
440 out_fmt = format_to_colorspace(out_pixel_fmt);
441
442 if (partial) {
443 if (in_fmt == RGB) {
444 if (out_fmt == RGB)
445 fg_csc_type = RGB2RGB;
446 else
447 fg_csc_type = RGB2YUV;
448 } else {
449 if (out_fmt == RGB)
450 fg_csc_type = YUV2RGB;
451 else
452 fg_csc_type = YUV2YUV;
453 }
454 } else {
455 if (in_fmt == RGB) {
456 if (out_fmt == RGB)
457 bg_csc_type = RGB2RGB;
458 else
459 bg_csc_type = RGB2YUV;
460 } else {
461 if (out_fmt == RGB)
462 bg_csc_type = YUV2RGB;
463 else
464 bg_csc_type = YUV2YUV;
465 }
466 }
467
468 /* Transform color key from rgb to yuv if CSC is enabled */
469 reg = __raw_readl(DP_COM_CONF());
470 if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
471 (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
472 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
473 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
474 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
475 int red, green, blue;
476 int y, u, v;
477 uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &
478 0xFFFFFFL;
479
480 debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
481 color_key);
482
483 red = (color_key >> 16) & 0xFF;
484 green = (color_key >> 8) & 0xFF;
485 blue = color_key & 0xFF;
486
487 y = rgb_to_yuv(0, red, green, blue);
488 u = rgb_to_yuv(1, red, green, blue);
489 v = rgb_to_yuv(2, red, green, blue);
490 color_key = (y << 16) | (u << 8) | v;
491
492 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
493 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
494 color_key_4rgb = 0;
495
496 debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n",
497 color_key);
498 }
499
500 ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1);
501
502 return 0;
503 }
504
505 void ipu_dp_uninit(ipu_channel_t channel)
506 {
507 int dp;
508 int partial = 0;
509
510 if (channel == MEM_FG_SYNC) {
511 dp = DP_SYNC;
512 partial = 1;
513 } else if (channel == MEM_BG_SYNC) {
514 dp = DP_SYNC;
515 partial = 0;
516 } else if (channel == MEM_BG_ASYNC0) {
517 dp = DP_ASYNC0;
518 partial = 0;
519 } else {
520 return;
521 }
522
523 if (partial)
524 fg_csc_type = CSC_NONE;
525 else
526 bg_csc_type = CSC_NONE;
527
528 ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0);
529 }
530
531 void ipu_dc_init(int dc_chan, int di, unsigned char interlaced)
532 {
533 u32 reg = 0;
534
535 if ((dc_chan == 1) || (dc_chan == 5)) {
536 if (interlaced) {
537 ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3);
538 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2);
539 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1);
540 } else {
541 if (di) {
542 ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);
543 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);
544 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
545 4, 1);
546 } else {
547 ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);
548 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);
549 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
550 7, 1);
551 }
552 }
553 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
554 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
555 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
556 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
557 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
558 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
559
560 reg = 0x2;
561 reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
562 reg |= di << 2;
563 if (interlaced)
564 reg |= DC_WR_CH_CONF_FIELD_MODE;
565 } else if ((dc_chan == 8) || (dc_chan == 9)) {
566 /* async channels */
567 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
568 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
569
570 reg = 0x3;
571 reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
572 }
573 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
574
575 __raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan));
576
577 __raw_writel(0x00000084, DC_GEN);
578 }
579
580 void ipu_dc_uninit(int dc_chan)
581 {
582 if ((dc_chan == 1) || (dc_chan == 5)) {
583 ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0);
584 ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0);
585 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0);
586 ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
587 ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
588 ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
589 ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
590 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
591 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
592 } else if ((dc_chan == 8) || (dc_chan == 9)) {
593 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
594 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
595 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
596 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
597 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
598 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
599 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
600 ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
601 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
602 ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
603 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
604 ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
605 }
606 }
607
608 void ipu_dp_dc_enable(ipu_channel_t channel)
609 {
610 int di;
611 uint32_t reg;
612 uint32_t dc_chan;
613
614 if (channel == MEM_FG_SYNC)
615 dc_chan = 5;
616 if (channel == MEM_DC_SYNC)
617 dc_chan = 1;
618 else if (channel == MEM_BG_SYNC)
619 dc_chan = 5;
620 else
621 return;
622
623 if (channel == MEM_FG_SYNC) {
624 /* Enable FG channel */
625 reg = __raw_readl(DP_COM_CONF());
626 __raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF());
627
628 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
629 __raw_writel(reg, IPU_SRM_PRI2);
630 return;
631 }
632
633 di = g_dc_di_assignment[dc_chan];
634
635 /* Make sure other DC sync channel is not assigned same DI */
636 reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan));
637 if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
638 reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
639 reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
640 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
641 }
642
643 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
644 reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
645 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
646
647 clk_enable(g_pixel_clk[di]);
648 }
649
650 static unsigned char dc_swap;
651
652 void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
653 {
654 uint32_t reg;
655 uint32_t csc;
656 uint32_t dc_chan = 0;
657 int timeout = 50;
658 int irq = 0;
659
660 dc_swap = swap;
661
662 if (channel == MEM_DC_SYNC) {
663 dc_chan = 1;
664 irq = IPU_IRQ_DC_FC_1;
665 } else if (channel == MEM_BG_SYNC) {
666 dc_chan = 5;
667 irq = IPU_IRQ_DP_SF_END;
668 } else if (channel == MEM_FG_SYNC) {
669 /* Disable FG channel */
670 dc_chan = 5;
671
672 reg = __raw_readl(DP_COM_CONF());
673 csc = reg & DP_COM_CONF_CSC_DEF_MASK;
674 if (csc == DP_COM_CONF_CSC_DEF_FG)
675 reg &= ~DP_COM_CONF_CSC_DEF_MASK;
676
677 reg &= ~DP_COM_CONF_FG_EN;
678 __raw_writel(reg, DP_COM_CONF());
679
680 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
681 __raw_writel(reg, IPU_SRM_PRI2);
682
683 timeout = 50;
684
685 /*
686 * Wait for DC triple buffer to empty,
687 * this check is useful for tv overlay.
688 */
689 if (g_dc_di_assignment[dc_chan] == 0)
690 while ((__raw_readl(DC_STAT) & 0x00000002)
691 != 0x00000002) {
692 udelay(2000);
693 timeout -= 2;
694 if (timeout <= 0)
695 break;
696 }
697 else if (g_dc_di_assignment[dc_chan] == 1)
698 while ((__raw_readl(DC_STAT) & 0x00000020)
699 != 0x00000020) {
700 udelay(2000);
701 timeout -= 2;
702 if (timeout <= 0)
703 break;
704 }
705 return;
706 } else {
707 return;
708 }
709
710 if (dc_swap) {
711 /* Swap DC channel 1 and 5 settings, and disable old dc chan */
712 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
713 __raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
714 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
715 reg ^= DC_WR_CH_CONF_PROG_DI_ID;
716 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
717 } else {
718 /* Make sure that we leave at the irq starting edge */
719 __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
720 do {
721 reg = __raw_readl(IPUIRQ_2_STATREG(irq));
722 } while (!(reg & IPUIRQ_2_MASK(irq)));
723
724 reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
725 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
726 __raw_writel(reg, DC_WR_CH_CONF(dc_chan));
727
728 reg = __raw_readl(IPU_DISP_GEN);
729 if (g_dc_di_assignment[dc_chan])
730 reg &= ~DI1_COUNTER_RELEASE;
731 else
732 reg &= ~DI0_COUNTER_RELEASE;
733 __raw_writel(reg, IPU_DISP_GEN);
734
735 /* Clock is already off because it must be done quickly, but
736 we need to fix the ref count */
737 clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]);
738 }
739 }
740
741 void ipu_init_dc_mappings(void)
742 {
743 /* IPU_PIX_FMT_RGB24 */
744 ipu_dc_map_clear(0);
745 ipu_dc_map_config(0, 0, 7, 0xFF);
746 ipu_dc_map_config(0, 1, 15, 0xFF);
747 ipu_dc_map_config(0, 2, 23, 0xFF);
748
749 /* IPU_PIX_FMT_RGB666 */
750 ipu_dc_map_clear(1);
751 ipu_dc_map_config(1, 0, 5, 0xFC);
752 ipu_dc_map_config(1, 1, 11, 0xFC);
753 ipu_dc_map_config(1, 2, 17, 0xFC);
754
755 /* IPU_PIX_FMT_YUV444 */
756 ipu_dc_map_clear(2);
757 ipu_dc_map_config(2, 0, 15, 0xFF);
758 ipu_dc_map_config(2, 1, 23, 0xFF);
759 ipu_dc_map_config(2, 2, 7, 0xFF);
760
761 /* IPU_PIX_FMT_RGB565 */
762 ipu_dc_map_clear(3);
763 ipu_dc_map_config(3, 0, 4, 0xF8);
764 ipu_dc_map_config(3, 1, 10, 0xFC);
765 ipu_dc_map_config(3, 2, 15, 0xF8);
766
767 /* IPU_PIX_FMT_LVDS666 */
768 ipu_dc_map_clear(4);
769 ipu_dc_map_config(4, 0, 5, 0xFC);
770 ipu_dc_map_config(4, 1, 13, 0xFC);
771 ipu_dc_map_config(4, 2, 21, 0xFC);
772 }
773
774 static int ipu_pixfmt_to_map(uint32_t fmt)
775 {
776 switch (fmt) {
777 case IPU_PIX_FMT_GENERIC:
778 case IPU_PIX_FMT_RGB24:
779 return 0;
780 case IPU_PIX_FMT_RGB666:
781 return 1;
782 case IPU_PIX_FMT_YUV444:
783 return 2;
784 case IPU_PIX_FMT_RGB565:
785 return 3;
786 case IPU_PIX_FMT_LVDS666:
787 return 4;
788 }
789
790 return -1;
791 }
792
793 /*
794 * This function is called to initialize a synchronous LCD panel.
795 *
796 * @param disp The DI the panel is attached to.
797 *
798 * @param pixel_clk Desired pixel clock frequency in Hz.
799 *
800 * @param pixel_fmt Input parameter for pixel format of buffer.
801 * Pixel format is a FOURCC ASCII code.
802 *
803 * @param width The width of panel in pixels.
804 *
805 * @param height The height of panel in pixels.
806 *
807 * @param hStartWidth The number of pixel clocks between the HSYNC
808 * signal pulse and the start of valid data.
809 *
810 * @param hSyncWidth The width of the HSYNC signal in units of pixel
811 * clocks.
812 *
813 * @param hEndWidth The number of pixel clocks between the end of
814 * valid data and the HSYNC signal for next line.
815 *
816 * @param vStartWidth The number of lines between the VSYNC
817 * signal pulse and the start of valid data.
818 *
819 * @param vSyncWidth The width of the VSYNC signal in units of lines
820 *
821 * @param vEndWidth The number of lines between the end of valid
822 * data and the VSYNC signal for next frame.
823 *
824 * @param sig Bitfield of signal polarities for LCD interface.
825 *
826 * @return This function returns 0 on success or negative error code on
827 * fail.
828 */
829
830 int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
831 uint16_t width, uint16_t height,
832 uint32_t pixel_fmt,
833 uint16_t h_start_width, uint16_t h_sync_width,
834 uint16_t h_end_width, uint16_t v_start_width,
835 uint16_t v_sync_width, uint16_t v_end_width,
836 uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
837 {
838 uint32_t reg;
839 uint32_t di_gen, vsync_cnt;
840 uint32_t div, rounded_pixel_clk;
841 uint32_t h_total, v_total;
842 int map;
843 struct clk *di_parent;
844
845 debug("panel size = %d x %d\n", width, height);
846
847 if ((v_sync_width == 0) || (h_sync_width == 0))
848 return -EINVAL;
849
850 /* adapt panel to ipu restricitions */
851 if (v_end_width < 2) {
852 v_end_width = 2;
853 puts("WARNING: v_end_width (lower_margin) must be >= 2, adjusted\n");
854 }
855
856 h_total = width + h_sync_width + h_start_width + h_end_width;
857 v_total = height + v_sync_width + v_start_width + v_end_width;
858
859 /* Init clocking */
860 debug("pixel clk = %dHz\n", pixel_clk);
861
862 if (sig.ext_clk) {
863 if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/
864 /*
865 * Set the PLL to be an even multiple
866 * of the pixel clock.
867 */
868 if ((clk_get_usecount(g_pixel_clk[0]) == 0) &&
869 (clk_get_usecount(g_pixel_clk[1]) == 0)) {
870 di_parent = clk_get_parent(g_di_clk[disp]);
871 rounded_pixel_clk =
872 clk_round_rate(g_pixel_clk[disp],
873 pixel_clk);
874 div = clk_get_rate(di_parent) /
875 rounded_pixel_clk;
876 if (div % 2)
877 div++;
878 if (clk_get_rate(di_parent) != div *
879 rounded_pixel_clk)
880 clk_set_rate(di_parent,
881 div * rounded_pixel_clk);
882 udelay(10000);
883 clk_set_rate(g_di_clk[disp],
884 2 * rounded_pixel_clk);
885 udelay(10000);
886 }
887 }
888 clk_set_parent(g_pixel_clk[disp], g_ldb_clk);
889 } else {
890 if (clk_get_usecount(g_pixel_clk[disp]) != 0)
891 clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
892 }
893 rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk);
894 clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
895 udelay(5000);
896 /* Get integer portion of divider */
897 div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
898 rounded_pixel_clk;
899
900 ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
901 ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
902
903 map = ipu_pixfmt_to_map(pixel_fmt);
904 if (map < 0) {
905 debug("IPU_DISP: No MAP\n");
906 return -EINVAL;
907 }
908
909 di_gen = __raw_readl(DI_GENERAL(disp));
910
911 if (sig.interlaced) {
912 /* Setup internal HSYNC waveform */
913 ipu_di_sync_config(
914 disp, /* display */
915 1, /* counter */
916 h_total / 2 - 1,/* run count */
917 DI_SYNC_CLK, /* run_resolution */
918 0, /* offset */
919 DI_SYNC_NONE, /* offset resolution */
920 0, /* repeat count */
921 DI_SYNC_NONE, /* CNT_CLR_SEL */
922 0, /* CNT_POLARITY_GEN_EN */
923 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
924 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
925 0, /* COUNT UP */
926 0 /* COUNT DOWN */
927 );
928
929 /* Field 1 VSYNC waveform */
930 ipu_di_sync_config(
931 disp, /* display */
932 2, /* counter */
933 h_total - 1, /* run count */
934 DI_SYNC_CLK, /* run_resolution */
935 0, /* offset */
936 DI_SYNC_NONE, /* offset resolution */
937 0, /* repeat count */
938 DI_SYNC_NONE, /* CNT_CLR_SEL */
939 0, /* CNT_POLARITY_GEN_EN */
940 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
941 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
942 0, /* COUNT UP */
943 4 /* COUNT DOWN */
944 );
945
946 /* Setup internal HSYNC waveform */
947 ipu_di_sync_config(
948 disp, /* display */
949 3, /* counter */
950 v_total * 2 - 1,/* run count */
951 DI_SYNC_INT_HSYNC, /* run_resolution */
952 1, /* offset */
953 DI_SYNC_INT_HSYNC, /* offset resolution */
954 0, /* repeat count */
955 DI_SYNC_NONE, /* CNT_CLR_SEL */
956 0, /* CNT_POLARITY_GEN_EN */
957 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
958 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
959 0, /* COUNT UP */
960 4 /* COUNT DOWN */
961 );
962
963 /* Active Field ? */
964 ipu_di_sync_config(
965 disp, /* display */
966 4, /* counter */
967 v_total / 2 - 1,/* run count */
968 DI_SYNC_HSYNC, /* run_resolution */
969 v_start_width, /* offset */
970 DI_SYNC_HSYNC, /* offset resolution */
971 2, /* repeat count */
972 DI_SYNC_VSYNC, /* CNT_CLR_SEL */
973 0, /* CNT_POLARITY_GEN_EN */
974 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
975 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
976 0, /* COUNT UP */
977 0 /* COUNT DOWN */
978 );
979
980 /* Active Line */
981 ipu_di_sync_config(
982 disp, /* display */
983 5, /* counter */
984 0, /* run count */
985 DI_SYNC_HSYNC, /* run_resolution */
986 0, /* offset */
987 DI_SYNC_NONE, /* offset resolution */
988 height / 2, /* repeat count */
989 4, /* CNT_CLR_SEL */
990 0, /* CNT_POLARITY_GEN_EN */
991 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
992 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
993 0, /* COUNT UP */
994 0 /* COUNT DOWN */
995 );
996
997 /* Field 0 VSYNC waveform */
998 ipu_di_sync_config(
999 disp, /* display */
1000 6, /* counter */
1001 v_total - 1, /* run count */
1002 DI_SYNC_HSYNC, /* run_resolution */
1003 0, /* offset */
1004 DI_SYNC_NONE, /* offset resolution */
1005 0, /* repeat count */
1006 DI_SYNC_NONE, /* CNT_CLR_SEL */
1007 0, /* CNT_POLARITY_GEN_EN */
1008 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1009 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1010 0, /* COUNT UP */
1011 0 /* COUNT DOWN */
1012 );
1013
1014 /* DC VSYNC waveform */
1015 vsync_cnt = 7;
1016 ipu_di_sync_config(
1017 disp, /* display */
1018 7, /* counter */
1019 v_total / 2 - 1,/* run count */
1020 DI_SYNC_HSYNC, /* run_resolution */
1021 9, /* offset */
1022 DI_SYNC_HSYNC, /* offset resolution */
1023 2, /* repeat count */
1024 DI_SYNC_VSYNC, /* CNT_CLR_SEL */
1025 0, /* CNT_POLARITY_GEN_EN */
1026 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1027 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1028 0, /* COUNT UP */
1029 0 /* COUNT DOWN */
1030 );
1031
1032 /* active pixel waveform */
1033 ipu_di_sync_config(
1034 disp, /* display */
1035 8, /* counter */
1036 0, /* run count */
1037 DI_SYNC_CLK, /* run_resolution */
1038 h_start_width, /* offset */
1039 DI_SYNC_CLK, /* offset resolution */
1040 width, /* repeat count */
1041 5, /* CNT_CLR_SEL */
1042 0, /* CNT_POLARITY_GEN_EN */
1043 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1044 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1045 0, /* COUNT UP */
1046 0 /* COUNT DOWN */
1047 );
1048
1049 ipu_di_sync_config(
1050 disp, /* display */
1051 9, /* counter */
1052 v_total - 1, /* run count */
1053 DI_SYNC_INT_HSYNC,/* run_resolution */
1054 v_total / 2, /* offset */
1055 DI_SYNC_INT_HSYNC,/* offset resolution */
1056 0, /* repeat count */
1057 DI_SYNC_HSYNC, /* CNT_CLR_SEL */
1058 0, /* CNT_POLARITY_GEN_EN */
1059 DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
1060 DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
1061 0, /* COUNT UP */
1062 4 /* COUNT DOWN */
1063 );
1064
1065 /* set gentime select and tag sel */
1066 reg = __raw_readl(DI_SW_GEN1(disp, 9));
1067 reg &= 0x1FFFFFFF;
1068 reg |= (3 - 1)<<29 | 0x00008000;
1069 __raw_writel(reg, DI_SW_GEN1(disp, 9));
1070
1071 __raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));
1072
1073 /* set y_sel = 1 */
1074 di_gen |= 0x10000000;
1075 di_gen |= DI_GEN_POLARITY_5;
1076 di_gen |= DI_GEN_POLARITY_8;
1077 } else {
1078 /* Setup internal HSYNC waveform */
1079 ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,
1080 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
1081 0, DI_SYNC_NONE,
1082 DI_SYNC_NONE, 0, 0);
1083
1084 /* Setup external (delayed) HSYNC waveform */
1085 ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1,
1086 DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
1087 0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
1088 DI_SYNC_CLK, 0, h_sync_width * 2);
1089 /* Setup VSYNC waveform */
1090 vsync_cnt = DI_SYNC_VSYNC;
1091 ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1,
1092 DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
1093 DI_SYNC_NONE, 1, DI_SYNC_NONE,
1094 DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
1095 __raw_writel(v_total - 1, DI_SCR_CONF(disp));
1096
1097 /* Setup active data waveform to sync with DC */
1098 ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,
1099 v_sync_width + v_start_width, DI_SYNC_HSYNC,
1100 height,
1101 DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
1102 DI_SYNC_NONE, 0, 0);
1103 ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,
1104 h_sync_width + h_start_width, DI_SYNC_CLK,
1105 width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
1106 0);
1107
1108 /* reset all unused counters */
1109 __raw_writel(0, DI_SW_GEN0(disp, 6));
1110 __raw_writel(0, DI_SW_GEN1(disp, 6));
1111 __raw_writel(0, DI_SW_GEN0(disp, 7));
1112 __raw_writel(0, DI_SW_GEN1(disp, 7));
1113 __raw_writel(0, DI_SW_GEN0(disp, 8));
1114 __raw_writel(0, DI_SW_GEN1(disp, 8));
1115 __raw_writel(0, DI_SW_GEN0(disp, 9));
1116 __raw_writel(0, DI_SW_GEN1(disp, 9));
1117
1118 reg = __raw_readl(DI_STP_REP(disp, 6));
1119 reg &= 0x0000FFFF;
1120 __raw_writel(reg, DI_STP_REP(disp, 6));
1121 __raw_writel(0, DI_STP_REP(disp, 7));
1122 __raw_writel(0, DI_STP_REP(disp, 9));
1123
1124 /* Init template microcode */
1125 if (disp) {
1126 ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1127 ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1128 ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1129 } else {
1130 ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
1131 ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
1132 ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
1133 }
1134
1135 if (sig.Hsync_pol)
1136 di_gen |= DI_GEN_POLARITY_2;
1137 if (sig.Vsync_pol)
1138 di_gen |= DI_GEN_POLARITY_3;
1139
1140 if (!sig.clk_pol)
1141 di_gen |= DI_GEN_POL_CLK;
1142
1143 }
1144
1145 __raw_writel(di_gen, DI_GENERAL(disp));
1146
1147 __raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
1148 0x00000002, DI_SYNC_AS_GEN(disp));
1149
1150 reg = __raw_readl(DI_POL(disp));
1151 reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
1152 if (sig.enable_pol)
1153 reg |= DI_POL_DRDY_POLARITY_15;
1154 if (sig.data_pol)
1155 reg |= DI_POL_DRDY_DATA_POLARITY;
1156 __raw_writel(reg, DI_POL(disp));
1157
1158 __raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
1159
1160 return 0;
1161 }
1162
1163 /*
1164 * This function sets the foreground and background plane global alpha blending
1165 * modes. This function also sets the DP graphic plane according to the
1166 * parameter of IPUv3 DP channel.
1167 *
1168 * @param channel IPUv3 DP channel
1169 *
1170 * @param enable Boolean to enable or disable global alpha
1171 * blending. If disabled, local blending is used.
1172 *
1173 * @param alpha Global alpha value.
1174 *
1175 * @return Returns 0 on success or negative error code on fail
1176 */
1177 int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
1178 uint8_t alpha)
1179 {
1180 uint32_t reg;
1181
1182 unsigned char bg_chan;
1183
1184 if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1185 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1186 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1187 return -EINVAL;
1188
1189 if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
1190 channel == MEM_BG_ASYNC1)
1191 bg_chan = 1;
1192 else
1193 bg_chan = 0;
1194
1195 if (!g_ipu_clk_enabled)
1196 clk_enable(g_ipu_clk);
1197
1198 if (bg_chan) {
1199 reg = __raw_readl(DP_COM_CONF());
1200 __raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF());
1201 } else {
1202 reg = __raw_readl(DP_COM_CONF());
1203 __raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF());
1204 }
1205
1206 if (enable) {
1207 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;
1208 __raw_writel(reg | ((uint32_t) alpha << 24),
1209 DP_GRAPH_WIND_CTRL());
1210
1211 reg = __raw_readl(DP_COM_CONF());
1212 __raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF());
1213 } else {
1214 reg = __raw_readl(DP_COM_CONF());
1215 __raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF());
1216 }
1217
1218 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1219 __raw_writel(reg, IPU_SRM_PRI2);
1220
1221 if (!g_ipu_clk_enabled)
1222 clk_disable(g_ipu_clk);
1223
1224 return 0;
1225 }
1226
1227 /*
1228 * This function sets the transparent color key for SDC graphic plane.
1229 *
1230 * @param channel Input parameter for the logical channel ID.
1231 *
1232 * @param enable Boolean to enable or disable color key
1233 *
1234 * @param colorKey 24-bit RGB color for transparent color key.
1235 *
1236 * @return Returns 0 on success or negative error code on fail
1237 */
1238 int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
1239 uint32_t color_key)
1240 {
1241 uint32_t reg;
1242 int y, u, v;
1243 int red, green, blue;
1244
1245 if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
1246 (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
1247 (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
1248 return -EINVAL;
1249
1250 if (!g_ipu_clk_enabled)
1251 clk_enable(g_ipu_clk);
1252
1253 color_key_4rgb = 1;
1254 /* Transform color key from rgb to yuv if CSC is enabled */
1255 if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
1256 ((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
1257 ((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
1258 ((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {
1259
1260 debug("color key 0x%x need change to yuv fmt\n", color_key);
1261
1262 red = (color_key >> 16) & 0xFF;
1263 green = (color_key >> 8) & 0xFF;
1264 blue = color_key & 0xFF;
1265
1266 y = rgb_to_yuv(0, red, green, blue);
1267 u = rgb_to_yuv(1, red, green, blue);
1268 v = rgb_to_yuv(2, red, green, blue);
1269 color_key = (y << 16) | (u << 8) | v;
1270
1271 color_key_4rgb = 0;
1272
1273 debug("color key change to yuv fmt 0x%x\n", color_key);
1274 }
1275
1276 if (enable) {
1277 reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
1278 __raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
1279
1280 reg = __raw_readl(DP_COM_CONF());
1281 __raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF());
1282 } else {
1283 reg = __raw_readl(DP_COM_CONF());
1284 __raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF());
1285 }
1286
1287 reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
1288 __raw_writel(reg, IPU_SRM_PRI2);
1289
1290 if (!g_ipu_clk_enabled)
1291 clk_disable(g_ipu_clk);
1292
1293 return 0;
1294 }
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