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rockchip: video: mipi: Split mipi driver into common and specific parts
[people/ms/u-boot.git] / drivers / video / rockchip / rk3399_mipi.c
1 /*
2 * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Eric Gao <eric.gao@rock-chips.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <display.h>
11 #include <dm.h>
12 #include <fdtdec.h>
13 #include <panel.h>
14 #include <regmap.h>
15 #include "rk_mipi.h"
16 #include <syscon.h>
17 #include <asm/gpio.h>
18 #include <asm/hardware.h>
19 #include <asm/io.h>
20 #include <dm/uclass-internal.h>
21 #include <linux/kernel.h>
22 #include <asm/arch/clock.h>
23 #include <asm/arch/cru_rk3399.h>
24 #include <asm/arch/grf_rk3399.h>
25 #include <asm/arch/rockchip_mipi_dsi.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 /* Select mipi dsi source, big or little vop */
30 static int rk_mipi_dsi_source_select(struct udevice *dev)
31 {
32 struct rk_mipi_priv *priv = dev_get_priv(dev);
33 struct rk3399_grf_regs *grf = priv->grf;
34 struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
35
36 /* Select the video source */
37 switch (disp_uc_plat->source_id) {
38 case VOP_B:
39 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
40 GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);
41 break;
42 case VOP_L:
43 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
44 GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);
45 break;
46 default:
47 debug("%s: Invalid VOP id\n", __func__);
48 return -EINVAL;
49 }
50
51 return 0;
52 }
53
54 /* Setup mipi dphy working mode */
55 static void rk_mipi_dphy_mode_set(struct udevice *dev)
56 {
57 struct rk_mipi_priv *priv = dev_get_priv(dev);
58 struct rk3399_grf_regs *grf = priv->grf;
59 int val;
60
61 /* Set Controller as TX mode */
62 val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;
63 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);
64
65 /* Exit tx stop mode */
66 val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;
67 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);
68
69 /* Disable turnequest */
70 val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;
71 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);
72 }
73
74 /*
75 * This function is called by rk_display_init() using rk_mipi_dsi_enable() and
76 * rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
77 * enable backlight.
78 */
79 static int rk_display_enable(struct udevice *dev, int panel_bpp,
80 const struct display_timing *timing)
81 {
82 int ret;
83 struct rk_mipi_priv *priv = dev_get_priv(dev);
84
85 /* Fill the mipi controller parameter */
86 priv->ref_clk = 24 * MHz;
87 priv->sys_clk = priv->ref_clk;
88 priv->pix_clk = timing->pixelclock.typ;
89 priv->phy_clk = priv->pix_clk * 6;
90 priv->txbyte_clk = priv->phy_clk / 8;
91 priv->txesc_clk = 20 * MHz;
92
93 /* Select vop port, big or little */
94 rk_mipi_dsi_source_select(dev);
95
96 /* Set mipi dphy work mode */
97 rk_mipi_dphy_mode_set(dev);
98
99 /* Config and enable mipi dsi according to timing */
100 ret = rk_mipi_dsi_enable(dev, timing);
101 if (ret) {
102 debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
103 __func__, ret);
104 return ret;
105 }
106
107 /* Config and enable mipi phy */
108 ret = rk_mipi_phy_enable(dev);
109 if (ret) {
110 debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
111 __func__, ret);
112 return ret;
113 }
114
115 /* Enable backlight */
116 ret = panel_enable_backlight(priv->panel);
117 if (ret) {
118 debug("%s: panel_enable_backlight() failed (err=%d)\n",
119 __func__, ret);
120 return ret;
121 }
122
123 return 0;
124 }
125
126 static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
127 {
128 struct rk_mipi_priv *priv = dev_get_priv(dev);
129
130 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
131 if (priv->grf <= 0) {
132 debug("%s: Get syscon grf failed (ret=%p)\n",
133 __func__, priv->grf);
134 return -ENXIO;
135 }
136 priv->regs = dev_read_addr(dev);
137 if (priv->regs == FDT_ADDR_T_NONE) {
138 debug("%s: Get MIPI dsi address failed\n", __func__);
139 return -ENXIO;
140 }
141
142 return 0;
143 }
144
145 /*
146 * Probe function: check panel existence and readingit's timing. Then config
147 * mipi dsi controller and enable it according to the timing parameter.
148 */
149 static int rk_mipi_probe(struct udevice *dev)
150 {
151 int ret;
152 struct rk_mipi_priv *priv = dev_get_priv(dev);
153
154 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
155 &priv->panel);
156 if (ret) {
157 debug("%s: Can not find panel (err=%d)\n", __func__, ret);
158 return ret;
159 }
160
161 return 0;
162 }
163
164 static const struct dm_display_ops rk_mipi_dsi_ops = {
165 .read_timing = rk_mipi_read_timing,
166 .enable = rk_display_enable,
167 };
168
169 static const struct udevice_id rk_mipi_dsi_ids[] = {
170 { .compatible = "rockchip,rk3399_mipi_dsi" },
171 { }
172 };
173
174 U_BOOT_DRIVER(rk_mipi_dsi) = {
175 .name = "rk_mipi_dsi",
176 .id = UCLASS_DISPLAY,
177 .of_match = rk_mipi_dsi_ids,
178 .ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
179 .probe = rk_mipi_probe,
180 .ops = &rk_mipi_dsi_ops,
181 .priv_auto_alloc_size = sizeof(struct rk_mipi_priv),
182 };