2 * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
6 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/hardware.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/hardware.h>
23 #include "rk_vop.h" /* for rk_vop_probe_regulators */
25 static const struct hdmi_phy_config rockchip_phy_config
[] = {
27 .mpixelclock
= 74250000,
28 .sym_ctr
= 0x8009, .term
= 0x0004, .vlev_ctr
= 0x0272,
30 .mpixelclock
= 148500000,
31 .sym_ctr
= 0x802b, .term
= 0x0004, .vlev_ctr
= 0x028d,
33 .mpixelclock
= 297000000,
34 .sym_ctr
= 0x8039, .term
= 0x0005, .vlev_ctr
= 0x028d,
36 .mpixelclock
= 584000000,
37 .sym_ctr
= 0x8039, .term
= 0x0000, .vlev_ctr
= 0x019d,
40 .sym_ctr
= 0x0000, .term
= 0x0000, .vlev_ctr
= 0x0000,
44 static const struct hdmi_mpll_config rockchip_mpll_cfg
[] = {
46 .mpixelclock
= 40000000,
47 .cpce
= 0x00b3, .gmp
= 0x0000, .curr
= 0x0018,
49 .mpixelclock
= 65000000,
50 .cpce
= 0x0072, .gmp
= 0x0001, .curr
= 0x0028,
52 .mpixelclock
= 66000000,
53 .cpce
= 0x013e, .gmp
= 0x0003, .curr
= 0x0038,
55 .mpixelclock
= 83500000,
56 .cpce
= 0x0072, .gmp
= 0x0001, .curr
= 0x0028,
58 .mpixelclock
= 146250000,
59 .cpce
= 0x0051, .gmp
= 0x0002, .curr
= 0x0038,
61 .mpixelclock
= 148500000,
62 .cpce
= 0x0051, .gmp
= 0x0003, .curr
= 0x0000,
64 .mpixelclock
= 272000000,
65 .cpce
= 0x0040, .gmp
= 0x0003, .curr
= 0x0000,
67 .mpixelclock
= 340000000,
68 .cpce
= 0x0040, .gmp
= 0x0003, .curr
= 0x0000,
71 .cpce
= 0x0051, .gmp
= 0x0003, .curr
= 0x0000,
75 int rk_hdmi_read_edid(struct udevice
*dev
, u8
*buf
, int buf_size
)
77 struct rk_hdmi_priv
*priv
= dev_get_priv(dev
);
79 return dw_hdmi_read_edid(&priv
->hdmi
, buf
, buf_size
);
82 int rk_hdmi_ofdata_to_platdata(struct udevice
*dev
)
84 struct rk_hdmi_priv
*priv
= dev_get_priv(dev
);
85 struct dw_hdmi
*hdmi
= &priv
->hdmi
;
87 hdmi
->ioaddr
= (ulong
)devfdt_get_addr(dev
);
88 hdmi
->mpll_cfg
= rockchip_mpll_cfg
;
89 hdmi
->phy_cfg
= rockchip_phy_config
;
91 /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
93 hdmi
->reg_io_width
= 4;
94 hdmi
->phy_set
= dw_hdmi_phy_cfg
;
96 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
101 void rk_hdmi_probe_regulators(struct udevice
*dev
,
102 const char * const *names
, int cnt
)
104 rk_vop_probe_regulators(dev
, names
, cnt
);
107 int rk_hdmi_probe(struct udevice
*dev
)
109 struct rk_hdmi_priv
*priv
= dev_get_priv(dev
);
110 struct dw_hdmi
*hdmi
= &priv
->hdmi
;
113 ret
= dw_hdmi_phy_wait_for_hpd(hdmi
);
115 debug("hdmi can not get hpd signal\n");
120 dw_hdmi_phy_init(hdmi
);