drivers/video/rockchip/rk_mipi.c

   1 /*
   2  * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Eric Gao <eric.gao@rock-chips.com>
   4  *
   5  * SPDX-License-Identifier: GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <display.h>
  11 #include <dm.h>
  12 #include <fdtdec.h>
  13 #include <panel.h>
  14 #include <regmap.h>
  15 #include "rk_mipi.h"
  16 #include <syscon.h>
  17 #include <asm/gpio.h>
  18 #include <asm/hardware.h>
  19 #include <asm/io.h>
  20 #include <dm/uclass-internal.h>
  21 #include <linux/kernel.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/arch/cru_rk3399.h>
  24 #include <asm/arch/grf_rk3399.h>
  25 #include <asm/arch/rockchip_mipi_dsi.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int rk_mipi_read_timing(struct udevice *dev,
  30                         struct display_timing *timing)
  31 {
  32         int ret;
  33
  34         ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
  35                                          0, timing);
  36         if (ret) {
  37                 debug("%s: Failed to decode display timing (ret=%d)\n",
  38                       __func__, ret);
  39                 return -EINVAL;
  40         }
  41
  42         return 0;
  43 }
  44
  45 /*
  46  * Register write function used only for mipi dsi controller.
  47  * Parameter:
  48  *  @regs: mipi controller address
  49  *  @reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you can
  50  *        use define in rk_mipi.h directly for this parameter
  51  *  @val: value that will be write to specified bits of register
  52  */
  53 static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val)
  54 {
  55         u32 dat;
  56         u32 mask;
  57         u32 offset = (reg >> OFFSET_SHIFT) & 0xff;
  58         u32 bits = (reg >> BITS_SHIFT) & 0xff;
  59         uintptr_t addr = (reg >> ADDR_SHIFT) + regs;
  60
  61         /* Mask for specifiled bits,the corresponding bits will be clear */
  62         mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits)));
  63
  64         /* Make sure val in the available range */
  65         val &= ~(0xffffffff << bits);
  66
  67         /* Get register's original val */
  68         dat = readl(addr);
  69
  70         /* Clear specified bits */
  71         dat &= mask;
  72
  73         /* Fill specified bits */
  74         dat |= val << offset;
  75
  76         writel(dat, addr);
  77 }
  78
  79 int rk_mipi_dsi_enable(struct udevice *dev,
  80                        const struct display_timing *timing)
  81 {
  82         int node, timing_node;
  83         int val;
  84         struct rk_mipi_priv *priv = dev_get_priv(dev);
  85         uintptr_t regs = priv->regs;
  86         u32 txbyte_clk = priv->txbyte_clk;
  87         u32 txesc_clk = priv->txesc_clk;
  88
  89         txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);
  90
  91         /* Set Display timing parameter */
  92         rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
  93         rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
  94         rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ
  95                           + timing->hback_porch.typ + timing->hactive.typ
  96                           + timing->hfront_porch.typ));
  97         rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ);
  98         rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ);
  99         rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ);
 100         rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ);
 101
 102         /* Set Signal Polarity */
 103         val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;
 104         rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val);
 105
 106         val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;
 107         rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val);
 108
 109         val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;
 110         rk_mipi_dsi_write(regs, DISPLAY_FLAGS_DE_LOW, val);
 111
 112         val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;
 113         rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val);
 114
 115         /* Set video mode */
 116         rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE);
 117
 118         /* Set video mode transmission type as burst mode */
 119         rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE);
 120
 121         /* Set pix num in a video package */
 122         rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
 123
 124         /* Set dpi color coding depth 24 bit */
 125         timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
 126                                                                          "display-timings");
 127         node = fdt_first_subnode(gd->fdt_blob, timing_node);
 128         val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
 129         switch (val) {
 130         case 16:
 131                 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1);
 132                 break;
 133         case 24:
 134                 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
 135                 break;
 136         case 30:
 137                 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT);
 138                 break;
 139         default:
 140                 rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
 141         }
 142         /* Enable low power mode */
 143         rk_mipi_dsi_write(regs, LP_CMD_EN, 1);
 144         rk_mipi_dsi_write(regs, LP_HFP_EN, 1);
 145         rk_mipi_dsi_write(regs, LP_VACT_EN, 1);
 146         rk_mipi_dsi_write(regs, LP_VFP_EN, 1);
 147         rk_mipi_dsi_write(regs, LP_VBP_EN, 1);
 148         rk_mipi_dsi_write(regs, LP_VSA_EN, 1);
 149
 150         /* Division for timeout counter clk */
 151         rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a);
 152
 153         /* Tx esc clk division from txbyte clk */
 154         rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk);
 155
 156         /* Timeout count for hs<->lp transation between Line period */
 157         rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8);
 158
 159         /* Phy State transfer timing */
 160         rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32);
 161         rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1);
 162         rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14);
 163         rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10);
 164         rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710);
 165
 166         /* Power on */
 167         rk_mipi_dsi_write(regs, SHUTDOWNZ, 1);
 168
 169         return 0;
 170 }
 171
 172 /* rk mipi dphy write function. It is used to write test data to dphy */
 173 static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code,
 174                               unsigned char *test_data, unsigned char size)
 175 {
 176         int i = 0;
 177
 178         /* Write Test code */
 179         rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
 180         rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code);
 181         rk_mipi_dsi_write(regs, PHY_TESTEN, 1);
 182         rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
 183         rk_mipi_dsi_write(regs, PHY_TESTEN, 0);
 184
 185         /* Write Test data */
 186         for (i = 0; i < size; i++) {
 187                 rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
 188                 rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]);
 189                 rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
 190         }
 191 }
 192
 193 /*
 194  * Mipi dphy config function. Calculate the suitable prediv, feedback div,
 195  * fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate,
 196  * and then enable phy.
 197  */
 198 int rk_mipi_phy_enable(struct udevice *dev)
 199 {
 200         int i;
 201         struct rk_mipi_priv *priv = dev_get_priv(dev);
 202         uintptr_t regs = priv->regs;
 203         u64 fbdiv;
 204         u64 prediv = 1;
 205         u32 max_fbdiv = 512;
 206         u32 max_prediv, min_prediv;
 207         u64 ddr_clk = priv->phy_clk;
 208         u32 refclk = priv->ref_clk;
 209         u32 remain = refclk;
 210         unsigned char test_data[2] = {0};
 211
 212         int freq_rang[][2] = {
 213                 {90, 0x01},   {100, 0x10},  {110, 0x20},  {130, 0x01},
 214                 {140, 0x11},  {150, 0x21},  {170, 0x02},  {180, 0x12},
 215                 {200, 0x22},  {220, 0x03},  {240, 0x13},  {250, 0x23},
 216                 {270, 0x04},  {300, 0x14},  {330, 0x05},  {360, 0x15},
 217                 {400, 0x25},  {450, 0x06},  {500, 0x16},  {550, 0x07},
 218                 {600, 0x17},  {650, 0x08},  {700, 0x18},  {750, 0x09},
 219                 {800, 0x19},  {850, 0x29},  {900, 0x39},  {950, 0x0a},
 220                 {1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
 221                 {1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
 222                 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
 223         };
 224
 225         /* Shutdown mode */
 226         rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0);
 227         rk_mipi_dsi_write(regs, PHY_RSTZ, 0);
 228         rk_mipi_dsi_write(regs, PHY_TESTCLR, 1);
 229
 230         /* Pll locking */
 231         rk_mipi_dsi_write(regs, PHY_TESTCLR, 0);
 232
 233         /* config cp and lfp */
 234         test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3;
 235         rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1);
 236
 237         test_data[0] = 0x8;
 238         rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1);
 239
 240         test_data[0] = 0x80 | 0x40;
 241         rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1);
 242
 243         /* select the suitable value for fsfreqrang reg */
 244         for (i = 0; i < ARRAY_SIZE(freq_rang); i++) {
 245                 if (ddr_clk / (MHz) >= freq_rang[i][0])
 246                         break;
 247         }
 248         if (i == ARRAY_SIZE(freq_rang)) {
 249                 debug("%s: Dphy freq out of range!\n", __func__);
 250                 return -EINVAL;
 251         }
 252         test_data[0] = freq_rang[i][1] << 1;
 253         rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1);
 254
 255         /*
 256          * Calculate the best ddrclk and it's corresponding div value. If the
 257          * given pixelclock is great than 250M, ddrclk will be fix 1500M.
 258          * Otherwise,
 259          * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
 260          * according to spec.
 261          */
 262         max_prediv = (refclk / (5 * MHz));
 263         min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);
 264
 265         debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__, max_prediv,
 266               min_prediv);
 267
 268         if (max_prediv < min_prediv) {
 269                 debug("%s: Invalid refclk value\n", __func__);
 270                 return -EINVAL;
 271         }
 272
 273         /* Calculate the best refclk and feedback division value for dphy pll */
 274         for (i = min_prediv; i < max_prediv; i++) {
 275                 if ((ddr_clk * i % refclk < remain) &&
 276                     (ddr_clk * i / refclk) < max_fbdiv) {
 277                         prediv = i;
 278                         remain = ddr_clk * i % refclk;
 279                 }
 280         }
 281         fbdiv = ddr_clk * prediv / refclk;
 282         ddr_clk = refclk * fbdiv / prediv;
 283         priv->phy_clk = ddr_clk;
 284
 285         debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n",
 286               __func__, refclk, prediv, fbdiv, ddr_clk);
 287
 288         /* config prediv and feedback reg */
 289         test_data[0] = prediv - 1;
 290         rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1);
 291         test_data[0] = (fbdiv - 1) & 0x1f;
 292         rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
 293         test_data[0] = (fbdiv - 1) >> 5 | 0x80;
 294         rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
 295         test_data[0] = 0x30;
 296         rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1);
 297
 298         /* rest config */
 299         test_data[0] = 0x4d;
 300         rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1);
 301
 302         test_data[0] = 0x3d;
 303         rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
 304
 305         test_data[0] = 0xdf;
 306         rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
 307
 308         test_data[0] =  0x7;
 309         rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
 310
 311         test_data[0] = 0x80 | 0x7;
 312         rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
 313
 314         test_data[0] = 0x80 | 15;
 315         rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME,
 316                           test_data, 1);
 317         test_data[0] = 0x80 | 85;
 318         rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME,
 319                           test_data, 1);
 320         test_data[0] = 0x40 | 10;
 321         rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME,
 322                           test_data, 1);
 323
 324         /* enter into stop mode */
 325         rk_mipi_dsi_write(regs, N_LANES, 0x03);
 326         rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1);
 327         rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1);
 328         rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1);
 329         rk_mipi_dsi_write(regs, PHY_RSTZ, 1);
 330
 331         return 0;
 332 }
 333