drivers/video/stm32/stm32_ltdc.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2017
   3  *
   4  * Authors: Philippe Cornu <philippe.cornu@st.com>
   5  *          Yannick Fertre <yannick.fertre@st.com>
   6  *
   7  * SPDX-License-Identifier: GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <clk.h>
  12 #include <dm.h>
  13 #include <panel.h>
  14 #include <video.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/gpio.h>
  17 #include <dm/device-internal.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 struct stm32_ltdc_priv {
  22         void __iomem *regs;
  23         struct display_timing timing;
  24         enum video_log2_bpp l2bpp;
  25         u32 bg_col_argb;
  26         u32 crop_x, crop_y, crop_w, crop_h;
  27         u32 alpha;
  28 };
  29
  30 /* LTDC main registers */
  31 #define LTDC_IDR        0x00    /* IDentification */
  32 #define LTDC_LCR        0x04    /* Layer Count */
  33 #define LTDC_SSCR       0x08    /* Synchronization Size Configuration */
  34 #define LTDC_BPCR       0x0C    /* Back Porch Configuration */
  35 #define LTDC_AWCR       0x10    /* Active Width Configuration */
  36 #define LTDC_TWCR       0x14    /* Total Width Configuration */
  37 #define LTDC_GCR        0x18    /* Global Control */
  38 #define LTDC_GC1R       0x1C    /* Global Configuration 1 */
  39 #define LTDC_GC2R       0x20    /* Global Configuration 2 */
  40 #define LTDC_SRCR       0x24    /* Shadow Reload Configuration */
  41 #define LTDC_GACR       0x28    /* GAmma Correction */
  42 #define LTDC_BCCR       0x2C    /* Background Color Configuration */
  43 #define LTDC_IER        0x34    /* Interrupt Enable */
  44 #define LTDC_ISR        0x38    /* Interrupt Status */
  45 #define LTDC_ICR        0x3C    /* Interrupt Clear */
  46 #define LTDC_LIPCR      0x40    /* Line Interrupt Position Conf. */
  47 #define LTDC_CPSR       0x44    /* Current Position Status */
  48 #define LTDC_CDSR       0x48    /* Current Display Status */
  49
  50 /* LTDC layer 1 registers */
  51 #define LTDC_L1LC1R     0x80    /* L1 Layer Configuration 1 */
  52 #define LTDC_L1LC2R     0x84    /* L1 Layer Configuration 2 */
  53 #define LTDC_L1CR       0x84    /* L1 Control */
  54 #define LTDC_L1WHPCR    0x88    /* L1 Window Hor Position Config */
  55 #define LTDC_L1WVPCR    0x8C    /* L1 Window Vert Position Config */
  56 #define LTDC_L1CKCR     0x90    /* L1 Color Keying Configuration */
  57 #define LTDC_L1PFCR     0x94    /* L1 Pixel Format Configuration */
  58 #define LTDC_L1CACR     0x98    /* L1 Constant Alpha Config */
  59 #define LTDC_L1DCCR     0x9C    /* L1 Default Color Configuration */
  60 #define LTDC_L1BFCR     0xA0    /* L1 Blend Factors Configuration */
  61 #define LTDC_L1FBBCR    0xA4    /* L1 FrameBuffer Bus Control */
  62 #define LTDC_L1AFBCR    0xA8    /* L1 AuxFB Control */
  63 #define LTDC_L1CFBAR    0xAC    /* L1 Color FrameBuffer Address */
  64 #define LTDC_L1CFBLR    0xB0    /* L1 Color FrameBuffer Length */
  65 #define LTDC_L1CFBLNR   0xB4    /* L1 Color FrameBuffer Line Nb */
  66 #define LTDC_L1AFBAR    0xB8    /* L1 AuxFB Address */
  67 #define LTDC_L1AFBLR    0xBC    /* L1 AuxFB Length */
  68 #define LTDC_L1AFBLNR   0xC0    /* L1 AuxFB Line Number */
  69 #define LTDC_L1CLUTWR   0xC4    /* L1 CLUT Write */
  70
  71 /* Bit definitions */
  72 #define SSCR_VSH        GENMASK(10, 0)  /* Vertical Synchronization Height */
  73 #define SSCR_HSW        GENMASK(27, 16) /* Horizontal Synchronization Width */
  74
  75 #define BPCR_AVBP       GENMASK(10, 0)  /* Accumulated Vertical Back Porch */
  76 #define BPCR_AHBP       GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
  77
  78 #define AWCR_AAH        GENMASK(10, 0)  /* Accumulated Active Height */
  79 #define AWCR_AAW        GENMASK(27, 16) /* Accumulated Active Width */
  80
  81 #define TWCR_TOTALH     GENMASK(10, 0)  /* TOTAL Height */
  82 #define TWCR_TOTALW     GENMASK(27, 16) /* TOTAL Width */
  83
  84 #define GCR_LTDCEN      BIT(0)          /* LTDC ENable */
  85 #define GCR_DEN         BIT(16)         /* Dither ENable */
  86 #define GCR_PCPOL       BIT(28)         /* Pixel Clock POLarity-Inverted */
  87 #define GCR_DEPOL       BIT(29)         /* Data Enable POLarity-High */
  88 #define GCR_VSPOL       BIT(30)         /* Vertical Synchro POLarity-High */
  89 #define GCR_HSPOL       BIT(31)         /* Horizontal Synchro POLarity-High */
  90
  91 #define GC1R_WBCH       GENMASK(3, 0)   /* Width of Blue CHannel output */
  92 #define GC1R_WGCH       GENMASK(7, 4)   /* Width of Green Channel output */
  93 #define GC1R_WRCH       GENMASK(11, 8)  /* Width of Red Channel output */
  94 #define GC1R_PBEN       BIT(12)         /* Precise Blending ENable */
  95 #define GC1R_DT         GENMASK(15, 14) /* Dithering Technique */
  96 #define GC1R_GCT        GENMASK(19, 17) /* Gamma Correction Technique */
  97 #define GC1R_SHREN      BIT(21)         /* SHadow Registers ENabled */
  98 #define GC1R_BCP        BIT(22)         /* Background Colour Programmable */
  99 #define GC1R_BBEN       BIT(23)         /* Background Blending ENabled */
 100 #define GC1R_LNIP       BIT(24)         /* Line Number IRQ Position */
 101 #define GC1R_TP         BIT(25)         /* Timing Programmable */
 102 #define GC1R_IPP        BIT(26)         /* IRQ Polarity Programmable */
 103 #define GC1R_SPP        BIT(27)         /* Sync Polarity Programmable */
 104 #define GC1R_DWP        BIT(28)         /* Dither Width Programmable */
 105 #define GC1R_STREN      BIT(29)         /* STatus Registers ENabled */
 106 #define GC1R_BMEN       BIT(31)         /* Blind Mode ENabled */
 107
 108 #define GC2R_EDCA       BIT(0)          /* External Display Control Ability  */
 109 #define GC2R_STSAEN     BIT(1)          /* Slave Timing Sync Ability ENabled */
 110 #define GC2R_DVAEN      BIT(2)          /* Dual-View Ability ENabled */
 111 #define GC2R_DPAEN      BIT(3)          /* Dual-Port Ability ENabled */
 112 #define GC2R_BW         GENMASK(6, 4)   /* Bus Width (log2 of nb of bytes) */
 113 #define GC2R_EDCEN      BIT(7)          /* External Display Control ENabled */
 114
 115 #define SRCR_IMR        BIT(0)          /* IMmediate Reload */
 116 #define SRCR_VBR        BIT(1)          /* Vertical Blanking Reload */
 117
 118 #define LXCR_LEN        BIT(0)          /* Layer ENable */
 119 #define LXCR_COLKEN     BIT(1)          /* Color Keying Enable */
 120 #define LXCR_CLUTEN     BIT(4)          /* Color Look-Up Table ENable */
 121
 122 #define LXWHPCR_WHSTPOS GENMASK(11, 0)  /* Window Horizontal StarT POSition */
 123 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
 124
 125 #define LXWVPCR_WVSTPOS GENMASK(10, 0)  /* Window Vertical StarT POSition */
 126 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
 127
 128 #define LXPFCR_PF       GENMASK(2, 0)   /* Pixel Format */
 129
 130 #define LXCACR_CONSTA   GENMASK(7, 0)   /* CONSTant Alpha */
 131
 132 #define LXBFCR_BF2      GENMASK(2, 0)   /* Blending Factor 2 */
 133 #define LXBFCR_BF1      GENMASK(10, 8)  /* Blending Factor 1 */
 134
 135 #define LXCFBLR_CFBLL   GENMASK(12, 0)  /* Color Frame Buffer Line Length */
 136 #define LXCFBLR_CFBP    GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
 137
 138 #define LXCFBLNR_CFBLN  GENMASK(10, 0)  /* Color Frame Buffer Line Number */
 139
 140 #define BF1_PAXCA       0x600           /* Pixel Alpha x Constant Alpha */
 141 #define BF2_1PAXCA      0x007           /* 1 - (Pixel Alpha x Constant Alpha) */
 142
 143 enum stm32_ltdc_pix_fmt {
 144         PF_ARGB8888 = 0,
 145         PF_RGB888,
 146         PF_RGB565,
 147         PF_ARGB1555,
 148         PF_ARGB4444,
 149         PF_L8,
 150         PF_AL44,
 151         PF_AL88
 152 };
 153
 154 /* TODO add more color format support */
 155 static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
 156 {
 157         enum stm32_ltdc_pix_fmt pf;
 158
 159         switch (l2bpp) {
 160         case VIDEO_BPP16:
 161                 pf = PF_RGB565;
 162                 break;
 163
 164         case VIDEO_BPP1:
 165         case VIDEO_BPP2:
 166         case VIDEO_BPP4:
 167         case VIDEO_BPP8:
 168         case VIDEO_BPP32:
 169         default:
 170                 debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
 171                       __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
 172                 pf = PF_RGB565;
 173                 break;
 174         }
 175
 176         debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
 177
 178         return (u32)pf;
 179 }
 180
 181 static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
 182 {
 183         /* Reload configuration immediately & enable LTDC */
 184         setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR);
 185         setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
 186 }
 187
 188 static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
 189 {
 190         void __iomem *regs = priv->regs;
 191         struct display_timing *timing = &priv->timing;
 192         u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
 193         u32 total_w, total_h;
 194         u32 val;
 195
 196         /* Convert video timings to ltdc timings */
 197         hsync = timing->hsync_len.typ - 1;
 198         vsync = timing->vsync_len.typ - 1;
 199         acc_hbp = hsync + timing->hback_porch.typ;
 200         acc_vbp = vsync + timing->vback_porch.typ;
 201         acc_act_w = acc_hbp + timing->hactive.typ;
 202         acc_act_h = acc_vbp + timing->vactive.typ;
 203         total_w = acc_act_w + timing->hfront_porch.typ;
 204         total_h = acc_act_h + timing->vfront_porch.typ;
 205
 206         /* Synchronization sizes */
 207         val = (hsync << 16) | vsync;
 208         clrsetbits_le32(regs + LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
 209
 210         /* Accumulated back porch */
 211         val = (acc_hbp << 16) | acc_vbp;
 212         clrsetbits_le32(regs + LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
 213
 214         /* Accumulated active width */
 215         val = (acc_act_w << 16) | acc_act_h;
 216         clrsetbits_le32(regs + LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
 217
 218         /* Total width & height */
 219         val = (total_w << 16) | total_h;
 220         clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
 221
 222         /* Signal polarities */
 223         val = 0;
 224         debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
 225         if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)
 226                 val |= GCR_HSPOL;
 227         if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
 228                 val |= GCR_VSPOL;
 229         if (timing->flags & DISPLAY_FLAGS_DE_HIGH)
 230                 val |= GCR_DEPOL;
 231         if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 232                 val |= GCR_PCPOL;
 233         clrsetbits_le32(regs + LTDC_GCR,
 234                         GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
 235
 236         /* Overall background color */
 237         writel(priv->bg_col_argb, priv->regs + LTDC_BCCR);
 238 }
 239
 240 static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
 241 {
 242         void __iomem *regs = priv->regs;
 243         u32 x0, x1, y0, y1;
 244         u32 pitch_in_bytes;
 245         u32 line_length;
 246         u32 bus_width;
 247         u32 val, tmp, bpp;
 248
 249         x0 = priv->crop_x;
 250         x1 = priv->crop_x + priv->crop_w - 1;
 251         y0 = priv->crop_y;
 252         y1 = priv->crop_y + priv->crop_h - 1;
 253
 254         /* Horizontal start and stop position */
 255         tmp = (readl(regs + LTDC_BPCR) & BPCR_AHBP) >> 16;
 256         val = ((x1 + 1 + tmp) << 16) + (x0 + 1 + tmp);
 257         clrsetbits_le32(regs + LTDC_L1WHPCR, LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS,
 258                         val);
 259
 260         /* Vertical start & stop position */
 261         tmp = readl(regs + LTDC_BPCR) & BPCR_AVBP;
 262         val = ((y1 + 1 + tmp) << 16) + (y0 + 1 + tmp);
 263         clrsetbits_le32(regs + LTDC_L1WVPCR, LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS,
 264                         val);
 265
 266         /* Layer background color */
 267         writel(priv->bg_col_argb, regs + LTDC_L1DCCR);
 268
 269         /* Color frame buffer pitch in bytes & line length */
 270         bpp = VNBITS(priv->l2bpp);
 271         pitch_in_bytes = priv->crop_w * (bpp >> 3);
 272         bus_width = 8 << ((readl(regs + LTDC_GC2R) & GC2R_BW) >> 4);
 273         line_length = ((bpp >> 3) * priv->crop_w) + (bus_width >> 3) - 1;
 274         val = (pitch_in_bytes << 16) | line_length;
 275         clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
 276
 277         /* Pixel format */
 278         val = stm32_ltdc_get_pixel_format(priv->l2bpp);
 279         clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
 280
 281         /* Constant alpha value */
 282         clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
 283
 284         /* Blending factors */
 285         clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1,
 286                         BF1_PAXCA | BF2_1PAXCA);
 287
 288         /* Frame buffer line number */
 289         clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
 290
 291         /* Frame buffer address */
 292         writel(fb_addr, regs + LTDC_L1CFBAR);
 293
 294         /* Enable layer 1 */
 295         setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
 296 }
 297
 298 static int stm32_ltdc_probe(struct udevice *dev)
 299 {
 300         struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 301         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 302         struct stm32_ltdc_priv *priv = dev_get_priv(dev);
 303         struct udevice *panel;
 304         struct clk pclk, pxclk;
 305         int ret;
 306
 307         priv->regs = (void *)dev_read_addr(dev);
 308         if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
 309                 debug("%s: ltdc dt register address error\n", __func__);
 310                 return -EINVAL;
 311         }
 312
 313         ret = uclass_first_device(UCLASS_PANEL, &panel);
 314         if (ret) {
 315                 debug("%s: panel device error %d\n", __func__, ret);
 316                 return ret;
 317         }
 318
 319         ret = panel_enable_backlight(panel);
 320         if (ret) {
 321                 debug("%s: panel %s enable backlight error %d\n",
 322                       __func__, panel->name, ret);
 323                 return ret;
 324         }
 325
 326         ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
 327                                            0, &priv->timing);
 328         if (ret) {
 329                 debug("%s: decode display timing error %d\n", __func__, ret);
 330                 return -EINVAL;
 331         }
 332
 333         ret = clk_get_by_name(dev, "pclk", &pclk);
 334         if (ret) {
 335                 debug("%s: peripheral clock get error %d\n", __func__, ret);
 336                 return ret;
 337         }
 338
 339         ret = clk_enable(&pclk);
 340         if (ret) {
 341                 debug("%s: peripheral clock enable error %d\n", __func__, ret);
 342                 return ret;
 343         }
 344
 345         /* Verify pixel clock value if any & inform user accordingly */
 346         ret = clk_get_by_name(dev, "pxclk", &pxclk);
 347         if (!ret) {
 348                 if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ)
 349                         printf("Warning: please adjust ltdc pixel clock\n");
 350         }
 351
 352         /* TODO Below parameters are hard-coded for the moment... */
 353         priv->l2bpp = VIDEO_BPP16;
 354         priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
 355         priv->crop_x = 0;
 356         priv->crop_y = 0;
 357         priv->crop_w = priv->timing.hactive.typ;
 358         priv->crop_h = priv->timing.vactive.typ;
 359         priv->alpha = 0xFF;
 360
 361         debug("%s: %dx%d %dbpp frame buffer at 0x%lx\n", __func__,
 362               priv->timing.hactive.typ, priv->timing.vactive.typ,
 363               VNBITS(priv->l2bpp), uc_plat->base);
 364         debug("%s: crop %d,%d %dx%d bg 0x%08x alpha %d\n", __func__,
 365               priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
 366               priv->bg_col_argb, priv->alpha);
 367
 368         /* Configure & start LTDC */
 369         stm32_ltdc_set_mode(priv);
 370         stm32_ltdc_set_layer1(priv, uc_plat->base);
 371         stm32_ltdc_enable(priv);
 372
 373         uc_priv->xsize = priv->timing.hactive.typ;
 374         uc_priv->ysize = priv->timing.vactive.typ;
 375         uc_priv->bpix = priv->l2bpp;
 376
 377         video_set_flush_dcache(dev, true);
 378
 379         return 0;
 380 }
 381
 382 static int stm32_ltdc_bind(struct udevice *dev)
 383 {
 384         struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 385
 386         uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
 387                         CONFIG_VIDEO_STM32_MAX_YRES *
 388                         (CONFIG_VIDEO_STM32_MAX_BPP >> 3);
 389         debug("%s: frame buffer max size %d bytes\n", __func__, uc_plat->size);
 390
 391         return 0;
 392 }
 393
 394 static const struct udevice_id stm32_ltdc_ids[] = {
 395         { .compatible = "st,stm32-ltdc" },
 396         { }
 397 };
 398
 399 U_BOOT_DRIVER(stm32_ltdc) = {
 400         .name   = "stm32_ltdc",
 401         .id     = UCLASS_VIDEO,
 402         .of_match = stm32_ltdc_ids,
 403         .probe  = stm32_ltdc_probe,
 404         .bind   = stm32_ltdc_bind,
 405         .priv_auto_alloc_size   = sizeof(struct stm32_ltdc_priv),
 406 };