drivers/video/sunxi/sunxi_de2.c

   1 /*
   2  * Allwinner DE2 display driver
   3  *
   4  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <display.h>
  11 #include <dm.h>
  12 #include <edid.h>
  13 #include <fdtdec.h>
  14 #include <fdt_support.h>
  15 #include <video.h>
  16 #include <asm/global_data.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/display2.h>
  20 #include <dm/device-internal.h>
  21 #include <dm/uclass-internal.h>
  22 #include "simplefb_common.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 enum {
  27         /* Maximum LCD size we support */
  28         LCD_MAX_WIDTH           = 3840,
  29         LCD_MAX_HEIGHT          = 2160,
  30         LCD_MAX_LOG2_BPP        = VIDEO_BPP32,
  31 };
  32
  33 static void sunxi_de2_composer_init(void)
  34 {
  35         struct sunxi_ccm_reg * const ccm =
  36                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  37
  38 #ifdef CONFIG_MACH_SUN50I
  39         u32 reg_value;
  40
  41         /* set SRAM for video use (A64 only) */
  42         reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
  43         reg_value &= ~(0x01 << 24);
  44         writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
  45 #endif
  46
  47         clock_set_pll10(432000000);
  48
  49         /* Set DE parent to pll10 */
  50         clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
  51                         CCM_DE2_CTRL_PLL10);
  52
  53         /* Set ahb gating to pass */
  54         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
  55         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
  56
  57         /* Clock on */
  58         setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE);
  59 }
  60
  61 static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
  62                                int bpp, ulong address, bool is_composite)
  63 {
  64         ulong de_mux_base = (mux == 0) ?
  65                             SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
  66         struct de_clk * const de_clk_regs =
  67                 (struct de_clk *)(SUNXI_DE2_BASE);
  68         struct de_glb * const de_glb_regs =
  69                 (struct de_glb *)(de_mux_base +
  70                                   SUNXI_DE2_MUX_GLB_REGS);
  71         struct de_bld * const de_bld_regs =
  72                 (struct de_bld *)(de_mux_base +
  73                                   SUNXI_DE2_MUX_BLD_REGS);
  74         struct de_ui * const de_ui_regs =
  75                 (struct de_ui *)(de_mux_base +
  76                                  SUNXI_DE2_MUX_CHAN_REGS +
  77                                  SUNXI_DE2_MUX_CHAN_SZ * 1);
  78         struct de_csc * const de_csc_regs =
  79                 (struct de_csc *)(de_mux_base +
  80                                   SUNXI_DE2_MUX_DCSC_REGS);
  81         u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
  82         int channel;
  83         u32 format;
  84
  85         /* enable clock */
  86 #ifdef CONFIG_MACH_SUN8I_H3
  87         setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
  88 #else
  89         setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));
  90 #endif
  91         setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));
  92         setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));
  93
  94         clrbits_le32(&de_clk_regs->sel_cfg, 1);
  95
  96         writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl);
  97         writel(0, &de_glb_regs->status);
  98         writel(1, &de_glb_regs->dbuff);
  99         writel(size, &de_glb_regs->size);
 100
 101         for (channel = 0; channel < 4; channel++) {
 102                 void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
 103                                     SUNXI_DE2_MUX_CHAN_SZ * channel);
 104                 memset(ch, 0, (channel == 0) ?
 105                         sizeof(struct de_vi) : sizeof(struct de_ui));
 106         }
 107         memset(de_bld_regs, 0, sizeof(struct de_bld));
 108
 109         writel(0x00000101, &de_bld_regs->fcolor_ctl);
 110
 111         writel(1, &de_bld_regs->route);
 112
 113         writel(0, &de_bld_regs->premultiply);
 114         writel(0xff000000, &de_bld_regs->bkcolor);
 115
 116         writel(0x03010301, &de_bld_regs->bld_mode[0]);
 117
 118         writel(size, &de_bld_regs->output_size);
 119         writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
 120                &de_bld_regs->out_ctl);
 121         writel(0, &de_bld_regs->ck_ctl);
 122
 123         writel(0xff000000, &de_bld_regs->attr[0].fcolor);
 124         writel(size, &de_bld_regs->attr[0].insize);
 125
 126         /* Disable all other units */
 127         writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS);
 128         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS);
 129         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS);
 130         writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS);
 131         writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS);
 132         writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS);
 133         writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS);
 134         writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
 135         writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
 136         writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
 137
 138         if (is_composite) {
 139                 /* set CSC coefficients */
 140                 writel(0x107, &de_csc_regs->coef11);
 141                 writel(0x204, &de_csc_regs->coef12);
 142                 writel(0x64, &de_csc_regs->coef13);
 143                 writel(0x4200, &de_csc_regs->coef14);
 144                 writel(0x1f68, &de_csc_regs->coef21);
 145                 writel(0x1ed6, &de_csc_regs->coef22);
 146                 writel(0x1c2, &de_csc_regs->coef23);
 147                 writel(0x20200, &de_csc_regs->coef24);
 148                 writel(0x1c2, &de_csc_regs->coef31);
 149                 writel(0x1e87, &de_csc_regs->coef32);
 150                 writel(0x1fb7, &de_csc_regs->coef33);
 151                 writel(0x20200, &de_csc_regs->coef34);
 152
 153                 /* enable CSC unit */
 154                 writel(1, &de_csc_regs->csc_ctl);
 155         } else {
 156                 writel(0, &de_csc_regs->csc_ctl);
 157         }
 158
 159         switch (bpp) {
 160         case 16:
 161                 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565);
 162                 break;
 163         case 32:
 164         default:
 165                 format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888);
 166                 break;
 167         }
 168
 169         writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr);
 170         writel(size, &de_ui_regs->cfg[0].size);
 171         writel(0, &de_ui_regs->cfg[0].coord);
 172         writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch);
 173         writel(address, &de_ui_regs->cfg[0].top_laddr);
 174         writel(size, &de_ui_regs->ovl_size);
 175
 176         /* apply settings */
 177         writel(1, &de_glb_regs->dbuff);
 178 }
 179
 180 static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
 181                           enum video_log2_bpp l2bpp,
 182                           struct udevice *disp, int mux, bool is_composite)
 183 {
 184         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 185         struct display_timing timing;
 186         struct display_plat *disp_uc_plat;
 187         int ret;
 188
 189         disp_uc_plat = dev_get_uclass_platdata(disp);
 190         debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
 191         if (display_in_use(disp)) {
 192                 debug("   - device in use\n");
 193                 return -EBUSY;
 194         }
 195
 196         disp_uc_plat->source_id = mux;
 197
 198         ret = device_probe(disp);
 199         if (ret) {
 200                 debug("%s: device '%s' display won't probe (ret=%d)\n",
 201                       __func__, dev->name, ret);
 202                 return ret;
 203         }
 204
 205         ret = display_read_timing(disp, &timing);
 206         if (ret) {
 207                 debug("%s: Failed to read timings\n", __func__);
 208                 return ret;
 209         }
 210
 211         sunxi_de2_composer_init();
 212         sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
 213
 214         ret = display_enable(disp, 1 << l2bpp, &timing);
 215         if (ret) {
 216                 debug("%s: Failed to enable display\n", __func__);
 217                 return ret;
 218         }
 219
 220         uc_priv->xsize = timing.hactive.typ;
 221         uc_priv->ysize = timing.vactive.typ;
 222         uc_priv->bpix = l2bpp;
 223         debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
 224
 225         return 0;
 226 }
 227
 228 static int sunxi_de2_probe(struct udevice *dev)
 229 {
 230         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 231         struct udevice *disp;
 232         int ret;
 233
 234         /* Before relocation we don't need to do anything */
 235         if (!(gd->flags & GD_FLG_RELOC))
 236                 return 0;
 237
 238         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 239                                          "sunxi_lcd", &disp);
 240         if (!ret) {
 241                 int mux;
 242
 243                 mux = 0;
 244
 245                 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
 246                                      false);
 247                 if (!ret) {
 248                         video_set_flush_dcache(dev, 1);
 249                         return 0;
 250                 }
 251         }
 252
 253         debug("%s: lcd display not found (ret=%d)\n", __func__, ret);
 254
 255         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 256                                          "sunxi_dw_hdmi", &disp);
 257         if (!ret) {
 258                 int mux;
 259                 if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
 260                         mux = 0;
 261                 else
 262                         mux = 1;
 263
 264                 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
 265                                      false);
 266                 if (!ret) {
 267                         video_set_flush_dcache(dev, 1);
 268                         return 0;
 269                 }
 270         }
 271
 272         debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
 273
 274         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 275                                         "sunxi_tve", &disp);
 276         if (ret) {
 277                 debug("%s: tv not found (ret=%d)\n", __func__, ret);
 278                 return ret;
 279         }
 280
 281         ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true);
 282         if (ret)
 283                 return ret;
 284
 285         video_set_flush_dcache(dev, 1);
 286
 287         return 0;
 288 }
 289
 290 static int sunxi_de2_bind(struct udevice *dev)
 291 {
 292         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 293
 294         plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 295                 (1 << LCD_MAX_LOG2_BPP) / 8;
 296
 297         return 0;
 298 }
 299
 300 static const struct video_ops sunxi_de2_ops = {
 301 };
 302
 303 U_BOOT_DRIVER(sunxi_de2) = {
 304         .name   = "sunxi_de2",
 305         .id     = UCLASS_VIDEO,
 306         .ops    = &sunxi_de2_ops,
 307         .bind   = sunxi_de2_bind,
 308         .probe  = sunxi_de2_probe,
 309         .flags  = DM_FLAG_PRE_RELOC,
 310 };
 311
 312 U_BOOT_DEVICE(sunxi_de2) = {
 313         .name = "sunxi_de2"
 314 };
 315
 316 /*
 317  * Simplefb support.
 318  */
 319 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
 320 int sunxi_simplefb_setup(void *blob)
 321 {
 322         struct udevice *de2, *hdmi;
 323         struct video_priv *de2_priv;
 324         struct video_uc_platdata *de2_plat;
 325         int mux;
 326         int offset, ret;
 327         u64 start, size;
 328         const char *pipeline = NULL;
 329
 330         debug("Setting up simplefb\n");
 331
 332         if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
 333                 mux = 0;
 334         else
 335                 mux = 1;
 336
 337         /* Skip simplefb setting if DE2 / HDMI is not present */
 338         ret = uclass_find_device_by_name(UCLASS_VIDEO,
 339                                          "sunxi_de2", &de2);
 340         if (ret) {
 341                 debug("DE2 not present\n");
 342                 return 0;
 343         }
 344
 345         ret = uclass_find_device_by_name(UCLASS_DISPLAY,
 346                                          "sunxi_dw_hdmi", &hdmi);
 347         if (ret) {
 348                 debug("HDMI not present\n");
 349                 return 0;
 350         }
 351
 352         if (mux == 0)
 353                 pipeline = "mixer0-lcd0-hdmi";
 354         else
 355                 pipeline = "mixer1-lcd1-hdmi";
 356
 357         de2_priv = dev_get_uclass_priv(de2);
 358         de2_plat = dev_get_uclass_platdata(de2);
 359
 360         offset = sunxi_simplefb_fdt_match(blob, pipeline);
 361         if (offset < 0) {
 362                 eprintf("Cannot setup simplefb: node not found\n");
 363                 return 0; /* Keep older kernels working */
 364         }
 365
 366         start = gd->bd->bi_dram[0].start;
 367         size = de2_plat->base - start;
 368         ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
 369         if (ret) {
 370                 eprintf("Cannot setup simplefb: Error reserving memory\n");
 371                 return ret;
 372         }
 373
 374         ret = fdt_setup_simplefb_node(blob, offset, de2_plat->base,
 375                         de2_priv->xsize, de2_priv->ysize,
 376                         VNBYTES(de2_priv->bpix) * de2_priv->xsize,
 377                         "x8r8g8b8");
 378         if (ret)
 379                 eprintf("Cannot setup simplefb: Error setting properties\n");
 380
 381         return ret;
 382 }
 383 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */