drivers/watchdog/xilinx_tb_wdt.c

   1 /*
   2  * Copyright (c) 2011-2013 Xilinx Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/microblaze_intc.h>
  10 #include <asm/processor.h>
  11 #include <watchdog.h>
  12
  13 #define XWT_CSR0_WRS_MASK       0x00000008 /* Reset status Mask */
  14 #define XWT_CSR0_WDS_MASK       0x00000004 /* Timer state Mask */
  15 #define XWT_CSR0_EWDT1_MASK     0x00000002 /* Enable bit 1 Mask*/
  16 #define XWT_CSRX_EWDT2_MASK     0x00000001 /* Enable bit 2 Mask */
  17
  18 struct watchdog_regs {
  19         u32 twcsr0; /* 0x0 */
  20         u32 twcsr1; /* 0x4 */
  21         u32 tbr; /* 0x8 */
  22 };
  23
  24 static struct watchdog_regs *watchdog_base =
  25                         (struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR;
  26
  27 void hw_watchdog_reset(void)
  28 {
  29         u32 reg;
  30
  31         /* Read the current contents of TCSR0 */
  32         reg = readl(&watchdog_base->twcsr0);
  33
  34         /* Clear the watchdog WDS bit */
  35         if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
  36                 writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0);
  37 }
  38
  39 void hw_watchdog_disable(void)
  40 {
  41         u32 reg;
  42
  43         /* Read the current contents of TCSR0 */
  44         reg = readl(&watchdog_base->twcsr0);
  45
  46         writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0);
  47         writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
  48
  49         puts("Watchdog disabled!\n");
  50 }
  51
  52 static void hw_watchdog_isr(void *arg)
  53 {
  54         hw_watchdog_reset();
  55 }
  56
  57 int hw_watchdog_init(void)
  58 {
  59         int ret;
  60
  61         writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
  62                &watchdog_base->twcsr0);
  63         writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1);
  64
  65         ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ,
  66                                                 hw_watchdog_isr, NULL);
  67         if (ret)
  68                 return 1;
  69
  70         return 0;
  71 }