examples/standalone/test_burst_lib.S

   1 /*
   2  * (C) Copyright 2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <config.h>
   9
  10 #include <ppc_asm.tmpl>
  11 #include <ppc_defs.h>
  12 #include <asm/cache.h>
  13 #include <asm/mmu.h>
  14 #include "test_burst.h"
  15
  16         .text
  17 /*
  18  *      void mmu_init(void);
  19  *
  20  *      This function turns the MMU on
  21  *
  22  *      Three 8 MByte regions are mapped 1:1, uncached
  23  *      - SDRAM lower 8 MByte
  24  *      - SDRAM higher 8 MByte
  25  *      - IMMR
  26  */
  27         .global mmu_init
  28 mmu_init:
  29         tlbia                   /* Invalidate all TLB entries */
  30         li      r8, 0
  31         mtspr   MI_CTR, r8      /* Set instruction control to zero */
  32         lis     r8, MD_RESETVAL@h
  33         mtspr   MD_CTR, r8      /* Set data TLB control */
  34
  35         /* Now map the lower 8 Meg into the TLBs.  For this quick hack,
  36          * we can load the instruction and data TLB registers with the
  37          * same values.
  38          */
  39         li      r8, MI_EVALID           /* Create EPN for address 0 */
  40         mtspr   MI_EPN, r8
  41         mtspr   MD_EPN, r8
  42         li      r8, MI_PS8MEG           /* Set 8M byte page */
  43         ori     r8, r8, MI_SVALID       /* Make it valid */
  44         mtspr   MI_TWC, r8
  45         mtspr   MD_TWC, r8
  46         li      r8, MI_BOOTINIT|0x2     /* Create RPN for address 0 */
  47         mtspr   MI_RPN, r8              /* Store TLB entry */
  48         mtspr   MD_RPN, r8
  49         lis     r8, MI_Kp@h             /* Set the protection mode */
  50         mtspr   MI_AP, r8
  51         mtspr   MD_AP, r8
  52
  53         /* Now map the higher 8 Meg into the TLBs.  For this quick hack,
  54          * we can load the instruction and data TLB registers with the
  55          * same values.
  56          */
  57         lwz     r9,20(r2)               /* gd->ram_size */
  58         addis   r9,r9,-0x80
  59
  60         mr      r8, r9                  /* Higher 8 Meg in SDRAM */
  61         ori     r8, r8, MI_EVALID       /* Mark page valid */
  62         mtspr   MI_EPN, r8
  63         mtspr   MD_EPN, r8
  64         li      r8, MI_PS8MEG           /* Set 8M byte page */
  65         ori     r8, r8, MI_SVALID       /* Make it valid */
  66         mtspr   MI_TWC, r8
  67         mtspr   MD_TWC, r8
  68         mr      r8, r9
  69         ori     r8, r8, MI_BOOTINIT|0x2
  70         mtspr   MI_RPN, r8              /* Store TLB entry */
  71         mtspr   MD_RPN, r8
  72         lis     r8, MI_Kp@h             /* Set the protection mode */
  73         mtspr   MI_AP, r8
  74         mtspr   MD_AP, r8
  75
  76         /* Map another 8 MByte at the IMMR to get the processor
  77          * internal registers (among other things).
  78          */
  79         mfspr   r9, 638                 /* Get current IMMR */
  80         andis.  r9, r9, 0xff80          /* Get 8Mbyte boundary */
  81
  82         mr      r8, r9                  /* Create vaddr for TLB */
  83         ori     r8, r8, MD_EVALID       /* Mark it valid */
  84         mtspr   MD_EPN, r8
  85         li      r8, MD_PS8MEG           /* Set 8M byte page */
  86         ori     r8, r8, MD_SVALID       /* Make it valid */
  87         mtspr   MD_TWC, r8
  88         mr      r8, r9                  /* Create paddr for TLB */
  89         ori     r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
  90         mtspr   MD_RPN, r8
  91
  92         /* We now have the lower and higher 8 Meg mapped into TLB entries,
  93          * and the caches ready to work.
  94          */
  95         mfmsr   r0
  96         ori     r0,r0,MSR_DR|MSR_IR
  97         mtspr   SRR1,r0
  98         mflr    r0
  99         mtspr   SRR0,r0
 100         SYNC
 101         rfi     /* enables MMU */
 102
 103 /*
 104  *      void caches_init(void);
 105  */
 106         .globl  caches_init
 107 caches_init:
 108         sync
 109
 110         mfspr   r3, IC_CST              /* Clear error bits */
 111         mfspr   r3, DC_CST
 112
 113         lis     r3, IDC_UNALL@h         /* Unlock all */
 114         mtspr   IC_CST, r3
 115         mtspr   DC_CST, r3
 116
 117         lis     r3, IDC_INVALL@h        /* Invalidate all */
 118         mtspr   IC_CST, r3
 119         mtspr   DC_CST, r3
 120
 121         lis     r3, IDC_ENABLE@h        /* Enable all */
 122         mtspr   IC_CST, r3
 123         mtspr   DC_CST, r3
 124
 125         blr
 126
 127 /*
 128  *      void flush_dcache_range(unsigned long start, unsigned long stop);
 129  */
 130         .global flush_dcache_range
 131 flush_dcache_range:
 132         li      r5,CACHE_LINE_SIZE-1
 133         andc    r3,r3,r5
 134         subf    r4,r3,r4
 135         add     r4,r4,r5
 136         srwi.   r4,r4,LG_CACHE_LINE_SIZE
 137         beqlr
 138         mtctr   r4
 139
 140 1:      dcbf    0,r3
 141         addi    r3,r3,CACHE_LINE_SIZE
 142         bdnz    1b
 143         sync                            /* wait for dcbf's to get to ram */
 144         blr
 145
 146 /*
 147  *      void disable_interrupts(void);
 148  */
 149         .global disable_interrupts
 150 disable_interrupts:
 151         mfmsr   r0
 152         rlwinm  r0,r0,0,17,15
 153         mtmsr   r0
 154         blr