include/4xx_i2c.h

   1 /*
   2  * (C) Copyright 2007-2009
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef _4xx_i2c_h_
  25 #define _4xx_i2c_h_
  26
  27 #define IIC_OK          0
  28 #define IIC_NOK         1
  29 #define IIC_NOK_LA      2               /* Lost arbitration */
  30 #define IIC_NOK_ICT     3               /* Incomplete transfer */
  31 #define IIC_NOK_XFRA    4               /* Transfer aborted */
  32 #define IIC_NOK_DATA    5               /* No data in buffer */
  33 #define IIC_NOK_TOUT    6               /* Transfer timeout */
  34
  35 #define IIC_TIMEOUT     1               /* 1 second */
  36
  37 #if defined(CONFIG_I2C_MULTI_BUS)
  38 #define I2C_BUS_OFFS    (i2c_bus_num * 0x100)
  39 #else
  40 #define I2C_BUS_OFFS    (0x000)
  41 #endif /* CONFIG_I2C_MULTI_BUS */
  42
  43 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  44     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  45     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  46 #define I2C_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
  47 #elif defined(CONFIG_440) || defined(CONFIG_405EX)
  48 /* all remaining 440 variants */
  49 #define I2C_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
  50 #else
  51 /* all 405 variants */
  52 #define I2C_BASE_ADDR   (0xEF600500 + I2C_BUS_OFFS)
  53 #endif
  54
  55 struct ppc4xx_i2c {
  56         u8 mdbuf;
  57         u8 res1;
  58         u8 sdbuf;
  59         u8 res2;
  60         u8 lmadr;
  61         u8 hmadr;
  62         u8 cntl;
  63         u8 mdcntl;
  64         u8 sts;
  65         u8 extsts;
  66         u8 lsadr;
  67         u8 hsadr;
  68         u8 clkdiv;
  69         u8 intrmsk;
  70         u8 xfrcnt;
  71         u8 xtcntlss;
  72         u8 directcntl;
  73         u8 intr;
  74 };
  75
  76 /* MDCNTL Register Bit definition */
  77 #define IIC_MDCNTL_HSCL         0x01
  78 #define IIC_MDCNTL_EUBS         0x02
  79 #define IIC_MDCNTL_EINT         0x04
  80 #define IIC_MDCNTL_ESM          0x08
  81 #define IIC_MDCNTL_FSM          0x10
  82 #define IIC_MDCNTL_EGC          0x20
  83 #define IIC_MDCNTL_FMDB         0x40
  84 #define IIC_MDCNTL_FSDB         0x80
  85
  86 /* CNTL Register Bit definition */
  87 #define IIC_CNTL_PT             0x01
  88 #define IIC_CNTL_READ           0x02
  89 #define IIC_CNTL_CHT            0x04
  90 #define IIC_CNTL_RPST           0x08
  91 /* bit 2/3 for Transfer count*/
  92 #define IIC_CNTL_AMD            0x40
  93 #define IIC_CNTL_HMT            0x80
  94
  95 /* STS Register Bit definition */
  96 #define IIC_STS_PT              0x01
  97 #define IIC_STS_IRQA            0x02
  98 #define IIC_STS_ERR             0x04
  99 #define IIC_STS_SCMP            0x08
 100 #define IIC_STS_MDBF            0x10
 101 #define IIC_STS_MDBS            0x20
 102 #define IIC_STS_SLPR            0x40
 103 #define IIC_STS_SSS             0x80
 104
 105 /* EXTSTS Register Bit definition */
 106 #define IIC_EXTSTS_XFRA         0x01
 107 #define IIC_EXTSTS_ICT          0x02
 108 #define IIC_EXTSTS_LA           0x04
 109
 110 /* XTCNTLSS Register Bit definition */
 111 #define IIC_XTCNTLSS_SRST       0x01
 112 #define IIC_XTCNTLSS_EPI        0x02
 113 #define IIC_XTCNTLSS_SDBF       0x04
 114 #define IIC_XTCNTLSS_SBDD       0x08
 115 #define IIC_XTCNTLSS_SWS        0x10
 116 #define IIC_XTCNTLSS_SWC        0x20
 117 #define IIC_XTCNTLSS_SRS        0x40
 118 #define IIC_XTCNTLSS_SRC        0x80
 119
 120 /* IICx_DIRECTCNTL register */
 121 #define IIC_DIRCNTL_SDAC        0x08
 122 #define IIC_DIRCNTL_SCC         0x04
 123 #define IIC_DIRCNTL_MSDA        0x02
 124 #define IIC_DIRCNTL_MSC         0x01
 125
 126 #define DIRCTNL_FREE(v)         (((v) & 0x0f) == 0x0f)
 127 #endif